1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "ARMGenRegisterInfo.inc"
48 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49 cl::desc("Force use of virtual base registers for stack load/store"));
51 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58 const ARMSubtarget &sti)
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66 static const unsigned CalleeSavedRegs[] = {
67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
68 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
70 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
71 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
75 static const unsigned iOSCalleeSavedRegs[] = {
76 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
79 ARM::R11, ARM::R10, ARM::R8,
81 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
82 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
85 return (STI.isTargetIOS()) ? iOSCalleeSavedRegs : CalleeSavedRegs;
88 BitVector ARMBaseRegisterInfo::
89 getReservedRegs(const MachineFunction &MF) const {
90 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
92 // FIXME: avoid re-calculating this every time.
93 BitVector Reserved(getNumRegs());
94 Reserved.set(ARM::SP);
95 Reserved.set(ARM::PC);
96 Reserved.set(ARM::FPSCR);
98 Reserved.set(FramePtr);
99 if (hasBasePointer(MF))
100 Reserved.set(BasePtr);
101 // Some targets reserve R9.
102 if (STI.isR9Reserved())
103 Reserved.set(ARM::R9);
104 // Reserve D16-D31 if the subtarget doesn't support them.
105 if (!STI.hasVFP3() || STI.hasD16()) {
106 assert(ARM::D31 == ARM::D16 + 15);
107 for (unsigned i = 0; i != 16; ++i)
108 Reserved.set(ARM::D16 + i);
113 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
114 unsigned Reg) const {
115 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
123 if (hasBasePointer(MF))
128 if (FramePtr == Reg && TFI->hasFP(MF))
132 return STI.isR9Reserved();
139 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
140 SmallVectorImpl<unsigned> &SubIndices,
141 unsigned &NewSubIdx) const {
143 unsigned Size = RC->getSize() * 8;
147 NewSubIdx = 0; // Whole register.
148 unsigned NumRegs = SubIndices.size();
150 // 8 D registers -> 1 QQQQ register.
151 return (Size == 512 &&
152 SubIndices[0] == ARM::dsub_0 &&
153 SubIndices[1] == ARM::dsub_1 &&
154 SubIndices[2] == ARM::dsub_2 &&
155 SubIndices[3] == ARM::dsub_3 &&
156 SubIndices[4] == ARM::dsub_4 &&
157 SubIndices[5] == ARM::dsub_5 &&
158 SubIndices[6] == ARM::dsub_6 &&
159 SubIndices[7] == ARM::dsub_7);
160 } else if (NumRegs == 4) {
161 if (SubIndices[0] == ARM::qsub_0) {
162 // 4 Q registers -> 1 QQQQ register.
163 return (Size == 512 &&
164 SubIndices[1] == ARM::qsub_1 &&
165 SubIndices[2] == ARM::qsub_2 &&
166 SubIndices[3] == ARM::qsub_3);
167 } else if (SubIndices[0] == ARM::dsub_0) {
168 // 4 D registers -> 1 QQ register.
170 SubIndices[1] == ARM::dsub_1 &&
171 SubIndices[2] == ARM::dsub_2 &&
172 SubIndices[3] == ARM::dsub_3) {
174 NewSubIdx = ARM::qqsub_0;
177 } else if (SubIndices[0] == ARM::dsub_4) {
178 // 4 D registers -> 1 QQ register (2nd).
180 SubIndices[1] == ARM::dsub_5 &&
181 SubIndices[2] == ARM::dsub_6 &&
182 SubIndices[3] == ARM::dsub_7) {
183 NewSubIdx = ARM::qqsub_1;
186 } else if (SubIndices[0] == ARM::ssub_0) {
187 // 4 S registers -> 1 Q register.
189 SubIndices[1] == ARM::ssub_1 &&
190 SubIndices[2] == ARM::ssub_2 &&
191 SubIndices[3] == ARM::ssub_3) {
193 NewSubIdx = ARM::qsub_0;
197 } else if (NumRegs == 2) {
198 if (SubIndices[0] == ARM::qsub_0) {
199 // 2 Q registers -> 1 QQ register.
200 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
202 NewSubIdx = ARM::qqsub_0;
205 } else if (SubIndices[0] == ARM::qsub_2) {
206 // 2 Q registers -> 1 QQ register (2nd).
207 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
208 NewSubIdx = ARM::qqsub_1;
211 } else if (SubIndices[0] == ARM::dsub_0) {
212 // 2 D registers -> 1 Q register.
213 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
215 NewSubIdx = ARM::qsub_0;
218 } else if (SubIndices[0] == ARM::dsub_2) {
219 // 2 D registers -> 1 Q register (2nd).
220 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
221 NewSubIdx = ARM::qsub_1;
224 } else if (SubIndices[0] == ARM::dsub_4) {
225 // 2 D registers -> 1 Q register (3rd).
226 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
227 NewSubIdx = ARM::qsub_2;
230 } else if (SubIndices[0] == ARM::dsub_6) {
231 // 2 D registers -> 1 Q register (3rd).
232 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
233 NewSubIdx = ARM::qsub_3;
236 } else if (SubIndices[0] == ARM::ssub_0) {
237 // 2 S registers -> 1 D register.
238 if (SubIndices[1] == ARM::ssub_1) {
240 NewSubIdx = ARM::dsub_0;
243 } else if (SubIndices[0] == ARM::ssub_2) {
244 // 2 S registers -> 1 D register (2nd).
245 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
246 NewSubIdx = ARM::dsub_1;
254 const TargetRegisterClass*
255 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
257 const TargetRegisterClass *Super = RC;
258 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
260 switch (Super->getID()) {
261 case ARM::GPRRegClassID:
262 case ARM::SPRRegClassID:
263 case ARM::DPRRegClassID:
264 case ARM::QPRRegClassID:
265 case ARM::QQPRRegClassID:
266 case ARM::QQQQPRRegClassID:
274 const TargetRegisterClass *
275 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
276 return ARM::GPRRegisterClass;
279 const TargetRegisterClass *
280 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
281 if (RC == &ARM::CCRRegClass)
282 return 0; // Can't copy CCR registers.
287 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
288 MachineFunction &MF) const {
289 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
291 switch (RC->getID()) {
294 case ARM::tGPRRegClassID:
295 return TFI->hasFP(MF) ? 4 : 5;
296 case ARM::GPRRegClassID: {
297 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
298 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
300 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
301 case ARM::DPRRegClassID:
306 /// getRawAllocationOrder - Returns the register allocation order for a
307 /// specified register class with a target-dependent hint.
309 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
310 unsigned HintType, unsigned HintReg,
311 const MachineFunction &MF) const {
312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
313 // Alternative register allocation orders when favoring even / odd registers
314 // of register pairs.
316 // No FP, R9 is available.
317 static const unsigned GPREven1[] = {
318 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
322 static const unsigned GPROdd1[] = {
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
328 // FP is R7, R9 is available.
329 static const unsigned GPREven2[] = {
330 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
334 static const unsigned GPROdd2[] = {
335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
340 // FP is R11, R9 is available.
341 static const unsigned GPREven3[] = {
342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
346 static const unsigned GPROdd3[] = {
347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
352 // No FP, R9 is not available.
353 static const unsigned GPREven4[] = {
354 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
358 static const unsigned GPROdd4[] = {
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
364 // FP is R7, R9 is not available.
365 static const unsigned GPREven5[] = {
366 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
370 static const unsigned GPROdd5[] = {
371 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
372 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
376 // FP is R11, R9 is not available.
377 static const unsigned GPREven6[] = {
378 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
379 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
381 static const unsigned GPROdd6[] = {
382 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
383 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
386 // We only support even/odd hints for GPR and rGPR.
387 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
388 return RC->getRawAllocationOrder(MF);
390 if (HintType == ARMRI::RegPairEven) {
391 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
392 // It's no longer possible to fulfill this hint. Return the default
394 return RC->getRawAllocationOrder(MF);
396 if (!TFI->hasFP(MF)) {
397 if (!STI.isR9Reserved())
398 return makeArrayRef(GPREven1);
400 return makeArrayRef(GPREven4);
401 } else if (FramePtr == ARM::R7) {
402 if (!STI.isR9Reserved())
403 return makeArrayRef(GPREven2);
405 return makeArrayRef(GPREven5);
406 } else { // FramePtr == ARM::R11
407 if (!STI.isR9Reserved())
408 return makeArrayRef(GPREven3);
410 return makeArrayRef(GPREven6);
412 } else if (HintType == ARMRI::RegPairOdd) {
413 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
414 // It's no longer possible to fulfill this hint. Return the default
416 return RC->getRawAllocationOrder(MF);
418 if (!TFI->hasFP(MF)) {
419 if (!STI.isR9Reserved())
420 return makeArrayRef(GPROdd1);
422 return makeArrayRef(GPROdd4);
423 } else if (FramePtr == ARM::R7) {
424 if (!STI.isR9Reserved())
425 return makeArrayRef(GPROdd2);
427 return makeArrayRef(GPROdd5);
428 } else { // FramePtr == ARM::R11
429 if (!STI.isR9Reserved())
430 return makeArrayRef(GPROdd3);
432 return makeArrayRef(GPROdd6);
435 return RC->getRawAllocationOrder(MF);
438 /// ResolveRegAllocHint - Resolves the specified register allocation hint
439 /// to a physical register. Returns the physical register if it is successful.
441 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
442 const MachineFunction &MF) const {
443 if (Reg == 0 || !isPhysicalRegister(Reg))
447 else if (Type == (unsigned)ARMRI::RegPairOdd)
449 return getRegisterPairOdd(Reg, MF);
450 else if (Type == (unsigned)ARMRI::RegPairEven)
452 return getRegisterPairEven(Reg, MF);
457 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
458 MachineFunction &MF) const {
459 MachineRegisterInfo *MRI = &MF.getRegInfo();
460 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
461 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
462 Hint.first == (unsigned)ARMRI::RegPairEven) &&
463 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
464 // If 'Reg' is one of the even / odd register pair and it's now changed
465 // (e.g. coalesced) into a different register. The other register of the
466 // pair allocation hint must be updated to reflect the relationship
468 unsigned OtherReg = Hint.second;
469 Hint = MRI->getRegAllocationHint(OtherReg);
470 if (Hint.second == Reg)
471 // Make sure the pair has not already divorced.
472 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
477 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
478 // CortexA9 has a Write-after-write hazard for NEON registers.
479 if (!STI.isCortexA9())
482 switch (RC->getID()) {
483 case ARM::DPRRegClassID:
484 case ARM::DPR_8RegClassID:
485 case ARM::DPR_VFP2RegClassID:
486 case ARM::QPRRegClassID:
487 case ARM::QPR_8RegClassID:
488 case ARM::QPR_VFP2RegClassID:
489 case ARM::SPRRegClassID:
490 case ARM::SPR_8RegClassID:
491 // Avoid reusing S, D, and Q registers.
492 // Don't increase register pressure for QQ and QQQQ.
499 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
500 const MachineFrameInfo *MFI = MF.getFrameInfo();
501 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
503 if (!EnableBasePointer)
506 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
509 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
510 // negative range for ldr/str (255), and thumb1 is positive offsets only.
511 // It's going to be better to use the SP or Base Pointer instead. When there
512 // are variable sized objects, we can't reference off of the SP, so we
513 // reserve a Base Pointer.
514 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
515 // Conservatively estimate whether the negative offset from the frame
516 // pointer will be sufficient to reach. If a function has a smallish
517 // frame, it's less likely to have lots of spills and callee saved
518 // space, so it's all more likely to be within range of the frame pointer.
519 // If it's wrong, the scavenger will still enable access to work, it just
521 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
529 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
530 const MachineFrameInfo *MFI = MF.getFrameInfo();
531 const MachineRegisterInfo *MRI = &MF.getRegInfo();
532 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
533 // We can't realign the stack if:
534 // 1. Dynamic stack realignment is explicitly disabled,
535 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
536 // 3. There are VLAs in the function and the base pointer is disabled.
537 if (!MF.getTarget().Options.RealignStack)
539 if (AFI->isThumb1OnlyFunction())
541 // Stack realignment requires a frame pointer. If we already started
542 // register allocation with frame pointer elimination, it is too late now.
543 if (!MRI->canReserveReg(FramePtr))
545 // We may also need a base pointer if there are dynamic allocas.
546 if (!MFI->hasVarSizedObjects())
548 if (!EnableBasePointer)
550 // A base pointer is required and allowed. Check that it isn't too late to
552 return MRI->canReserveReg(BasePtr);
555 bool ARMBaseRegisterInfo::
556 needsStackRealignment(const MachineFunction &MF) const {
557 const MachineFrameInfo *MFI = MF.getFrameInfo();
558 const Function *F = MF.getFunction();
559 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
560 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
561 F->hasFnAttr(Attribute::StackAlignment));
563 return requiresRealignment && canRealignStack(MF);
566 bool ARMBaseRegisterInfo::
567 cannotEliminateFrame(const MachineFunction &MF) const {
568 const MachineFrameInfo *MFI = MF.getFrameInfo();
569 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
571 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
572 || needsStackRealignment(MF);
576 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
577 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
584 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
585 llvm_unreachable("What is the exception register");
589 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
590 llvm_unreachable("What is the exception handler register");
594 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
595 const MachineFunction &MF) const {
598 // Return 0 if either register of the pair is a special register.
600 case ARM::R1: return ARM::R0;
601 case ARM::R3: return ARM::R2;
602 case ARM::R5: return ARM::R4;
604 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
606 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
607 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
609 case ARM::S1: return ARM::S0;
610 case ARM::S3: return ARM::S2;
611 case ARM::S5: return ARM::S4;
612 case ARM::S7: return ARM::S6;
613 case ARM::S9: return ARM::S8;
614 case ARM::S11: return ARM::S10;
615 case ARM::S13: return ARM::S12;
616 case ARM::S15: return ARM::S14;
617 case ARM::S17: return ARM::S16;
618 case ARM::S19: return ARM::S18;
619 case ARM::S21: return ARM::S20;
620 case ARM::S23: return ARM::S22;
621 case ARM::S25: return ARM::S24;
622 case ARM::S27: return ARM::S26;
623 case ARM::S29: return ARM::S28;
624 case ARM::S31: return ARM::S30;
626 case ARM::D1: return ARM::D0;
627 case ARM::D3: return ARM::D2;
628 case ARM::D5: return ARM::D4;
629 case ARM::D7: return ARM::D6;
630 case ARM::D9: return ARM::D8;
631 case ARM::D11: return ARM::D10;
632 case ARM::D13: return ARM::D12;
633 case ARM::D15: return ARM::D14;
634 case ARM::D17: return ARM::D16;
635 case ARM::D19: return ARM::D18;
636 case ARM::D21: return ARM::D20;
637 case ARM::D23: return ARM::D22;
638 case ARM::D25: return ARM::D24;
639 case ARM::D27: return ARM::D26;
640 case ARM::D29: return ARM::D28;
641 case ARM::D31: return ARM::D30;
647 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
648 const MachineFunction &MF) const {
651 // Return 0 if either register of the pair is a special register.
653 case ARM::R0: return ARM::R1;
654 case ARM::R2: return ARM::R3;
655 case ARM::R4: return ARM::R5;
657 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
659 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
660 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
662 case ARM::S0: return ARM::S1;
663 case ARM::S2: return ARM::S3;
664 case ARM::S4: return ARM::S5;
665 case ARM::S6: return ARM::S7;
666 case ARM::S8: return ARM::S9;
667 case ARM::S10: return ARM::S11;
668 case ARM::S12: return ARM::S13;
669 case ARM::S14: return ARM::S15;
670 case ARM::S16: return ARM::S17;
671 case ARM::S18: return ARM::S19;
672 case ARM::S20: return ARM::S21;
673 case ARM::S22: return ARM::S23;
674 case ARM::S24: return ARM::S25;
675 case ARM::S26: return ARM::S27;
676 case ARM::S28: return ARM::S29;
677 case ARM::S30: return ARM::S31;
679 case ARM::D0: return ARM::D1;
680 case ARM::D2: return ARM::D3;
681 case ARM::D4: return ARM::D5;
682 case ARM::D6: return ARM::D7;
683 case ARM::D8: return ARM::D9;
684 case ARM::D10: return ARM::D11;
685 case ARM::D12: return ARM::D13;
686 case ARM::D14: return ARM::D15;
687 case ARM::D16: return ARM::D17;
688 case ARM::D18: return ARM::D19;
689 case ARM::D20: return ARM::D21;
690 case ARM::D22: return ARM::D23;
691 case ARM::D24: return ARM::D25;
692 case ARM::D26: return ARM::D27;
693 case ARM::D28: return ARM::D29;
694 case ARM::D30: return ARM::D31;
700 /// emitLoadConstPool - Emits a load from constpool to materialize the
701 /// specified immediate.
702 void ARMBaseRegisterInfo::
703 emitLoadConstPool(MachineBasicBlock &MBB,
704 MachineBasicBlock::iterator &MBBI,
706 unsigned DestReg, unsigned SubIdx, int Val,
707 ARMCC::CondCodes Pred,
708 unsigned PredReg, unsigned MIFlags) const {
709 MachineFunction &MF = *MBB.getParent();
710 MachineConstantPool *ConstantPool = MF.getConstantPool();
712 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
713 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
715 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
716 .addReg(DestReg, getDefRegState(true), SubIdx)
717 .addConstantPoolIndex(Idx)
718 .addImm(0).addImm(Pred).addReg(PredReg)
719 .setMIFlags(MIFlags);
722 bool ARMBaseRegisterInfo::
723 requiresRegisterScavenging(const MachineFunction &MF) const {
727 bool ARMBaseRegisterInfo::
728 requiresFrameIndexScavenging(const MachineFunction &MF) const {
732 bool ARMBaseRegisterInfo::
733 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
734 return EnableLocalStackAlloc;
738 emitSPUpdate(bool isARM,
739 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
740 DebugLoc dl, const ARMBaseInstrInfo &TII,
742 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
744 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
747 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
752 void ARMBaseRegisterInfo::
753 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
754 MachineBasicBlock::iterator I) const {
755 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
756 if (!TFI->hasReservedCallFrame(MF)) {
757 // If we have alloca, convert as follows:
758 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
759 // ADJCALLSTACKUP -> add, sp, sp, amount
760 MachineInstr *Old = I;
761 DebugLoc dl = Old->getDebugLoc();
762 unsigned Amount = Old->getOperand(0).getImm();
764 // We need to keep the stack aligned properly. To do this, we round the
765 // amount of space needed for the outgoing arguments up to the next
766 // alignment boundary.
767 unsigned Align = TFI->getStackAlignment();
768 Amount = (Amount+Align-1)/Align*Align;
770 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
771 assert(!AFI->isThumb1OnlyFunction() &&
772 "This eliminateCallFramePseudoInstr does not support Thumb1!");
773 bool isARM = !AFI->isThumbFunction();
775 // Replace the pseudo instruction with a new instruction...
776 unsigned Opc = Old->getOpcode();
777 int PIdx = Old->findFirstPredOperandIdx();
778 ARMCC::CondCodes Pred = (PIdx == -1)
779 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
780 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
781 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
782 unsigned PredReg = Old->getOperand(2).getReg();
783 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
785 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
786 unsigned PredReg = Old->getOperand(3).getReg();
787 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
788 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
795 int64_t ARMBaseRegisterInfo::
796 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
797 const MCInstrDesc &Desc = MI->getDesc();
798 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
799 int64_t InstrOffs = 0;;
803 case ARMII::AddrModeT2_i8:
804 case ARMII::AddrModeT2_i12:
805 case ARMII::AddrMode_i12:
806 InstrOffs = MI->getOperand(Idx+1).getImm();
809 case ARMII::AddrMode5: {
811 const MachineOperand &OffOp = MI->getOperand(Idx+1);
812 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
813 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
814 InstrOffs = -InstrOffs;
818 case ARMII::AddrMode2: {
820 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
821 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
822 InstrOffs = -InstrOffs;
825 case ARMII::AddrMode3: {
827 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
828 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
829 InstrOffs = -InstrOffs;
832 case ARMII::AddrModeT1_s: {
834 InstrOffs = MI->getOperand(ImmIdx).getImm();
839 llvm_unreachable("Unsupported addressing mode!");
843 return InstrOffs * Scale;
846 /// needsFrameBaseReg - Returns true if the instruction's frame index
847 /// reference would be better served by a base register other than FP
848 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
849 /// references it should create new base registers for.
850 bool ARMBaseRegisterInfo::
851 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
852 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
853 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
856 // It's the load/store FI references that cause issues, as it can be difficult
857 // to materialize the offset if it won't fit in the literal field. Estimate
858 // based on the size of the local frame and some conservative assumptions
859 // about the rest of the stack frame (note, this is pre-regalloc, so
860 // we don't know everything for certain yet) whether this offset is likely
861 // to be out of range of the immediate. Return true if so.
863 // We only generate virtual base registers for loads and stores, so
864 // return false for everything else.
865 unsigned Opc = MI->getOpcode();
867 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
868 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
869 case ARM::t2LDRi12: case ARM::t2LDRi8:
870 case ARM::t2STRi12: case ARM::t2STRi8:
871 case ARM::VLDRS: case ARM::VLDRD:
872 case ARM::VSTRS: case ARM::VSTRD:
873 case ARM::tSTRspi: case ARM::tLDRspi:
874 if (ForceAllBaseRegAlloc)
881 // Without a virtual base register, if the function has variable sized
882 // objects, all fixed-size local references will be via the frame pointer,
883 // Approximate the offset and see if it's legal for the instruction.
884 // Note that the incoming offset is based on the SP value at function entry,
885 // so it'll be negative.
886 MachineFunction &MF = *MI->getParent()->getParent();
887 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
888 MachineFrameInfo *MFI = MF.getFrameInfo();
889 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
891 // Estimate an offset from the frame pointer.
892 // Conservatively assume all callee-saved registers get pushed. R4-R6
893 // will be earlier than the FP, so we ignore those.
895 int64_t FPOffset = Offset - 8;
896 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
897 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
899 // Estimate an offset from the stack pointer.
900 // The incoming offset is relating to the SP at the start of the function,
901 // but when we access the local it'll be relative to the SP after local
902 // allocation, so adjust our SP-relative offset by that allocation size.
904 Offset += MFI->getLocalFrameSize();
905 // Assume that we'll have at least some spill slots allocated.
906 // FIXME: This is a total SWAG number. We should run some statistics
907 // and pick a real one.
908 Offset += 128; // 128 bytes of spill slots
910 // If there is a frame pointer, try using it.
911 // The FP is only available if there is no dynamic realignment. We
912 // don't know for sure yet whether we'll need that, so we guess based
913 // on whether there are any local variables that would trigger it.
914 unsigned StackAlign = TFI->getStackAlignment();
915 if (TFI->hasFP(MF) &&
916 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
917 if (isFrameOffsetLegal(MI, FPOffset))
920 // If we can reference via the stack pointer, try that.
921 // FIXME: This (and the code that resolves the references) can be improved
922 // to only disallow SP relative references in the live range of
923 // the VLA(s). In practice, it's unclear how much difference that
924 // would make, but it may be worth doing.
925 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
928 // The offset likely isn't legal, we want to allocate a virtual base register.
932 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
933 /// be a pointer to FrameIdx at the beginning of the basic block.
934 void ARMBaseRegisterInfo::
935 materializeFrameBaseRegister(MachineBasicBlock *MBB,
936 unsigned BaseReg, int FrameIdx,
937 int64_t Offset) const {
938 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
939 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
940 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
942 MachineBasicBlock::iterator Ins = MBB->begin();
943 DebugLoc DL; // Defaults to "unknown"
944 if (Ins != MBB->end())
945 DL = Ins->getDebugLoc();
947 const MCInstrDesc &MCID = TII.get(ADDriOpc);
948 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
949 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
951 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
952 .addFrameIndex(FrameIdx).addImm(Offset));
954 if (!AFI->isThumb1OnlyFunction())
959 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
960 unsigned BaseReg, int64_t Offset) const {
961 MachineInstr &MI = *I;
962 MachineBasicBlock &MBB = *MI.getParent();
963 MachineFunction &MF = *MBB.getParent();
964 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
965 int Off = Offset; // ARM doesn't need the general 64-bit offsets
968 assert(!AFI->isThumb1OnlyFunction() &&
969 "This resolveFrameIndex does not support Thumb1!");
971 while (!MI.getOperand(i).isFI()) {
973 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
976 if (!AFI->isThumbFunction())
977 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
979 assert(AFI->isThumb2Function());
980 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
982 assert (Done && "Unable to resolve frame index!");
986 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
987 int64_t Offset) const {
988 const MCInstrDesc &Desc = MI->getDesc();
989 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
992 while (!MI->getOperand(i).isFI()) {
994 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
997 // AddrMode4 and AddrMode6 cannot handle any offset.
998 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1001 unsigned NumBits = 0;
1003 bool isSigned = true;
1005 case ARMII::AddrModeT2_i8:
1006 case ARMII::AddrModeT2_i12:
1007 // i8 supports only negative, and i12 supports only positive, so
1008 // based on Offset sign, consider the appropriate instruction
1017 case ARMII::AddrMode5:
1018 // VFP address mode.
1022 case ARMII::AddrMode_i12:
1023 case ARMII::AddrMode2:
1026 case ARMII::AddrMode3:
1029 case ARMII::AddrModeT1_s:
1035 llvm_unreachable("Unsupported addressing mode!");
1039 Offset += getFrameIndexInstrOffset(MI, i);
1040 // Make sure the offset is encodable for instructions that scale the
1042 if ((Offset & (Scale-1)) != 0)
1045 if (isSigned && Offset < 0)
1048 unsigned Mask = (1 << NumBits) - 1;
1049 if ((unsigned)Offset <= Mask * Scale)
1056 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1057 int SPAdj, RegScavenger *RS) const {
1059 MachineInstr &MI = *II;
1060 MachineBasicBlock &MBB = *MI.getParent();
1061 MachineFunction &MF = *MBB.getParent();
1062 const ARMFrameLowering *TFI =
1063 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1064 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1065 assert(!AFI->isThumb1OnlyFunction() &&
1066 "This eliminateFrameIndex does not support Thumb1!");
1068 while (!MI.getOperand(i).isFI()) {
1070 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1073 int FrameIndex = MI.getOperand(i).getIndex();
1076 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1078 // Special handling of dbg_value instructions.
1079 if (MI.isDebugValue()) {
1080 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1081 MI.getOperand(i+1).ChangeToImmediate(Offset);
1085 // Modify MI as necessary to handle as much of 'Offset' as possible
1087 if (!AFI->isThumbFunction())
1088 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1090 assert(AFI->isThumb2Function());
1091 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1096 // If we get here, the immediate doesn't fit into the instruction. We folded
1097 // as much as possible above, handle the rest, providing a register that is
1100 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1101 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1102 "This code isn't needed if offset already handled!");
1104 unsigned ScratchReg = 0;
1105 int PIdx = MI.findFirstPredOperandIdx();
1106 ARMCC::CondCodes Pred = (PIdx == -1)
1107 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1108 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1110 // Must be addrmode4/6.
1111 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1113 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1114 if (!AFI->isThumbFunction())
1115 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1116 Offset, Pred, PredReg, TII);
1118 assert(AFI->isThumb2Function());
1119 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1120 Offset, Pred, PredReg, TII);
1122 // Update the original instruction to use the scratch register.
1123 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);