1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45 cl::desc("Force use of virtual base registers for stack load/store"));
47 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
58 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
59 const ARMSubtarget &sti)
60 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
62 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
67 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68 static const unsigned CalleeSavedRegs[] = {
69 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
70 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
72 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
73 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
77 static const unsigned DarwinCalleeSavedRegs[] = {
78 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
80 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
81 ARM::R11, ARM::R10, ARM::R8,
83 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
84 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
87 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
90 BitVector ARMBaseRegisterInfo::
91 getReservedRegs(const MachineFunction &MF) const {
92 // FIXME: avoid re-calculating this everytime.
93 BitVector Reserved(getNumRegs());
94 Reserved.set(ARM::SP);
95 Reserved.set(ARM::PC);
96 Reserved.set(ARM::FPSCR);
98 Reserved.set(FramePtr);
99 if (hasBasePointer(MF))
100 Reserved.set(BasePtr);
101 // Some targets reserve R9.
102 if (STI.isR9Reserved())
103 Reserved.set(ARM::R9);
107 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
108 unsigned Reg) const {
115 if (hasBasePointer(MF))
120 if (FramePtr == Reg && hasFP(MF))
124 return STI.isR9Reserved();
130 const TargetRegisterClass *
131 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132 const TargetRegisterClass *B,
133 unsigned SubIdx) const {
141 if (A->getSize() == 8) {
142 if (B == &ARM::SPR_8RegClass)
143 return &ARM::DPR_8RegClass;
144 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145 if (A == &ARM::DPR_8RegClass)
147 return &ARM::DPR_VFP2RegClass;
150 if (A->getSize() == 16) {
151 if (B == &ARM::SPR_8RegClass)
152 return &ARM::QPR_8RegClass;
153 return &ARM::QPR_VFP2RegClass;
156 if (A->getSize() == 32) {
157 if (B == &ARM::SPR_8RegClass)
158 return 0; // Do not allow coalescing!
159 return &ARM::QQPR_VFP2RegClass;
162 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163 return 0; // Do not allow coalescing!
170 if (A->getSize() == 16) {
171 if (B == &ARM::DPR_VFP2RegClass)
172 return &ARM::QPR_VFP2RegClass;
173 if (B == &ARM::DPR_8RegClass)
174 return 0; // Do not allow coalescing!
178 if (A->getSize() == 32) {
179 if (B == &ARM::DPR_VFP2RegClass)
180 return &ARM::QQPR_VFP2RegClass;
181 if (B == &ARM::DPR_8RegClass)
182 return 0; // Do not allow coalescing!
186 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187 if (B != &ARM::DPRRegClass)
188 return 0; // Do not allow coalescing!
195 // D sub-registers of QQQQ registers.
196 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
198 return 0; // Do not allow coalescing!
204 if (A->getSize() == 32) {
205 if (B == &ARM::QPR_VFP2RegClass)
206 return &ARM::QQPR_VFP2RegClass;
207 if (B == &ARM::QPR_8RegClass)
208 return 0; // Do not allow coalescing!
212 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213 if (B == &ARM::QPRRegClass)
215 return 0; // Do not allow coalescing!
219 // Q sub-registers of QQQQ registers.
220 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
222 return 0; // Do not allow coalescing!
229 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230 SmallVectorImpl<unsigned> &SubIndices,
231 unsigned &NewSubIdx) const {
233 unsigned Size = RC->getSize() * 8;
237 NewSubIdx = 0; // Whole register.
238 unsigned NumRegs = SubIndices.size();
240 // 8 D registers -> 1 QQQQ register.
241 return (Size == 512 &&
242 SubIndices[0] == ARM::dsub_0 &&
243 SubIndices[1] == ARM::dsub_1 &&
244 SubIndices[2] == ARM::dsub_2 &&
245 SubIndices[3] == ARM::dsub_3 &&
246 SubIndices[4] == ARM::dsub_4 &&
247 SubIndices[5] == ARM::dsub_5 &&
248 SubIndices[6] == ARM::dsub_6 &&
249 SubIndices[7] == ARM::dsub_7);
250 } else if (NumRegs == 4) {
251 if (SubIndices[0] == ARM::qsub_0) {
252 // 4 Q registers -> 1 QQQQ register.
253 return (Size == 512 &&
254 SubIndices[1] == ARM::qsub_1 &&
255 SubIndices[2] == ARM::qsub_2 &&
256 SubIndices[3] == ARM::qsub_3);
257 } else if (SubIndices[0] == ARM::dsub_0) {
258 // 4 D registers -> 1 QQ register.
260 SubIndices[1] == ARM::dsub_1 &&
261 SubIndices[2] == ARM::dsub_2 &&
262 SubIndices[3] == ARM::dsub_3) {
264 NewSubIdx = ARM::qqsub_0;
267 } else if (SubIndices[0] == ARM::dsub_4) {
268 // 4 D registers -> 1 QQ register (2nd).
270 SubIndices[1] == ARM::dsub_5 &&
271 SubIndices[2] == ARM::dsub_6 &&
272 SubIndices[3] == ARM::dsub_7) {
273 NewSubIdx = ARM::qqsub_1;
276 } else if (SubIndices[0] == ARM::ssub_0) {
277 // 4 S registers -> 1 Q register.
279 SubIndices[1] == ARM::ssub_1 &&
280 SubIndices[2] == ARM::ssub_2 &&
281 SubIndices[3] == ARM::ssub_3) {
283 NewSubIdx = ARM::qsub_0;
287 } else if (NumRegs == 2) {
288 if (SubIndices[0] == ARM::qsub_0) {
289 // 2 Q registers -> 1 QQ register.
290 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
292 NewSubIdx = ARM::qqsub_0;
295 } else if (SubIndices[0] == ARM::qsub_2) {
296 // 2 Q registers -> 1 QQ register (2nd).
297 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298 NewSubIdx = ARM::qqsub_1;
301 } else if (SubIndices[0] == ARM::dsub_0) {
302 // 2 D registers -> 1 Q register.
303 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
305 NewSubIdx = ARM::qsub_0;
308 } else if (SubIndices[0] == ARM::dsub_2) {
309 // 2 D registers -> 1 Q register (2nd).
310 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311 NewSubIdx = ARM::qsub_1;
314 } else if (SubIndices[0] == ARM::dsub_4) {
315 // 2 D registers -> 1 Q register (3rd).
316 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317 NewSubIdx = ARM::qsub_2;
320 } else if (SubIndices[0] == ARM::dsub_6) {
321 // 2 D registers -> 1 Q register (3rd).
322 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323 NewSubIdx = ARM::qsub_3;
326 } else if (SubIndices[0] == ARM::ssub_0) {
327 // 2 S registers -> 1 D register.
328 if (SubIndices[1] == ARM::ssub_1) {
330 NewSubIdx = ARM::dsub_0;
333 } else if (SubIndices[0] == ARM::ssub_2) {
334 // 2 S registers -> 1 D register (2nd).
335 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336 NewSubIdx = ARM::dsub_1;
345 const TargetRegisterClass *
346 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347 return ARM::GPRRegisterClass;
350 /// getAllocationOrder - Returns the register allocation order for a specified
351 /// register class in the form of a pair of TargetRegisterClass iterators.
352 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354 unsigned HintType, unsigned HintReg,
355 const MachineFunction &MF) const {
356 // Alternative register allocation orders when favoring even / odd registers
357 // of register pairs.
359 // No FP, R9 is available.
360 static const unsigned GPREven1[] = {
361 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
362 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
365 static const unsigned GPROdd1[] = {
366 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
367 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
371 // FP is R7, R9 is available.
372 static const unsigned GPREven2[] = {
373 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
374 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
377 static const unsigned GPROdd2[] = {
378 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
379 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
383 // FP is R11, R9 is available.
384 static const unsigned GPREven3[] = {
385 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
386 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
389 static const unsigned GPROdd3[] = {
390 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
391 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
395 // No FP, R9 is not available.
396 static const unsigned GPREven4[] = {
397 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
398 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
401 static const unsigned GPROdd4[] = {
402 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
403 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
407 // FP is R7, R9 is not available.
408 static const unsigned GPREven5[] = {
409 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
413 static const unsigned GPROdd5[] = {
414 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
415 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
419 // FP is R11, R9 is not available.
420 static const unsigned GPREven6[] = {
421 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
422 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
424 static const unsigned GPROdd6[] = {
425 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
426 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
430 if (HintType == ARMRI::RegPairEven) {
431 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
432 // It's no longer possible to fulfill this hint. Return the default
434 return std::make_pair(RC->allocation_order_begin(MF),
435 RC->allocation_order_end(MF));
438 if (!STI.isR9Reserved())
439 return std::make_pair(GPREven1,
440 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
442 return std::make_pair(GPREven4,
443 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
444 } else if (FramePtr == ARM::R7) {
445 if (!STI.isR9Reserved())
446 return std::make_pair(GPREven2,
447 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
449 return std::make_pair(GPREven5,
450 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
451 } else { // FramePtr == ARM::R11
452 if (!STI.isR9Reserved())
453 return std::make_pair(GPREven3,
454 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
456 return std::make_pair(GPREven6,
457 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
459 } else if (HintType == ARMRI::RegPairOdd) {
460 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
461 // It's no longer possible to fulfill this hint. Return the default
463 return std::make_pair(RC->allocation_order_begin(MF),
464 RC->allocation_order_end(MF));
467 if (!STI.isR9Reserved())
468 return std::make_pair(GPROdd1,
469 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
471 return std::make_pair(GPROdd4,
472 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
473 } else if (FramePtr == ARM::R7) {
474 if (!STI.isR9Reserved())
475 return std::make_pair(GPROdd2,
476 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
478 return std::make_pair(GPROdd5,
479 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
480 } else { // FramePtr == ARM::R11
481 if (!STI.isR9Reserved())
482 return std::make_pair(GPROdd3,
483 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
485 return std::make_pair(GPROdd6,
486 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
489 return std::make_pair(RC->allocation_order_begin(MF),
490 RC->allocation_order_end(MF));
493 /// ResolveRegAllocHint - Resolves the specified register allocation hint
494 /// to a physical register. Returns the physical register if it is successful.
496 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
497 const MachineFunction &MF) const {
498 if (Reg == 0 || !isPhysicalRegister(Reg))
502 else if (Type == (unsigned)ARMRI::RegPairOdd)
504 return getRegisterPairOdd(Reg, MF);
505 else if (Type == (unsigned)ARMRI::RegPairEven)
507 return getRegisterPairEven(Reg, MF);
512 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
513 MachineFunction &MF) const {
514 MachineRegisterInfo *MRI = &MF.getRegInfo();
515 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
516 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
517 Hint.first == (unsigned)ARMRI::RegPairEven) &&
518 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
519 // If 'Reg' is one of the even / odd register pair and it's now changed
520 // (e.g. coalesced) into a different register. The other register of the
521 // pair allocation hint must be updated to reflect the relationship
523 unsigned OtherReg = Hint.second;
524 Hint = MRI->getRegAllocationHint(OtherReg);
525 if (Hint.second == Reg)
526 // Make sure the pair has not already divorced.
527 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
531 /// hasFP - Return true if the specified function should have a dedicated frame
532 /// pointer register. This is true if the function has variable sized allocas
533 /// or if frame pointer elimination is disabled.
535 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
536 // Mac OS X requires FP not to be clobbered for backtracing purpose.
537 if (STI.isTargetDarwin())
540 const MachineFrameInfo *MFI = MF.getFrameInfo();
541 // Always eliminate non-leaf frame pointers.
542 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
543 needsStackRealignment(MF) ||
544 MFI->hasVarSizedObjects() ||
545 MFI->isFrameAddressTaken());
548 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
549 const MachineFrameInfo *MFI = MF.getFrameInfo();
550 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
552 if (!EnableBasePointer)
555 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
558 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
559 // negative range for ldr/str (255), and thumb1 is positive offsets only.
560 // It's going to be better to use the SP or Base Pointer instead. When there
561 // are variable sized objects, we can't reference off of the SP, so we
562 // reserve a Base Pointer.
563 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
564 // Conservatively estimate whether the negative offset from the frame
565 // pointer will be sufficient to reach. If a function has a smallish
566 // frame, it's less likely to have lots of spills and callee saved
567 // space, so it's all more likely to be within range of the frame pointer.
568 // If it's wrong, the scavenger will still enable access to work, it just
570 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
578 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
579 const MachineFrameInfo *MFI = MF.getFrameInfo();
580 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
581 // We can't realign the stack if:
582 // 1. Dynamic stack realignment is explicitly disabled,
583 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
584 // 3. There are VLAs in the function and the base pointer is disabled.
585 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
586 (!MFI->hasVarSizedObjects() || EnableBasePointer));
589 bool ARMBaseRegisterInfo::
590 needsStackRealignment(const MachineFunction &MF) const {
591 const MachineFrameInfo *MFI = MF.getFrameInfo();
592 const Function *F = MF.getFunction();
593 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
594 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
595 F->hasFnAttr(Attribute::StackAlignment));
597 return requiresRealignment && canRealignStack(MF);
600 bool ARMBaseRegisterInfo::
601 cannotEliminateFrame(const MachineFunction &MF) const {
602 const MachineFrameInfo *MFI = MF.getFrameInfo();
603 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
605 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
606 || needsStackRealignment(MF);
609 /// estimateStackSize - Estimate and return the size of the frame.
610 static unsigned estimateStackSize(MachineFunction &MF) {
611 const MachineFrameInfo *FFI = MF.getFrameInfo();
613 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
614 int FixedOff = -FFI->getObjectOffset(i);
615 if (FixedOff > Offset) Offset = FixedOff;
617 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
618 if (FFI->isDeadObjectIndex(i))
620 Offset += FFI->getObjectSize(i);
621 unsigned Align = FFI->getObjectAlignment(i);
622 // Adjust to alignment boundary
623 Offset = (Offset+Align-1)/Align*Align;
625 return (unsigned)Offset;
628 /// estimateRSStackSizeLimit - Look at each instruction that references stack
629 /// frames and return the stack size limit beyond which some of these
630 /// instructions will require a scratch register during their expansion later.
632 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
633 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
634 unsigned Limit = (1 << 12) - 1;
635 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
636 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
638 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
639 if (!I->getOperand(i).isFI()) continue;
641 // When using ADDri to get the address of a stack object, 255 is the
642 // largest offset guaranteed to fit in the immediate offset.
643 if (I->getOpcode() == ARM::ADDri) {
644 Limit = std::min(Limit, (1U << 8) - 1);
648 // Otherwise check the addressing mode.
649 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
650 case ARMII::AddrMode3:
651 case ARMII::AddrModeT2_i8:
652 Limit = std::min(Limit, (1U << 8) - 1);
654 case ARMII::AddrMode5:
655 case ARMII::AddrModeT2_i8s4:
656 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
658 case ARMII::AddrModeT2_i12:
659 // i12 supports only positive offset so these will be converted to
660 // i8 opcodes. See llvm::rewriteT2FrameIndex.
661 if (hasFP(MF) && AFI->hasStackFrame())
662 Limit = std::min(Limit, (1U << 8) - 1);
664 case ARMII::AddrMode4:
665 case ARMII::AddrMode6:
666 // Addressing modes 4 & 6 (load/store) instructions can't encode an
667 // immediate offset for stack references.
672 break; // At most one FI per instruction
680 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
681 const ARMBaseInstrInfo &TII) {
683 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
685 const MachineBasicBlock &MBB = *MBBI;
686 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
688 FnSize += TII.GetInstSizeInBytes(I);
694 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
695 RegScavenger *RS) const {
696 // This tells PEI to spill the FP as if it is any other callee-save register
697 // to take advantage the eliminateFrameIndex machinery. This also ensures it
698 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
699 // to combine multiple loads / stores.
700 bool CanEliminateFrame = true;
701 bool CS1Spilled = false;
702 bool LRSpilled = false;
703 unsigned NumGPRSpills = 0;
704 SmallVector<unsigned, 4> UnspilledCS1GPRs;
705 SmallVector<unsigned, 4> UnspilledCS2GPRs;
706 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
707 MachineFrameInfo *MFI = MF.getFrameInfo();
709 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
711 // FIXME: It will be better just to find spare register here.
712 if (needsStackRealignment(MF) &&
713 AFI->isThumb2Function())
714 MF.getRegInfo().setPhysRegUsed(ARM::R4);
716 // Spill LR if Thumb1 function uses variable length argument lists.
717 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
718 MF.getRegInfo().setPhysRegUsed(ARM::LR);
720 // Spill the BasePtr if it's used.
721 if (hasBasePointer(MF))
722 MF.getRegInfo().setPhysRegUsed(BasePtr);
724 // Don't spill FP if the frame can be eliminated. This is determined
725 // by scanning the callee-save registers to see if any is used.
726 const unsigned *CSRegs = getCalleeSavedRegs();
727 for (unsigned i = 0; CSRegs[i]; ++i) {
728 unsigned Reg = CSRegs[i];
729 bool Spilled = false;
730 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
731 AFI->setCSRegisterIsSpilled(Reg);
733 CanEliminateFrame = false;
735 // Check alias registers too.
736 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
737 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
739 CanEliminateFrame = false;
744 if (!ARM::GPRRegisterClass->contains(Reg))
750 if (!STI.isTargetDarwin()) {
757 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
772 if (!STI.isTargetDarwin()) {
773 UnspilledCS1GPRs.push_back(Reg);
783 UnspilledCS1GPRs.push_back(Reg);
786 UnspilledCS2GPRs.push_back(Reg);
792 bool ForceLRSpill = false;
793 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
794 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
795 // Force LR to be spilled if the Thumb function size is > 2048. This enables
796 // use of BL to implement far jump. If it turns out that it's not needed
797 // then the branch fix up path will undo it.
798 if (FnSize >= (1 << 11)) {
799 CanEliminateFrame = false;
804 // If any of the stack slot references may be out of range of an immediate
805 // offset, make sure a register (or a spill slot) is available for the
806 // register scavenger. Note that if we're indexing off the frame pointer, the
807 // effective stack size is 4 bytes larger since the FP points to the stack
808 // slot of the previous FP. Also, if we have variable sized objects in the
809 // function, stack slot references will often be negative, and some of
810 // our instructions are positive-offset only, so conservatively consider
811 // that case to want a spill slot (or register) as well. Similarly, if
812 // the function adjusts the stack pointer during execution and the
813 // adjustments aren't already part of our stack size estimate, our offset
814 // calculations may be off, so be conservative.
815 // FIXME: We could add logic to be more precise about negative offsets
816 // and which instructions will need a scratch register for them. Is it
817 // worth the effort and added fragility?
820 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
821 estimateRSStackSizeLimit(MF)))
822 || MFI->hasVarSizedObjects()
823 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
825 bool ExtraCSSpill = false;
826 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
827 AFI->setHasStackFrame(true);
829 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
830 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
831 if (!LRSpilled && CS1Spilled) {
832 MF.getRegInfo().setPhysRegUsed(ARM::LR);
833 AFI->setCSRegisterIsSpilled(ARM::LR);
835 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
836 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
837 ForceLRSpill = false;
842 MF.getRegInfo().setPhysRegUsed(FramePtr);
846 // If stack and double are 8-byte aligned and we are spilling an odd number
847 // of GPRs, spill one extra callee save GPR so we won't have to pad between
848 // the integer and double callee save areas.
849 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
850 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
851 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
852 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
853 unsigned Reg = UnspilledCS1GPRs[i];
854 // Don't spill high register if the function is thumb1
855 if (!AFI->isThumb1OnlyFunction() ||
856 isARMLowRegister(Reg) || Reg == ARM::LR) {
857 MF.getRegInfo().setPhysRegUsed(Reg);
858 AFI->setCSRegisterIsSpilled(Reg);
859 if (!isReservedReg(MF, Reg))
864 } else if (!UnspilledCS2GPRs.empty() &&
865 !AFI->isThumb1OnlyFunction()) {
866 unsigned Reg = UnspilledCS2GPRs.front();
867 MF.getRegInfo().setPhysRegUsed(Reg);
868 AFI->setCSRegisterIsSpilled(Reg);
869 if (!isReservedReg(MF, Reg))
874 // Estimate if we might need to scavenge a register at some point in order
875 // to materialize a stack offset. If so, either spill one additional
876 // callee-saved register or reserve a special spill slot to facilitate
877 // register scavenging. Thumb1 needs a spill slot for stack pointer
878 // adjustments also, even when the frame itself is small.
879 if (BigStack && !ExtraCSSpill) {
880 // If any non-reserved CS register isn't spilled, just spill one or two
881 // extra. That should take care of it!
882 unsigned NumExtras = TargetAlign / 4;
883 SmallVector<unsigned, 2> Extras;
884 while (NumExtras && !UnspilledCS1GPRs.empty()) {
885 unsigned Reg = UnspilledCS1GPRs.back();
886 UnspilledCS1GPRs.pop_back();
887 if (!isReservedReg(MF, Reg) &&
888 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
890 Extras.push_back(Reg);
894 // For non-Thumb1 functions, also check for hi-reg CS registers
895 if (!AFI->isThumb1OnlyFunction()) {
896 while (NumExtras && !UnspilledCS2GPRs.empty()) {
897 unsigned Reg = UnspilledCS2GPRs.back();
898 UnspilledCS2GPRs.pop_back();
899 if (!isReservedReg(MF, Reg)) {
900 Extras.push_back(Reg);
905 if (Extras.size() && NumExtras == 0) {
906 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
907 MF.getRegInfo().setPhysRegUsed(Extras[i]);
908 AFI->setCSRegisterIsSpilled(Extras[i]);
910 } else if (!AFI->isThumb1OnlyFunction()) {
911 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
912 // closest to SP or frame pointer.
913 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
914 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
922 MF.getRegInfo().setPhysRegUsed(ARM::LR);
923 AFI->setCSRegisterIsSpilled(ARM::LR);
924 AFI->setLRIsSpilledForFarJump(true);
928 unsigned ARMBaseRegisterInfo::getRARegister() const {
933 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
939 // Provide a base+offset reference to an FI slot for debug info. It's the
940 // same as what we use for resolving the code-gen references for now.
941 // FIXME: This can go wrong when references are SP-relative and simple call
942 // frames aren't used.
944 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
945 unsigned &FrameReg) const {
946 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
950 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
954 const MachineFrameInfo *MFI = MF.getFrameInfo();
955 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
956 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
957 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
958 bool isFixed = MFI->isFixedObjectIndex(FI);
962 if (AFI->isGPRCalleeSavedArea1Frame(FI))
963 return Offset - AFI->getGPRCalleeSavedArea1Offset();
964 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
965 return Offset - AFI->getGPRCalleeSavedArea2Offset();
966 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
967 return Offset - AFI->getDPRCalleeSavedAreaOffset();
969 // When dynamically realigning the stack, use the frame pointer for
970 // parameters, and the stack/base pointer for locals.
971 if (needsStackRealignment(MF)) {
972 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
974 FrameReg = getFrameRegister(MF);
976 } else if (MFI->hasVarSizedObjects()) {
977 assert(hasBasePointer(MF) &&
978 "VLAs and dynamic stack alignment, but missing base pointer!");
984 // If there is a frame pointer, use it when we can.
985 if (hasFP(MF) && AFI->hasStackFrame()) {
986 // Use frame pointer to reference fixed objects. Use it for locals if
987 // there are VLAs (and thus the SP isn't reliable as a base).
988 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
989 FrameReg = getFrameRegister(MF);
991 } else if (MFI->hasVarSizedObjects()) {
992 assert(hasBasePointer(MF) && "missing base pointer!");
993 // Try to use the frame pointer if we can, else use the base pointer
994 // since it's available. This is handy for the emergency spill slot, in
996 if (AFI->isThumb2Function()) {
997 if (FPOffset >= -255 && FPOffset < 0) {
998 FrameReg = getFrameRegister(MF);
1003 } else if (AFI->isThumb2Function()) {
1004 // In Thumb2 mode, the negative offset is very limited. Try to avoid
1005 // out of range references.
1006 if (FPOffset >= -255 && FPOffset < 0) {
1007 FrameReg = getFrameRegister(MF);
1010 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1011 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1012 FrameReg = getFrameRegister(MF);
1016 // Use the base pointer if we have one.
1017 if (hasBasePointer(MF))
1023 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1026 return getFrameIndexReference(MF, FI, FrameReg);
1029 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1030 llvm_unreachable("What is the exception register");
1034 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1035 llvm_unreachable("What is the exception handler register");
1039 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1040 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1043 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1044 const MachineFunction &MF) const {
1047 // Return 0 if either register of the pair is a special register.
1056 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1059 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1061 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1133 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1134 const MachineFunction &MF) const {
1137 // Return 0 if either register of the pair is a special register.
1146 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1149 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1151 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1223 /// emitLoadConstPool - Emits a load from constpool to materialize the
1224 /// specified immediate.
1225 void ARMBaseRegisterInfo::
1226 emitLoadConstPool(MachineBasicBlock &MBB,
1227 MachineBasicBlock::iterator &MBBI,
1229 unsigned DestReg, unsigned SubIdx, int Val,
1230 ARMCC::CondCodes Pred,
1231 unsigned PredReg) const {
1232 MachineFunction &MF = *MBB.getParent();
1233 MachineConstantPool *ConstantPool = MF.getConstantPool();
1235 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1236 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1238 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1239 .addReg(DestReg, getDefRegState(true), SubIdx)
1240 .addConstantPoolIndex(Idx)
1241 .addImm(0).addImm(Pred).addReg(PredReg);
1244 bool ARMBaseRegisterInfo::
1245 requiresRegisterScavenging(const MachineFunction &MF) const {
1249 bool ARMBaseRegisterInfo::
1250 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1254 bool ARMBaseRegisterInfo::
1255 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1256 return EnableLocalStackAlloc;
1259 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1260 // not required, we reserve argument space for call sites in the function
1261 // immediately on entry to the current function. This eliminates the need for
1262 // add/sub sp brackets around call sites. Returns true if the call frame is
1263 // included as part of the stack frame.
1264 bool ARMBaseRegisterInfo::
1265 hasReservedCallFrame(const MachineFunction &MF) const {
1266 const MachineFrameInfo *FFI = MF.getFrameInfo();
1267 unsigned CFSize = FFI->getMaxCallFrameSize();
1268 // It's not always a good idea to include the call frame as part of the
1269 // stack frame. ARM (especially Thumb) has small immediate offset to
1270 // address the stack frame. So a large call frame can cause poor codegen
1271 // and may even makes it impossible to scavenge a register.
1272 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1275 return !MF.getFrameInfo()->hasVarSizedObjects();
1278 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1279 // call frame pseudos can be simplified. Unlike most targets, having a FP
1280 // is not sufficient here since we still may reference some objects via SP
1281 // even when FP is available in Thumb2 mode.
1282 bool ARMBaseRegisterInfo::
1283 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1284 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1288 emitSPUpdate(bool isARM,
1289 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1290 DebugLoc dl, const ARMBaseInstrInfo &TII,
1292 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1294 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1295 Pred, PredReg, TII);
1297 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1298 Pred, PredReg, TII);
1302 void ARMBaseRegisterInfo::
1303 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1304 MachineBasicBlock::iterator I) const {
1305 if (!hasReservedCallFrame(MF)) {
1306 // If we have alloca, convert as follows:
1307 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1308 // ADJCALLSTACKUP -> add, sp, sp, amount
1309 MachineInstr *Old = I;
1310 DebugLoc dl = Old->getDebugLoc();
1311 unsigned Amount = Old->getOperand(0).getImm();
1313 // We need to keep the stack aligned properly. To do this, we round the
1314 // amount of space needed for the outgoing arguments up to the next
1315 // alignment boundary.
1316 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1317 Amount = (Amount+Align-1)/Align*Align;
1319 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1320 assert(!AFI->isThumb1OnlyFunction() &&
1321 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1322 bool isARM = !AFI->isThumbFunction();
1324 // Replace the pseudo instruction with a new instruction...
1325 unsigned Opc = Old->getOpcode();
1326 int PIdx = Old->findFirstPredOperandIdx();
1327 ARMCC::CondCodes Pred = (PIdx == -1)
1328 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1329 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1330 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1331 unsigned PredReg = Old->getOperand(2).getReg();
1332 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1334 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1335 unsigned PredReg = Old->getOperand(3).getReg();
1336 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1337 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1344 int64_t ARMBaseRegisterInfo::
1345 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1346 const TargetInstrDesc &Desc = MI->getDesc();
1347 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1348 int64_t InstrOffs = 0;;
1350 unsigned ImmIdx = 0;
1352 case ARMII::AddrModeT2_i8:
1353 case ARMII::AddrModeT2_i12:
1354 case ARMII::AddrMode_i12:
1355 InstrOffs = MI->getOperand(Idx+1).getImm();
1358 case ARMII::AddrMode5: {
1359 // VFP address mode.
1360 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1361 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1362 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1363 InstrOffs = -InstrOffs;
1367 case ARMII::AddrMode2: {
1369 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1370 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1371 InstrOffs = -InstrOffs;
1374 case ARMII::AddrMode3: {
1376 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1377 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1378 InstrOffs = -InstrOffs;
1381 case ARMII::AddrModeT1_s: {
1383 InstrOffs = MI->getOperand(ImmIdx).getImm();
1388 llvm_unreachable("Unsupported addressing mode!");
1392 return InstrOffs * Scale;
1395 /// needsFrameBaseReg - Returns true if the instruction's frame index
1396 /// reference would be better served by a base register other than FP
1397 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1398 /// references it should create new base registers for.
1399 bool ARMBaseRegisterInfo::
1400 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1401 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1402 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1405 // It's the load/store FI references that cause issues, as it can be difficult
1406 // to materialize the offset if it won't fit in the literal field. Estimate
1407 // based on the size of the local frame and some conservative assumptions
1408 // about the rest of the stack frame (note, this is pre-regalloc, so
1409 // we don't know everything for certain yet) whether this offset is likely
1410 // to be out of range of the immediate. Return true if so.
1412 // We only generate virtual base registers for loads and stores, so
1413 // return false for everything else.
1414 unsigned Opc = MI->getOpcode();
1416 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1417 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1418 case ARM::t2LDRi12: case ARM::t2LDRi8:
1419 case ARM::t2STRi12: case ARM::t2STRi8:
1420 case ARM::VLDRS: case ARM::VLDRD:
1421 case ARM::VSTRS: case ARM::VSTRD:
1422 case ARM::tSTRspi: case ARM::tLDRspi:
1423 if (ForceAllBaseRegAlloc)
1430 // Without a virtual base register, if the function has variable sized
1431 // objects, all fixed-size local references will be via the frame pointer,
1432 // Approximate the offset and see if it's legal for the instruction.
1433 // Note that the incoming offset is based on the SP value at function entry,
1434 // so it'll be negative.
1435 MachineFunction &MF = *MI->getParent()->getParent();
1436 MachineFrameInfo *MFI = MF.getFrameInfo();
1437 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1439 // Estimate an offset from the frame pointer.
1440 // Conservatively assume all callee-saved registers get pushed. R4-R6
1441 // will be earlier than the FP, so we ignore those.
1443 int64_t FPOffset = Offset - 8;
1444 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1445 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1447 // Estimate an offset from the stack pointer.
1448 // The incoming offset is relating to the SP at the start of the function,
1449 // but when we access the local it'll be relative to the SP after local
1450 // allocation, so adjust our SP-relative offset by that allocation size.
1452 Offset += MFI->getLocalFrameSize();
1453 // Assume that we'll have at least some spill slots allocated.
1454 // FIXME: This is a total SWAG number. We should run some statistics
1455 // and pick a real one.
1456 Offset += 128; // 128 bytes of spill slots
1458 // If there is a frame pointer, try using it.
1459 // The FP is only available if there is no dynamic realignment. We
1460 // don't know for sure yet whether we'll need that, so we guess based
1461 // on whether there are any local variables that would trigger it.
1462 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1464 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1465 if (isFrameOffsetLegal(MI, FPOffset))
1468 // If we can reference via the stack pointer, try that.
1469 // FIXME: This (and the code that resolves the references) can be improved
1470 // to only disallow SP relative references in the live range of
1471 // the VLA(s). In practice, it's unclear how much difference that
1472 // would make, but it may be worth doing.
1473 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1476 // The offset likely isn't legal, we want to allocate a virtual base register.
1480 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1481 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1482 void ARMBaseRegisterInfo::
1483 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1484 int FrameIdx, int64_t Offset) const {
1485 ARMFunctionInfo *AFI =
1486 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1487 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1488 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1490 MachineInstrBuilder MIB =
1491 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1492 .addFrameIndex(FrameIdx).addImm(Offset);
1493 if (!AFI->isThumb1OnlyFunction())
1494 AddDefaultCC(AddDefaultPred(MIB));
1498 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1499 unsigned BaseReg, int64_t Offset) const {
1500 MachineInstr &MI = *I;
1501 MachineBasicBlock &MBB = *MI.getParent();
1502 MachineFunction &MF = *MBB.getParent();
1503 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1504 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1507 assert(!AFI->isThumb1OnlyFunction() &&
1508 "This resolveFrameIndex does not support Thumb1!");
1510 while (!MI.getOperand(i).isFI()) {
1512 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1515 if (!AFI->isThumbFunction())
1516 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1518 assert(AFI->isThumb2Function());
1519 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1521 assert (Done && "Unable to resolve frame index!");
1524 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1525 int64_t Offset) const {
1526 const TargetInstrDesc &Desc = MI->getDesc();
1527 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1530 while (!MI->getOperand(i).isFI()) {
1532 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1535 // AddrMode4 and AddrMode6 cannot handle any offset.
1536 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1539 unsigned NumBits = 0;
1541 bool isSigned = true;
1543 case ARMII::AddrModeT2_i8:
1544 case ARMII::AddrModeT2_i12:
1545 // i8 supports only negative, and i12 supports only positive, so
1546 // based on Offset sign, consider the appropriate instruction
1555 case ARMII::AddrMode5:
1556 // VFP address mode.
1560 case ARMII::AddrMode_i12:
1561 case ARMII::AddrMode2:
1564 case ARMII::AddrMode3:
1567 case ARMII::AddrModeT1_s:
1573 llvm_unreachable("Unsupported addressing mode!");
1577 Offset += getFrameIndexInstrOffset(MI, i);
1578 // Make sure the offset is encodable for instructions that scale the
1580 if ((Offset & (Scale-1)) != 0)
1583 if (isSigned && Offset < 0)
1586 unsigned Mask = (1 << NumBits) - 1;
1587 if ((unsigned)Offset <= Mask * Scale)
1594 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1595 int SPAdj, RegScavenger *RS) const {
1597 MachineInstr &MI = *II;
1598 MachineBasicBlock &MBB = *MI.getParent();
1599 MachineFunction &MF = *MBB.getParent();
1600 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1601 assert(!AFI->isThumb1OnlyFunction() &&
1602 "This eliminateFrameIndex does not support Thumb1!");
1604 while (!MI.getOperand(i).isFI()) {
1606 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1609 int FrameIndex = MI.getOperand(i).getIndex();
1612 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1614 // Special handling of dbg_value instructions.
1615 if (MI.isDebugValue()) {
1616 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1617 MI.getOperand(i+1).ChangeToImmediate(Offset);
1621 // Modify MI as necessary to handle as much of 'Offset' as possible
1623 if (!AFI->isThumbFunction())
1624 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1626 assert(AFI->isThumb2Function());
1627 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1632 // If we get here, the immediate doesn't fit into the instruction. We folded
1633 // as much as possible above, handle the rest, providing a register that is
1636 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1637 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1638 "This code isn't needed if offset already handled!");
1640 unsigned ScratchReg = 0;
1641 int PIdx = MI.findFirstPredOperandIdx();
1642 ARMCC::CondCodes Pred = (PIdx == -1)
1643 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1644 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1646 // Must be addrmode4/6.
1647 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1649 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1650 if (!AFI->isThumbFunction())
1651 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1652 Offset, Pred, PredReg, TII);
1654 assert(AFI->isThumb2Function());
1655 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1656 Offset, Pred, PredReg, TII);
1658 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1662 /// Move iterator past the next bunch of callee save load / store ops for
1663 /// the particular spill area (1: integer area 1, 2: integer area 2,
1664 /// 3: fp area, 0: don't care).
1665 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1666 MachineBasicBlock::iterator &MBBI,
1667 int Opc1, int Opc2, unsigned Area,
1668 const ARMSubtarget &STI) {
1669 while (MBBI != MBB.end() &&
1670 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1671 MBBI->getOperand(1).isFI()) {
1674 unsigned Category = 0;
1675 switch (MBBI->getOperand(0).getReg()) {
1676 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1680 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1681 Category = STI.isTargetDarwin() ? 2 : 1;
1683 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1684 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1691 if (Done || Category != Area)
1699 void ARMBaseRegisterInfo::
1700 emitPrologue(MachineFunction &MF) const {
1701 MachineBasicBlock &MBB = MF.front();
1702 MachineBasicBlock::iterator MBBI = MBB.begin();
1703 MachineFrameInfo *MFI = MF.getFrameInfo();
1704 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1705 assert(!AFI->isThumb1OnlyFunction() &&
1706 "This emitPrologue does not support Thumb1!");
1707 bool isARM = !AFI->isThumbFunction();
1708 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1709 unsigned NumBytes = MFI->getStackSize();
1710 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1711 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1713 // Determine the sizes of each callee-save spill areas and record which frame
1714 // belongs to which callee-save spill areas.
1715 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1716 int FramePtrSpillFI = 0;
1718 // Allocate the vararg register save area. This is not counted in NumBytes.
1720 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1722 if (!AFI->hasStackFrame()) {
1724 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1728 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1729 unsigned Reg = CSI[i].getReg();
1730 int FI = CSI[i].getFrameIdx();
1737 if (Reg == FramePtr)
1738 FramePtrSpillFI = FI;
1739 AFI->addGPRCalleeSavedArea1Frame(FI);
1746 if (Reg == FramePtr)
1747 FramePtrSpillFI = FI;
1748 if (STI.isTargetDarwin()) {
1749 AFI->addGPRCalleeSavedArea2Frame(FI);
1752 AFI->addGPRCalleeSavedArea1Frame(FI);
1757 AFI->addDPRCalleeSavedAreaFrame(FI);
1762 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1763 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1764 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
1766 // Set FP to point to the stack slot that contains the previous FP.
1767 // For Darwin, FP is R7, which has now been stored in spill area 1.
1768 // Otherwise, if this is not Darwin, all the callee-saved registers go
1769 // into spill area 1, including the FP in R11. In either case, it is
1770 // now safe to emit this assignment.
1771 bool HasFP = hasFP(MF);
1773 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1774 MachineInstrBuilder MIB =
1775 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1776 .addFrameIndex(FramePtrSpillFI).addImm(0);
1777 AddDefaultCC(AddDefaultPred(MIB));
1780 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1781 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1783 // Build the new SUBri to adjust SP for FP callee-save spill area.
1784 movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
1785 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1787 // Determine starting offsets of spill areas.
1788 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1789 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1790 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1792 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1794 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1795 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1796 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1798 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1799 NumBytes = DPRCSOffset;
1801 // Adjust SP after all the callee-save spills.
1802 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1804 AFI->setShouldRestoreSPFromFP(true);
1807 if (STI.isTargetELF() && hasFP(MF)) {
1808 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1809 AFI->getFramePtrSpillOffset());
1810 AFI->setShouldRestoreSPFromFP(true);
1813 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1814 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1815 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1817 // If we need dynamic stack realignment, do it here. Be paranoid and make
1818 // sure if we also have VLAs, we have a base pointer for frame access.
1819 if (needsStackRealignment(MF)) {
1820 unsigned MaxAlign = MFI->getMaxAlignment();
1821 assert (!AFI->isThumb1OnlyFunction());
1822 if (!AFI->isThumbFunction()) {
1823 // Emit bic sp, sp, MaxAlign
1824 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1825 TII.get(ARM::BICri), ARM::SP)
1826 .addReg(ARM::SP, RegState::Kill)
1827 .addImm(MaxAlign-1)));
1829 // We cannot use sp as source/dest register here, thus we're emitting the
1830 // following sequence:
1832 // bic r4, r4, MaxAlign
1834 // FIXME: It will be better just to find spare register here.
1835 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1836 .addReg(ARM::SP, RegState::Kill);
1837 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1838 TII.get(ARM::t2BICri), ARM::R4)
1839 .addReg(ARM::R4, RegState::Kill)
1840 .addImm(MaxAlign-1)));
1841 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1842 .addReg(ARM::R4, RegState::Kill);
1845 AFI->setShouldRestoreSPFromFP(true);
1848 // If we need a base pointer, set it up here. It's whatever the value
1849 // of the stack pointer is at this point. Any variable size objects
1850 // will be allocated after this, so we can still use the base pointer
1851 // to reference locals.
1852 if (hasBasePointer(MF)) {
1854 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1856 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1858 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1862 // If the frame has variable sized objects then the epilogue must restore
1864 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1865 AFI->setShouldRestoreSPFromFP(true);
1868 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1869 for (unsigned i = 0; CSRegs[i]; ++i)
1870 if (Reg == CSRegs[i])
1875 static bool isCSRestore(MachineInstr *MI,
1876 const ARMBaseInstrInfo &TII,
1877 const unsigned *CSRegs) {
1878 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1879 MI->getOpcode() == (int)ARM::LDRi12 ||
1880 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1881 MI->getOperand(1).isFI() &&
1882 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1885 void ARMBaseRegisterInfo::
1886 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1887 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1888 assert(MBBI->getDesc().isReturn() &&
1889 "Can only insert epilog into returning blocks");
1890 unsigned RetOpcode = MBBI->getOpcode();
1891 DebugLoc dl = MBBI->getDebugLoc();
1892 MachineFrameInfo *MFI = MF.getFrameInfo();
1893 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1894 assert(!AFI->isThumb1OnlyFunction() &&
1895 "This emitEpilogue does not support Thumb1!");
1896 bool isARM = !AFI->isThumbFunction();
1898 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1899 int NumBytes = (int)MFI->getStackSize();
1901 if (!AFI->hasStackFrame()) {
1903 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1905 // Unwind MBBI to point to first LDR / VLDRD.
1906 const unsigned *CSRegs = getCalleeSavedRegs();
1907 if (MBBI != MBB.begin()) {
1910 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1911 if (!isCSRestore(MBBI, TII, CSRegs))
1915 // Move SP to start of FP callee save spill area.
1916 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1917 AFI->getGPRCalleeSavedArea2Size() +
1918 AFI->getDPRCalleeSavedAreaSize());
1920 // Reset SP based on frame pointer only if the stack frame extends beyond
1921 // frame pointer stack slot or target is ELF and the function has FP.
1922 if (AFI->shouldRestoreSPFromFP()) {
1923 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1926 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1929 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1934 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1935 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1937 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1940 } else if (NumBytes)
1941 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1943 // Move SP to start of integer callee save spill area 2.
1944 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1945 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1947 // Move SP to start of integer callee save spill area 1.
1948 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
1949 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1951 // Move SP to SP upon entry to the function.
1952 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
1953 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1956 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1957 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1958 // Tail call return: adjust the stack pointer and jump to callee.
1959 MBBI = prior(MBB.end());
1960 MachineOperand &JumpTarget = MBBI->getOperand(0);
1962 // Jump to label or value in register.
1963 if (RetOpcode == ARM::TCRETURNdi) {
1964 BuildMI(MBB, MBBI, dl,
1965 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1966 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1967 JumpTarget.getTargetFlags());
1968 } else if (RetOpcode == ARM::TCRETURNdiND) {
1969 BuildMI(MBB, MBBI, dl,
1970 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1971 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1972 JumpTarget.getTargetFlags());
1973 } else if (RetOpcode == ARM::TCRETURNri) {
1974 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1975 addReg(JumpTarget.getReg(), RegState::Kill);
1976 } else if (RetOpcode == ARM::TCRETURNriND) {
1977 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1978 addReg(JumpTarget.getReg(), RegState::Kill);
1981 MachineInstr *NewMI = prior(MBBI);
1982 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1983 NewMI->addOperand(MBBI->getOperand(i));
1985 // Delete the pseudo instruction TCRETURN.
1990 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1993 #include "ARMGenRegisterInfo.inc"