1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "ARMGenRegisterInfo.inc"
48 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49 cl::desc("Force use of virtual base registers for stack load/store"));
51 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58 const ARMSubtarget &sti)
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66 return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
70 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71 return (STI.isTargetIOS()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
74 BitVector ARMBaseRegisterInfo::
75 getReservedRegs(const MachineFunction &MF) const {
76 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
78 // FIXME: avoid re-calculating this every time.
79 BitVector Reserved(getNumRegs());
80 Reserved.set(ARM::SP);
81 Reserved.set(ARM::PC);
82 Reserved.set(ARM::FPSCR);
84 Reserved.set(FramePtr);
85 if (hasBasePointer(MF))
86 Reserved.set(BasePtr);
87 // Some targets reserve R9.
88 if (STI.isR9Reserved())
89 Reserved.set(ARM::R9);
90 // Reserve D16-D31 if the subtarget doesn't support them.
91 if (!STI.hasVFP3() || STI.hasD16()) {
92 assert(ARM::D31 == ARM::D16 + 15);
93 for (unsigned i = 0; i != 16; ++i)
94 Reserved.set(ARM::D16 + i);
99 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
100 unsigned Reg) const {
101 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
109 if (hasBasePointer(MF))
114 if (FramePtr == Reg && TFI->hasFP(MF))
118 return STI.isR9Reserved();
125 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
126 SmallVectorImpl<unsigned> &SubIndices,
127 unsigned &NewSubIdx) const {
129 unsigned Size = RC->getSize() * 8;
133 NewSubIdx = 0; // Whole register.
134 unsigned NumRegs = SubIndices.size();
136 // 8 D registers -> 1 QQQQ register.
137 return (Size == 512 &&
138 SubIndices[0] == ARM::dsub_0 &&
139 SubIndices[1] == ARM::dsub_1 &&
140 SubIndices[2] == ARM::dsub_2 &&
141 SubIndices[3] == ARM::dsub_3 &&
142 SubIndices[4] == ARM::dsub_4 &&
143 SubIndices[5] == ARM::dsub_5 &&
144 SubIndices[6] == ARM::dsub_6 &&
145 SubIndices[7] == ARM::dsub_7);
146 } else if (NumRegs == 4) {
147 if (SubIndices[0] == ARM::qsub_0) {
148 // 4 Q registers -> 1 QQQQ register.
149 return (Size == 512 &&
150 SubIndices[1] == ARM::qsub_1 &&
151 SubIndices[2] == ARM::qsub_2 &&
152 SubIndices[3] == ARM::qsub_3);
153 } else if (SubIndices[0] == ARM::dsub_0) {
154 // 4 D registers -> 1 QQ register.
156 SubIndices[1] == ARM::dsub_1 &&
157 SubIndices[2] == ARM::dsub_2 &&
158 SubIndices[3] == ARM::dsub_3) {
160 NewSubIdx = ARM::qqsub_0;
163 } else if (SubIndices[0] == ARM::dsub_4) {
164 // 4 D registers -> 1 QQ register (2nd).
166 SubIndices[1] == ARM::dsub_5 &&
167 SubIndices[2] == ARM::dsub_6 &&
168 SubIndices[3] == ARM::dsub_7) {
169 NewSubIdx = ARM::qqsub_1;
172 } else if (SubIndices[0] == ARM::ssub_0) {
173 // 4 S registers -> 1 Q register.
175 SubIndices[1] == ARM::ssub_1 &&
176 SubIndices[2] == ARM::ssub_2 &&
177 SubIndices[3] == ARM::ssub_3) {
179 NewSubIdx = ARM::qsub_0;
183 } else if (NumRegs == 2) {
184 if (SubIndices[0] == ARM::qsub_0) {
185 // 2 Q registers -> 1 QQ register.
186 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
188 NewSubIdx = ARM::qqsub_0;
191 } else if (SubIndices[0] == ARM::qsub_2) {
192 // 2 Q registers -> 1 QQ register (2nd).
193 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
194 NewSubIdx = ARM::qqsub_1;
197 } else if (SubIndices[0] == ARM::dsub_0) {
198 // 2 D registers -> 1 Q register.
199 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
201 NewSubIdx = ARM::qsub_0;
204 } else if (SubIndices[0] == ARM::dsub_2) {
205 // 2 D registers -> 1 Q register (2nd).
206 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
207 NewSubIdx = ARM::qsub_1;
210 } else if (SubIndices[0] == ARM::dsub_4) {
211 // 2 D registers -> 1 Q register (3rd).
212 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
213 NewSubIdx = ARM::qsub_2;
216 } else if (SubIndices[0] == ARM::dsub_6) {
217 // 2 D registers -> 1 Q register (3rd).
218 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
219 NewSubIdx = ARM::qsub_3;
222 } else if (SubIndices[0] == ARM::ssub_0) {
223 // 2 S registers -> 1 D register.
224 if (SubIndices[1] == ARM::ssub_1) {
226 NewSubIdx = ARM::dsub_0;
229 } else if (SubIndices[0] == ARM::ssub_2) {
230 // 2 S registers -> 1 D register (2nd).
231 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
232 NewSubIdx = ARM::dsub_1;
240 const TargetRegisterClass*
241 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
243 const TargetRegisterClass *Super = RC;
244 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
246 switch (Super->getID()) {
247 case ARM::GPRRegClassID:
248 case ARM::SPRRegClassID:
249 case ARM::DPRRegClassID:
250 case ARM::QPRRegClassID:
251 case ARM::QQPRRegClassID:
252 case ARM::QQQQPRRegClassID:
260 const TargetRegisterClass *
261 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
262 return ARM::GPRRegisterClass;
265 const TargetRegisterClass *
266 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
267 if (RC == &ARM::CCRRegClass)
268 return 0; // Can't copy CCR registers.
273 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
274 MachineFunction &MF) const {
275 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
277 switch (RC->getID()) {
280 case ARM::tGPRRegClassID:
281 return TFI->hasFP(MF) ? 4 : 5;
282 case ARM::GPRRegClassID: {
283 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
284 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
286 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
287 case ARM::DPRRegClassID:
292 /// getRawAllocationOrder - Returns the register allocation order for a
293 /// specified register class with a target-dependent hint.
295 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
296 unsigned HintType, unsigned HintReg,
297 const MachineFunction &MF) const {
298 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
299 // Alternative register allocation orders when favoring even / odd registers
300 // of register pairs.
302 // No FP, R9 is available.
303 static const uint16_t GPREven1[] = {
304 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
305 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
308 static const uint16_t GPROdd1[] = {
309 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
310 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
314 // FP is R7, R9 is available.
315 static const uint16_t GPREven2[] = {
316 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
317 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
320 static const uint16_t GPROdd2[] = {
321 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
322 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
326 // FP is R11, R9 is available.
327 static const uint16_t GPREven3[] = {
328 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
329 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
332 static const uint16_t GPROdd3[] = {
333 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
334 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
338 // No FP, R9 is not available.
339 static const uint16_t GPREven4[] = {
340 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
341 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
344 static const uint16_t GPROdd4[] = {
345 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
346 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
350 // FP is R7, R9 is not available.
351 static const uint16_t GPREven5[] = {
352 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
353 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
356 static const uint16_t GPROdd5[] = {
357 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
358 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
362 // FP is R11, R9 is not available.
363 static const uint16_t GPREven6[] = {
364 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
365 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
367 static const uint16_t GPROdd6[] = {
368 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
369 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
372 // We only support even/odd hints for GPR and rGPR.
373 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
374 return RC->getRawAllocationOrder(MF);
376 if (HintType == ARMRI::RegPairEven) {
377 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
378 // It's no longer possible to fulfill this hint. Return the default
380 return RC->getRawAllocationOrder(MF);
382 if (!TFI->hasFP(MF)) {
383 if (!STI.isR9Reserved())
384 return makeArrayRef(GPREven1);
386 return makeArrayRef(GPREven4);
387 } else if (FramePtr == ARM::R7) {
388 if (!STI.isR9Reserved())
389 return makeArrayRef(GPREven2);
391 return makeArrayRef(GPREven5);
392 } else { // FramePtr == ARM::R11
393 if (!STI.isR9Reserved())
394 return makeArrayRef(GPREven3);
396 return makeArrayRef(GPREven6);
398 } else if (HintType == ARMRI::RegPairOdd) {
399 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
400 // It's no longer possible to fulfill this hint. Return the default
402 return RC->getRawAllocationOrder(MF);
404 if (!TFI->hasFP(MF)) {
405 if (!STI.isR9Reserved())
406 return makeArrayRef(GPROdd1);
408 return makeArrayRef(GPROdd4);
409 } else if (FramePtr == ARM::R7) {
410 if (!STI.isR9Reserved())
411 return makeArrayRef(GPROdd2);
413 return makeArrayRef(GPROdd5);
414 } else { // FramePtr == ARM::R11
415 if (!STI.isR9Reserved())
416 return makeArrayRef(GPROdd3);
418 return makeArrayRef(GPROdd6);
421 return RC->getRawAllocationOrder(MF);
424 /// ResolveRegAllocHint - Resolves the specified register allocation hint
425 /// to a physical register. Returns the physical register if it is successful.
427 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
428 const MachineFunction &MF) const {
429 if (Reg == 0 || !isPhysicalRegister(Reg))
433 else if (Type == (unsigned)ARMRI::RegPairOdd)
435 return getRegisterPairOdd(Reg, MF);
436 else if (Type == (unsigned)ARMRI::RegPairEven)
438 return getRegisterPairEven(Reg, MF);
443 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
444 MachineFunction &MF) const {
445 MachineRegisterInfo *MRI = &MF.getRegInfo();
446 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
447 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
448 Hint.first == (unsigned)ARMRI::RegPairEven) &&
449 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
450 // If 'Reg' is one of the even / odd register pair and it's now changed
451 // (e.g. coalesced) into a different register. The other register of the
452 // pair allocation hint must be updated to reflect the relationship
454 unsigned OtherReg = Hint.second;
455 Hint = MRI->getRegAllocationHint(OtherReg);
456 if (Hint.second == Reg)
457 // Make sure the pair has not already divorced.
458 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
463 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
464 // CortexA9 has a Write-after-write hazard for NEON registers.
465 if (!STI.isCortexA9())
468 switch (RC->getID()) {
469 case ARM::DPRRegClassID:
470 case ARM::DPR_8RegClassID:
471 case ARM::DPR_VFP2RegClassID:
472 case ARM::QPRRegClassID:
473 case ARM::QPR_8RegClassID:
474 case ARM::QPR_VFP2RegClassID:
475 case ARM::SPRRegClassID:
476 case ARM::SPR_8RegClassID:
477 // Avoid reusing S, D, and Q registers.
478 // Don't increase register pressure for QQ and QQQQ.
485 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
486 const MachineFrameInfo *MFI = MF.getFrameInfo();
487 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
488 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
490 if (!EnableBasePointer)
493 // When outgoing call frames are so large that we adjust the stack pointer
494 // around the call, we can no longer use the stack pointer to reach the
495 // emergency spill slot.
496 if (needsStackRealignment(MF) && (MFI->hasVarSizedObjects() ||
497 !TFI->hasReservedCallFrame(MF)))
500 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
501 // negative range for ldr/str (255), and thumb1 is positive offsets only.
502 // It's going to be better to use the SP or Base Pointer instead. When there
503 // are variable sized objects, we can't reference off of the SP, so we
504 // reserve a Base Pointer.
505 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
506 // Conservatively estimate whether the negative offset from the frame
507 // pointer will be sufficient to reach. If a function has a smallish
508 // frame, it's less likely to have lots of spills and callee saved
509 // space, so it's all more likely to be within range of the frame pointer.
510 // If it's wrong, the scavenger will still enable access to work, it just
512 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
520 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
521 const MachineFrameInfo *MFI = MF.getFrameInfo();
522 const MachineRegisterInfo *MRI = &MF.getRegInfo();
523 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
524 // We can't realign the stack if:
525 // 1. Dynamic stack realignment is explicitly disabled,
526 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
527 // 3. There are VLAs in the function and the base pointer is disabled.
528 if (!MF.getTarget().Options.RealignStack)
530 if (AFI->isThumb1OnlyFunction())
532 // Stack realignment requires a frame pointer. If we already started
533 // register allocation with frame pointer elimination, it is too late now.
534 if (!MRI->canReserveReg(FramePtr))
536 // We may also need a base pointer if there are dynamic allocas.
537 if (!MFI->hasVarSizedObjects())
539 if (!EnableBasePointer)
541 // A base pointer is required and allowed. Check that it isn't too late to
543 return MRI->canReserveReg(BasePtr);
546 bool ARMBaseRegisterInfo::
547 needsStackRealignment(const MachineFunction &MF) const {
548 const MachineFrameInfo *MFI = MF.getFrameInfo();
549 const Function *F = MF.getFunction();
550 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
551 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
552 F->hasFnAttr(Attribute::StackAlignment));
554 return requiresRealignment && canRealignStack(MF);
557 bool ARMBaseRegisterInfo::
558 cannotEliminateFrame(const MachineFunction &MF) const {
559 const MachineFrameInfo *MFI = MF.getFrameInfo();
560 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
562 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
563 || needsStackRealignment(MF);
567 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
568 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
575 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
576 llvm_unreachable("What is the exception register");
579 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
580 llvm_unreachable("What is the exception handler register");
583 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
584 const MachineFunction &MF) const {
587 // Return 0 if either register of the pair is a special register.
589 case ARM::R1: return ARM::R0;
590 case ARM::R3: return ARM::R2;
591 case ARM::R5: return ARM::R4;
593 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
595 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
596 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
598 case ARM::S1: return ARM::S0;
599 case ARM::S3: return ARM::S2;
600 case ARM::S5: return ARM::S4;
601 case ARM::S7: return ARM::S6;
602 case ARM::S9: return ARM::S8;
603 case ARM::S11: return ARM::S10;
604 case ARM::S13: return ARM::S12;
605 case ARM::S15: return ARM::S14;
606 case ARM::S17: return ARM::S16;
607 case ARM::S19: return ARM::S18;
608 case ARM::S21: return ARM::S20;
609 case ARM::S23: return ARM::S22;
610 case ARM::S25: return ARM::S24;
611 case ARM::S27: return ARM::S26;
612 case ARM::S29: return ARM::S28;
613 case ARM::S31: return ARM::S30;
615 case ARM::D1: return ARM::D0;
616 case ARM::D3: return ARM::D2;
617 case ARM::D5: return ARM::D4;
618 case ARM::D7: return ARM::D6;
619 case ARM::D9: return ARM::D8;
620 case ARM::D11: return ARM::D10;
621 case ARM::D13: return ARM::D12;
622 case ARM::D15: return ARM::D14;
623 case ARM::D17: return ARM::D16;
624 case ARM::D19: return ARM::D18;
625 case ARM::D21: return ARM::D20;
626 case ARM::D23: return ARM::D22;
627 case ARM::D25: return ARM::D24;
628 case ARM::D27: return ARM::D26;
629 case ARM::D29: return ARM::D28;
630 case ARM::D31: return ARM::D30;
636 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
637 const MachineFunction &MF) const {
640 // Return 0 if either register of the pair is a special register.
642 case ARM::R0: return ARM::R1;
643 case ARM::R2: return ARM::R3;
644 case ARM::R4: return ARM::R5;
646 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
648 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
649 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
651 case ARM::S0: return ARM::S1;
652 case ARM::S2: return ARM::S3;
653 case ARM::S4: return ARM::S5;
654 case ARM::S6: return ARM::S7;
655 case ARM::S8: return ARM::S9;
656 case ARM::S10: return ARM::S11;
657 case ARM::S12: return ARM::S13;
658 case ARM::S14: return ARM::S15;
659 case ARM::S16: return ARM::S17;
660 case ARM::S18: return ARM::S19;
661 case ARM::S20: return ARM::S21;
662 case ARM::S22: return ARM::S23;
663 case ARM::S24: return ARM::S25;
664 case ARM::S26: return ARM::S27;
665 case ARM::S28: return ARM::S29;
666 case ARM::S30: return ARM::S31;
668 case ARM::D0: return ARM::D1;
669 case ARM::D2: return ARM::D3;
670 case ARM::D4: return ARM::D5;
671 case ARM::D6: return ARM::D7;
672 case ARM::D8: return ARM::D9;
673 case ARM::D10: return ARM::D11;
674 case ARM::D12: return ARM::D13;
675 case ARM::D14: return ARM::D15;
676 case ARM::D16: return ARM::D17;
677 case ARM::D18: return ARM::D19;
678 case ARM::D20: return ARM::D21;
679 case ARM::D22: return ARM::D23;
680 case ARM::D24: return ARM::D25;
681 case ARM::D26: return ARM::D27;
682 case ARM::D28: return ARM::D29;
683 case ARM::D30: return ARM::D31;
689 /// emitLoadConstPool - Emits a load from constpool to materialize the
690 /// specified immediate.
691 void ARMBaseRegisterInfo::
692 emitLoadConstPool(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator &MBBI,
695 unsigned DestReg, unsigned SubIdx, int Val,
696 ARMCC::CondCodes Pred,
697 unsigned PredReg, unsigned MIFlags) const {
698 MachineFunction &MF = *MBB.getParent();
699 MachineConstantPool *ConstantPool = MF.getConstantPool();
701 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
702 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
704 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
705 .addReg(DestReg, getDefRegState(true), SubIdx)
706 .addConstantPoolIndex(Idx)
707 .addImm(0).addImm(Pred).addReg(PredReg)
708 .setMIFlags(MIFlags);
711 bool ARMBaseRegisterInfo::
712 requiresRegisterScavenging(const MachineFunction &MF) const {
716 bool ARMBaseRegisterInfo::
717 requiresFrameIndexScavenging(const MachineFunction &MF) const {
721 bool ARMBaseRegisterInfo::
722 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
723 return EnableLocalStackAlloc;
727 emitSPUpdate(bool isARM,
728 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
729 DebugLoc dl, const ARMBaseInstrInfo &TII,
731 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
733 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
736 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
741 void ARMBaseRegisterInfo::
742 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
743 MachineBasicBlock::iterator I) const {
744 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
745 if (!TFI->hasReservedCallFrame(MF)) {
746 // If we have alloca, convert as follows:
747 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
748 // ADJCALLSTACKUP -> add, sp, sp, amount
749 MachineInstr *Old = I;
750 DebugLoc dl = Old->getDebugLoc();
751 unsigned Amount = Old->getOperand(0).getImm();
753 // We need to keep the stack aligned properly. To do this, we round the
754 // amount of space needed for the outgoing arguments up to the next
755 // alignment boundary.
756 unsigned Align = TFI->getStackAlignment();
757 Amount = (Amount+Align-1)/Align*Align;
759 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
760 assert(!AFI->isThumb1OnlyFunction() &&
761 "This eliminateCallFramePseudoInstr does not support Thumb1!");
762 bool isARM = !AFI->isThumbFunction();
764 // Replace the pseudo instruction with a new instruction...
765 unsigned Opc = Old->getOpcode();
766 int PIdx = Old->findFirstPredOperandIdx();
767 ARMCC::CondCodes Pred = (PIdx == -1)
768 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
769 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
770 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
771 unsigned PredReg = Old->getOperand(2).getReg();
772 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
774 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
775 unsigned PredReg = Old->getOperand(3).getReg();
776 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
777 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
784 int64_t ARMBaseRegisterInfo::
785 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
786 const MCInstrDesc &Desc = MI->getDesc();
787 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
788 int64_t InstrOffs = 0;
792 case ARMII::AddrModeT2_i8:
793 case ARMII::AddrModeT2_i12:
794 case ARMII::AddrMode_i12:
795 InstrOffs = MI->getOperand(Idx+1).getImm();
798 case ARMII::AddrMode5: {
800 const MachineOperand &OffOp = MI->getOperand(Idx+1);
801 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
802 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
803 InstrOffs = -InstrOffs;
807 case ARMII::AddrMode2: {
809 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
810 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
811 InstrOffs = -InstrOffs;
814 case ARMII::AddrMode3: {
816 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
817 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
818 InstrOffs = -InstrOffs;
821 case ARMII::AddrModeT1_s: {
823 InstrOffs = MI->getOperand(ImmIdx).getImm();
828 llvm_unreachable("Unsupported addressing mode!");
831 return InstrOffs * Scale;
834 /// needsFrameBaseReg - Returns true if the instruction's frame index
835 /// reference would be better served by a base register other than FP
836 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
837 /// references it should create new base registers for.
838 bool ARMBaseRegisterInfo::
839 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
840 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
841 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
844 // It's the load/store FI references that cause issues, as it can be difficult
845 // to materialize the offset if it won't fit in the literal field. Estimate
846 // based on the size of the local frame and some conservative assumptions
847 // about the rest of the stack frame (note, this is pre-regalloc, so
848 // we don't know everything for certain yet) whether this offset is likely
849 // to be out of range of the immediate. Return true if so.
851 // We only generate virtual base registers for loads and stores, so
852 // return false for everything else.
853 unsigned Opc = MI->getOpcode();
855 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
856 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
857 case ARM::t2LDRi12: case ARM::t2LDRi8:
858 case ARM::t2STRi12: case ARM::t2STRi8:
859 case ARM::VLDRS: case ARM::VLDRD:
860 case ARM::VSTRS: case ARM::VSTRD:
861 case ARM::tSTRspi: case ARM::tLDRspi:
862 if (ForceAllBaseRegAlloc)
869 // Without a virtual base register, if the function has variable sized
870 // objects, all fixed-size local references will be via the frame pointer,
871 // Approximate the offset and see if it's legal for the instruction.
872 // Note that the incoming offset is based on the SP value at function entry,
873 // so it'll be negative.
874 MachineFunction &MF = *MI->getParent()->getParent();
875 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
876 MachineFrameInfo *MFI = MF.getFrameInfo();
877 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
879 // Estimate an offset from the frame pointer.
880 // Conservatively assume all callee-saved registers get pushed. R4-R6
881 // will be earlier than the FP, so we ignore those.
883 int64_t FPOffset = Offset - 8;
884 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
885 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
887 // Estimate an offset from the stack pointer.
888 // The incoming offset is relating to the SP at the start of the function,
889 // but when we access the local it'll be relative to the SP after local
890 // allocation, so adjust our SP-relative offset by that allocation size.
892 Offset += MFI->getLocalFrameSize();
893 // Assume that we'll have at least some spill slots allocated.
894 // FIXME: This is a total SWAG number. We should run some statistics
895 // and pick a real one.
896 Offset += 128; // 128 bytes of spill slots
898 // If there is a frame pointer, try using it.
899 // The FP is only available if there is no dynamic realignment. We
900 // don't know for sure yet whether we'll need that, so we guess based
901 // on whether there are any local variables that would trigger it.
902 unsigned StackAlign = TFI->getStackAlignment();
903 if (TFI->hasFP(MF) &&
904 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
905 if (isFrameOffsetLegal(MI, FPOffset))
908 // If we can reference via the stack pointer, try that.
909 // FIXME: This (and the code that resolves the references) can be improved
910 // to only disallow SP relative references in the live range of
911 // the VLA(s). In practice, it's unclear how much difference that
912 // would make, but it may be worth doing.
913 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
916 // The offset likely isn't legal, we want to allocate a virtual base register.
920 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
921 /// be a pointer to FrameIdx at the beginning of the basic block.
922 void ARMBaseRegisterInfo::
923 materializeFrameBaseRegister(MachineBasicBlock *MBB,
924 unsigned BaseReg, int FrameIdx,
925 int64_t Offset) const {
926 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
927 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
928 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
930 MachineBasicBlock::iterator Ins = MBB->begin();
931 DebugLoc DL; // Defaults to "unknown"
932 if (Ins != MBB->end())
933 DL = Ins->getDebugLoc();
935 const MCInstrDesc &MCID = TII.get(ADDriOpc);
936 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
937 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
939 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
940 .addFrameIndex(FrameIdx).addImm(Offset));
942 if (!AFI->isThumb1OnlyFunction())
947 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
948 unsigned BaseReg, int64_t Offset) const {
949 MachineInstr &MI = *I;
950 MachineBasicBlock &MBB = *MI.getParent();
951 MachineFunction &MF = *MBB.getParent();
952 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
953 int Off = Offset; // ARM doesn't need the general 64-bit offsets
956 assert(!AFI->isThumb1OnlyFunction() &&
957 "This resolveFrameIndex does not support Thumb1!");
959 while (!MI.getOperand(i).isFI()) {
961 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
964 if (!AFI->isThumbFunction())
965 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
967 assert(AFI->isThumb2Function());
968 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
970 assert (Done && "Unable to resolve frame index!");
974 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
975 int64_t Offset) const {
976 const MCInstrDesc &Desc = MI->getDesc();
977 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
980 while (!MI->getOperand(i).isFI()) {
982 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
985 // AddrMode4 and AddrMode6 cannot handle any offset.
986 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
989 unsigned NumBits = 0;
991 bool isSigned = true;
993 case ARMII::AddrModeT2_i8:
994 case ARMII::AddrModeT2_i12:
995 // i8 supports only negative, and i12 supports only positive, so
996 // based on Offset sign, consider the appropriate instruction
1005 case ARMII::AddrMode5:
1006 // VFP address mode.
1010 case ARMII::AddrMode_i12:
1011 case ARMII::AddrMode2:
1014 case ARMII::AddrMode3:
1017 case ARMII::AddrModeT1_s:
1023 llvm_unreachable("Unsupported addressing mode!");
1026 Offset += getFrameIndexInstrOffset(MI, i);
1027 // Make sure the offset is encodable for instructions that scale the
1029 if ((Offset & (Scale-1)) != 0)
1032 if (isSigned && Offset < 0)
1035 unsigned Mask = (1 << NumBits) - 1;
1036 if ((unsigned)Offset <= Mask * Scale)
1043 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1044 int SPAdj, RegScavenger *RS) const {
1046 MachineInstr &MI = *II;
1047 MachineBasicBlock &MBB = *MI.getParent();
1048 MachineFunction &MF = *MBB.getParent();
1049 const ARMFrameLowering *TFI =
1050 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1051 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1052 assert(!AFI->isThumb1OnlyFunction() &&
1053 "This eliminateFrameIndex does not support Thumb1!");
1055 while (!MI.getOperand(i).isFI()) {
1057 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1060 int FrameIndex = MI.getOperand(i).getIndex();
1063 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1065 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
1066 // call frame setup/destroy instructions have already been eliminated. That
1067 // means the stack pointer cannot be used to access the emergency spill slot
1068 // when !hasReservedCallFrame().
1070 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1071 assert(TFI->hasReservedCallFrame(MF) &&
1072 "Cannot use SP to access the emergency spill slot in "
1073 "functions without a reserved call frame");
1074 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
1075 "Cannot use SP to access the emergency spill slot in "
1076 "functions with variable sized frame objects");
1080 // Special handling of dbg_value instructions.
1081 if (MI.isDebugValue()) {
1082 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1083 MI.getOperand(i+1).ChangeToImmediate(Offset);
1087 // Modify MI as necessary to handle as much of 'Offset' as possible
1089 if (!AFI->isThumbFunction())
1090 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1092 assert(AFI->isThumb2Function());
1093 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1098 // If we get here, the immediate doesn't fit into the instruction. We folded
1099 // as much as possible above, handle the rest, providing a register that is
1102 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1103 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1104 "This code isn't needed if offset already handled!");
1106 unsigned ScratchReg = 0;
1107 int PIdx = MI.findFirstPredOperandIdx();
1108 ARMCC::CondCodes Pred = (PIdx == -1)
1109 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1110 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1112 // Must be addrmode4/6.
1113 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1115 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1116 if (!AFI->isThumbFunction())
1117 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1118 Offset, Pred, PredReg, TII);
1120 assert(AFI->isThumb2Function());
1121 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1122 Offset, Pred, PredReg, TII);
1124 // Update the original instruction to use the scratch register.
1125 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);