1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
53 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
57 const Function *F = MF->getFunction();
58 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
62 return CSR_GHC_SaveList;
65 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
66 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
71 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
72 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
73 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
77 ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const {
78 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
79 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask;
83 ARMBaseRegisterInfo::getNoPreservedMask() const {
84 return CSR_NoRegs_RegMask;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // FIXME: avoid re-calculating this every time.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
96 Reserved.set(ARM::APSR_NZCV);
98 Reserved.set(FramePtr);
99 if (hasBasePointer(MF))
100 Reserved.set(BasePtr);
101 // Some targets reserve R9.
102 if (STI.isR9Reserved())
103 Reserved.set(ARM::R9);
104 // Reserve D16-D31 if the subtarget doesn't support them.
105 if (!STI.hasVFP3() || STI.hasD16()) {
106 assert(ARM::D31 == ARM::D16 + 15);
107 for (unsigned i = 0; i != 16; ++i)
108 Reserved.set(ARM::D16 + i);
110 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
111 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
112 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
113 if (Reserved.test(*SI)) Reserved.set(*I);
118 const TargetRegisterClass*
119 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
121 const TargetRegisterClass *Super = RC;
122 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
124 switch (Super->getID()) {
125 case ARM::GPRRegClassID:
126 case ARM::SPRRegClassID:
127 case ARM::DPRRegClassID:
128 case ARM::QPRRegClassID:
129 case ARM::QQPRRegClassID:
130 case ARM::QQQQPRRegClassID:
131 case ARM::GPRPairRegClassID:
139 const TargetRegisterClass *
140 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
142 return &ARM::GPRRegClass;
145 const TargetRegisterClass *
146 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
147 if (RC == &ARM::CCRRegClass)
148 return 0; // Can't copy CCR registers.
153 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
154 MachineFunction &MF) const {
155 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
157 switch (RC->getID()) {
160 case ARM::tGPRRegClassID:
161 return TFI->hasFP(MF) ? 4 : 5;
162 case ARM::GPRRegClassID: {
163 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
164 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
166 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
167 case ARM::DPRRegClassID:
172 // Get the other register in a GPRPair.
173 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
174 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
175 if (ARM::GPRPairRegClass.contains(*Supers))
176 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
180 // Resolve the RegPairEven / RegPairOdd register allocator hints.
182 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
183 ArrayRef<MCPhysReg> Order,
184 SmallVectorImpl<MCPhysReg> &Hints,
185 const MachineFunction &MF,
186 const VirtRegMap *VRM) const {
187 const MachineRegisterInfo &MRI = MF.getRegInfo();
188 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
191 switch (Hint.first) {
192 case ARMRI::RegPairEven:
195 case ARMRI::RegPairOdd:
199 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
203 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
204 // Check if the other part of the pair has already been assigned, and provide
205 // the paired register as the first hint.
206 unsigned PairedPhys = 0;
207 if (VRM && VRM->hasPhys(Hint.second)) {
208 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
209 if (PairedPhys && MRI.isReserved(PairedPhys))
213 // First prefer the paired physreg.
215 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
216 Hints.push_back(PairedPhys);
218 // Then prefer even or odd registers.
219 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
220 unsigned Reg = Order[I];
221 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
223 // Don't provide hints that are paired to a reserved register.
224 unsigned Paired = getPairedGPR(Reg, !Odd, this);
225 if (!Paired || MRI.isReserved(Paired))
227 Hints.push_back(Reg);
232 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
233 MachineFunction &MF) const {
234 MachineRegisterInfo *MRI = &MF.getRegInfo();
235 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
236 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
237 Hint.first == (unsigned)ARMRI::RegPairEven) &&
238 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
239 // If 'Reg' is one of the even / odd register pair and it's now changed
240 // (e.g. coalesced) into a different register. The other register of the
241 // pair allocation hint must be updated to reflect the relationship
243 unsigned OtherReg = Hint.second;
244 Hint = MRI->getRegAllocationHint(OtherReg);
245 if (Hint.second == Reg)
246 // Make sure the pair has not already divorced.
247 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
252 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
253 // CortexA9 has a Write-after-write hazard for NEON registers.
257 switch (RC->getID()) {
258 case ARM::DPRRegClassID:
259 case ARM::DPR_8RegClassID:
260 case ARM::DPR_VFP2RegClassID:
261 case ARM::QPRRegClassID:
262 case ARM::QPR_8RegClassID:
263 case ARM::QPR_VFP2RegClassID:
264 case ARM::SPRRegClassID:
265 case ARM::SPR_8RegClassID:
266 // Avoid reusing S, D, and Q registers.
267 // Don't increase register pressure for QQ and QQQQ.
274 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
275 const MachineFrameInfo *MFI = MF.getFrameInfo();
276 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
277 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
279 // When outgoing call frames are so large that we adjust the stack pointer
280 // around the call, we can no longer use the stack pointer to reach the
281 // emergency spill slot.
282 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
285 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
286 // negative range for ldr/str (255), and thumb1 is positive offsets only.
287 // It's going to be better to use the SP or Base Pointer instead. When there
288 // are variable sized objects, we can't reference off of the SP, so we
289 // reserve a Base Pointer.
290 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
291 // Conservatively estimate whether the negative offset from the frame
292 // pointer will be sufficient to reach. If a function has a smallish
293 // frame, it's less likely to have lots of spills and callee saved
294 // space, so it's all more likely to be within range of the frame pointer.
295 // If it's wrong, the scavenger will still enable access to work, it just
297 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
305 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
306 const MachineRegisterInfo *MRI = &MF.getRegInfo();
307 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
308 // We can't realign the stack if:
309 // 1. Dynamic stack realignment is explicitly disabled,
310 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
311 // 3. There are VLAs in the function and the base pointer is disabled.
312 if (!MF.getTarget().Options.RealignStack)
314 if (AFI->isThumb1OnlyFunction())
316 // Stack realignment requires a frame pointer. If we already started
317 // register allocation with frame pointer elimination, it is too late now.
318 if (!MRI->canReserveReg(FramePtr))
320 // We may also need a base pointer if there are dynamic allocas or stack
321 // pointer adjustments around calls.
322 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
324 // A base pointer is required and allowed. Check that it isn't too late to
326 return MRI->canReserveReg(BasePtr);
329 bool ARMBaseRegisterInfo::
330 needsStackRealignment(const MachineFunction &MF) const {
331 const MachineFrameInfo *MFI = MF.getFrameInfo();
332 const Function *F = MF.getFunction();
333 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
334 bool requiresRealignment =
335 ((MFI->getMaxAlignment() > StackAlign) ||
336 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
337 Attribute::StackAlignment));
339 return requiresRealignment && canRealignStack(MF);
342 bool ARMBaseRegisterInfo::
343 cannotEliminateFrame(const MachineFunction &MF) const {
344 const MachineFrameInfo *MFI = MF.getFrameInfo();
345 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
347 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
348 || needsStackRealignment(MF);
352 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
353 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
360 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
361 llvm_unreachable("What is the exception register");
364 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
365 llvm_unreachable("What is the exception handler register");
368 /// emitLoadConstPool - Emits a load from constpool to materialize the
369 /// specified immediate.
370 void ARMBaseRegisterInfo::
371 emitLoadConstPool(MachineBasicBlock &MBB,
372 MachineBasicBlock::iterator &MBBI,
374 unsigned DestReg, unsigned SubIdx, int Val,
375 ARMCC::CondCodes Pred,
376 unsigned PredReg, unsigned MIFlags) const {
377 MachineFunction &MF = *MBB.getParent();
378 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
379 MachineConstantPool *ConstantPool = MF.getConstantPool();
381 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
382 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
384 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
385 .addReg(DestReg, getDefRegState(true), SubIdx)
386 .addConstantPoolIndex(Idx)
387 .addImm(0).addImm(Pred).addReg(PredReg)
388 .setMIFlags(MIFlags);
391 bool ARMBaseRegisterInfo::
392 requiresRegisterScavenging(const MachineFunction &MF) const {
396 bool ARMBaseRegisterInfo::
397 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
401 bool ARMBaseRegisterInfo::
402 requiresFrameIndexScavenging(const MachineFunction &MF) const {
406 bool ARMBaseRegisterInfo::
407 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
411 int64_t ARMBaseRegisterInfo::
412 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
413 const MCInstrDesc &Desc = MI->getDesc();
414 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
415 int64_t InstrOffs = 0;
419 case ARMII::AddrModeT2_i8:
420 case ARMII::AddrModeT2_i12:
421 case ARMII::AddrMode_i12:
422 InstrOffs = MI->getOperand(Idx+1).getImm();
425 case ARMII::AddrMode5: {
427 const MachineOperand &OffOp = MI->getOperand(Idx+1);
428 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
429 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
430 InstrOffs = -InstrOffs;
434 case ARMII::AddrMode2: {
436 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
437 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
438 InstrOffs = -InstrOffs;
441 case ARMII::AddrMode3: {
443 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
444 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
445 InstrOffs = -InstrOffs;
448 case ARMII::AddrModeT1_s: {
450 InstrOffs = MI->getOperand(ImmIdx).getImm();
455 llvm_unreachable("Unsupported addressing mode!");
458 return InstrOffs * Scale;
461 /// needsFrameBaseReg - Returns true if the instruction's frame index
462 /// reference would be better served by a base register other than FP
463 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
464 /// references it should create new base registers for.
465 bool ARMBaseRegisterInfo::
466 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
467 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
468 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
471 // It's the load/store FI references that cause issues, as it can be difficult
472 // to materialize the offset if it won't fit in the literal field. Estimate
473 // based on the size of the local frame and some conservative assumptions
474 // about the rest of the stack frame (note, this is pre-regalloc, so
475 // we don't know everything for certain yet) whether this offset is likely
476 // to be out of range of the immediate. Return true if so.
478 // We only generate virtual base registers for loads and stores, so
479 // return false for everything else.
480 unsigned Opc = MI->getOpcode();
482 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
483 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
484 case ARM::t2LDRi12: case ARM::t2LDRi8:
485 case ARM::t2STRi12: case ARM::t2STRi8:
486 case ARM::VLDRS: case ARM::VLDRD:
487 case ARM::VSTRS: case ARM::VSTRD:
488 case ARM::tSTRspi: case ARM::tLDRspi:
494 // Without a virtual base register, if the function has variable sized
495 // objects, all fixed-size local references will be via the frame pointer,
496 // Approximate the offset and see if it's legal for the instruction.
497 // Note that the incoming offset is based on the SP value at function entry,
498 // so it'll be negative.
499 MachineFunction &MF = *MI->getParent()->getParent();
500 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
501 MachineFrameInfo *MFI = MF.getFrameInfo();
502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
504 // Estimate an offset from the frame pointer.
505 // Conservatively assume all callee-saved registers get pushed. R4-R6
506 // will be earlier than the FP, so we ignore those.
508 int64_t FPOffset = Offset - 8;
509 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
510 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
512 // Estimate an offset from the stack pointer.
513 // The incoming offset is relating to the SP at the start of the function,
514 // but when we access the local it'll be relative to the SP after local
515 // allocation, so adjust our SP-relative offset by that allocation size.
517 Offset += MFI->getLocalFrameSize();
518 // Assume that we'll have at least some spill slots allocated.
519 // FIXME: This is a total SWAG number. We should run some statistics
520 // and pick a real one.
521 Offset += 128; // 128 bytes of spill slots
523 // If there is a frame pointer, try using it.
524 // The FP is only available if there is no dynamic realignment. We
525 // don't know for sure yet whether we'll need that, so we guess based
526 // on whether there are any local variables that would trigger it.
527 unsigned StackAlign = TFI->getStackAlignment();
528 if (TFI->hasFP(MF) &&
529 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
530 if (isFrameOffsetLegal(MI, FPOffset))
533 // If we can reference via the stack pointer, try that.
534 // FIXME: This (and the code that resolves the references) can be improved
535 // to only disallow SP relative references in the live range of
536 // the VLA(s). In practice, it's unclear how much difference that
537 // would make, but it may be worth doing.
538 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
541 // The offset likely isn't legal, we want to allocate a virtual base register.
545 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
546 /// be a pointer to FrameIdx at the beginning of the basic block.
547 void ARMBaseRegisterInfo::
548 materializeFrameBaseRegister(MachineBasicBlock *MBB,
549 unsigned BaseReg, int FrameIdx,
550 int64_t Offset) const {
551 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
552 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
553 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
555 MachineBasicBlock::iterator Ins = MBB->begin();
556 DebugLoc DL; // Defaults to "unknown"
557 if (Ins != MBB->end())
558 DL = Ins->getDebugLoc();
560 const MachineFunction &MF = *MBB->getParent();
561 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
562 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
563 const MCInstrDesc &MCID = TII.get(ADDriOpc);
564 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
566 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
567 .addFrameIndex(FrameIdx).addImm(Offset));
569 if (!AFI->isThumb1OnlyFunction())
574 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
575 unsigned BaseReg, int64_t Offset) const {
576 MachineInstr &MI = *I;
577 MachineBasicBlock &MBB = *MI.getParent();
578 MachineFunction &MF = *MBB.getParent();
579 const ARMBaseInstrInfo &TII =
580 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
581 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
582 int Off = Offset; // ARM doesn't need the general 64-bit offsets
585 assert(!AFI->isThumb1OnlyFunction() &&
586 "This resolveFrameIndex does not support Thumb1!");
588 while (!MI.getOperand(i).isFI()) {
590 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
593 if (!AFI->isThumbFunction())
594 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
596 assert(AFI->isThumb2Function());
597 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
599 assert (Done && "Unable to resolve frame index!");
603 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
604 int64_t Offset) const {
605 const MCInstrDesc &Desc = MI->getDesc();
606 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
609 while (!MI->getOperand(i).isFI()) {
611 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
614 // AddrMode4 and AddrMode6 cannot handle any offset.
615 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
618 unsigned NumBits = 0;
620 bool isSigned = true;
622 case ARMII::AddrModeT2_i8:
623 case ARMII::AddrModeT2_i12:
624 // i8 supports only negative, and i12 supports only positive, so
625 // based on Offset sign, consider the appropriate instruction
634 case ARMII::AddrMode5:
639 case ARMII::AddrMode_i12:
640 case ARMII::AddrMode2:
643 case ARMII::AddrMode3:
646 case ARMII::AddrModeT1_s:
652 llvm_unreachable("Unsupported addressing mode!");
655 Offset += getFrameIndexInstrOffset(MI, i);
656 // Make sure the offset is encodable for instructions that scale the
658 if ((Offset & (Scale-1)) != 0)
661 if (isSigned && Offset < 0)
664 unsigned Mask = (1 << NumBits) - 1;
665 if ((unsigned)Offset <= Mask * Scale)
672 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
673 int SPAdj, unsigned FIOperandNum,
674 RegScavenger *RS) const {
675 MachineInstr &MI = *II;
676 MachineBasicBlock &MBB = *MI.getParent();
677 MachineFunction &MF = *MBB.getParent();
678 const ARMBaseInstrInfo &TII =
679 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
680 const ARMFrameLowering *TFI =
681 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
682 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
683 assert(!AFI->isThumb1OnlyFunction() &&
684 "This eliminateFrameIndex does not support Thumb1!");
685 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
688 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
690 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
691 // call frame setup/destroy instructions have already been eliminated. That
692 // means the stack pointer cannot be used to access the emergency spill slot
693 // when !hasReservedCallFrame().
695 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
696 assert(TFI->hasReservedCallFrame(MF) &&
697 "Cannot use SP to access the emergency spill slot in "
698 "functions without a reserved call frame");
699 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
700 "Cannot use SP to access the emergency spill slot in "
701 "functions with variable sized frame objects");
705 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
707 // Modify MI as necessary to handle as much of 'Offset' as possible
709 if (!AFI->isThumbFunction())
710 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
712 assert(AFI->isThumb2Function());
713 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
718 // If we get here, the immediate doesn't fit into the instruction. We folded
719 // as much as possible above, handle the rest, providing a register that is
722 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
723 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
724 "This code isn't needed if offset already handled!");
726 unsigned ScratchReg = 0;
727 int PIdx = MI.findFirstPredOperandIdx();
728 ARMCC::CondCodes Pred = (PIdx == -1)
729 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
730 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
732 // Must be addrmode4/6.
733 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
735 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
736 if (!AFI->isThumbFunction())
737 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
738 Offset, Pred, PredReg, TII);
740 assert(AFI->isThumb2Function());
741 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
742 Offset, Pred, PredReg, TII);
744 // Update the original instruction to use the scratch register.
745 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);