1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
53 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
57 const Function *F = MF->getFunction();
58 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
62 return CSR_GHC_SaveList;
64 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
65 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
69 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
70 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
71 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
75 ARMBaseRegisterInfo::getNoPreservedMask() const {
76 return CSR_NoRegs_RegMask;
80 ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const {
81 // This should return a register mask that is the same as that returned by
82 // getCallPreservedMask but that additionally preserves the register used for
83 // the first i32 argument (which must also be the register used to return a
84 // single i32 return value)
86 // In case that the calling convention does not use the same register for
87 // both, the function should return NULL (does not currently apply)
88 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
89 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask;
92 BitVector ARMBaseRegisterInfo::
93 getReservedRegs(const MachineFunction &MF) const {
94 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
96 // FIXME: avoid re-calculating this every time.
97 BitVector Reserved(getNumRegs());
98 Reserved.set(ARM::SP);
99 Reserved.set(ARM::PC);
100 Reserved.set(ARM::FPSCR);
101 Reserved.set(ARM::APSR_NZCV);
103 Reserved.set(FramePtr);
104 if (hasBasePointer(MF))
105 Reserved.set(BasePtr);
106 // Some targets reserve R9.
107 if (STI.isR9Reserved())
108 Reserved.set(ARM::R9);
109 // Reserve D16-D31 if the subtarget doesn't support them.
110 if (!STI.hasVFP3() || STI.hasD16()) {
111 assert(ARM::D31 == ARM::D16 + 15);
112 for (unsigned i = 0; i != 16; ++i)
113 Reserved.set(ARM::D16 + i);
115 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
116 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
117 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
118 if (Reserved.test(*SI)) Reserved.set(*I);
123 const TargetRegisterClass*
124 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
126 const TargetRegisterClass *Super = RC;
127 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
129 switch (Super->getID()) {
130 case ARM::GPRRegClassID:
131 case ARM::SPRRegClassID:
132 case ARM::DPRRegClassID:
133 case ARM::QPRRegClassID:
134 case ARM::QQPRRegClassID:
135 case ARM::QQQQPRRegClassID:
136 case ARM::GPRPairRegClassID:
144 const TargetRegisterClass *
145 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
147 return &ARM::GPRRegClass;
150 const TargetRegisterClass *
151 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
152 if (RC == &ARM::CCRRegClass)
153 return 0; // Can't copy CCR registers.
158 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
159 MachineFunction &MF) const {
160 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
162 switch (RC->getID()) {
165 case ARM::tGPRRegClassID:
166 return TFI->hasFP(MF) ? 4 : 5;
167 case ARM::GPRRegClassID: {
168 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
169 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
171 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
172 case ARM::DPRRegClassID:
177 // Get the other register in a GPRPair.
178 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
179 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
180 if (ARM::GPRPairRegClass.contains(*Supers))
181 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
185 // Resolve the RegPairEven / RegPairOdd register allocator hints.
187 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
188 ArrayRef<MCPhysReg> Order,
189 SmallVectorImpl<MCPhysReg> &Hints,
190 const MachineFunction &MF,
191 const VirtRegMap *VRM) const {
192 const MachineRegisterInfo &MRI = MF.getRegInfo();
193 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
196 switch (Hint.first) {
197 case ARMRI::RegPairEven:
200 case ARMRI::RegPairOdd:
204 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
208 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
209 // Check if the other part of the pair has already been assigned, and provide
210 // the paired register as the first hint.
211 unsigned PairedPhys = 0;
212 if (VRM && VRM->hasPhys(Hint.second)) {
213 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
214 if (PairedPhys && MRI.isReserved(PairedPhys))
218 // First prefer the paired physreg.
220 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
221 Hints.push_back(PairedPhys);
223 // Then prefer even or odd registers.
224 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
225 unsigned Reg = Order[I];
226 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
228 // Don't provide hints that are paired to a reserved register.
229 unsigned Paired = getPairedGPR(Reg, !Odd, this);
230 if (!Paired || MRI.isReserved(Paired))
232 Hints.push_back(Reg);
237 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
238 MachineFunction &MF) const {
239 MachineRegisterInfo *MRI = &MF.getRegInfo();
240 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
241 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
242 Hint.first == (unsigned)ARMRI::RegPairEven) &&
243 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
244 // If 'Reg' is one of the even / odd register pair and it's now changed
245 // (e.g. coalesced) into a different register. The other register of the
246 // pair allocation hint must be updated to reflect the relationship
248 unsigned OtherReg = Hint.second;
249 Hint = MRI->getRegAllocationHint(OtherReg);
250 if (Hint.second == Reg)
251 // Make sure the pair has not already divorced.
252 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
257 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
258 // CortexA9 has a Write-after-write hazard for NEON registers.
262 switch (RC->getID()) {
263 case ARM::DPRRegClassID:
264 case ARM::DPR_8RegClassID:
265 case ARM::DPR_VFP2RegClassID:
266 case ARM::QPRRegClassID:
267 case ARM::QPR_8RegClassID:
268 case ARM::QPR_VFP2RegClassID:
269 case ARM::SPRRegClassID:
270 case ARM::SPR_8RegClassID:
271 // Avoid reusing S, D, and Q registers.
272 // Don't increase register pressure for QQ and QQQQ.
279 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
280 const MachineFrameInfo *MFI = MF.getFrameInfo();
281 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
282 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
284 // When outgoing call frames are so large that we adjust the stack pointer
285 // around the call, we can no longer use the stack pointer to reach the
286 // emergency spill slot.
287 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
290 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
291 // negative range for ldr/str (255), and thumb1 is positive offsets only.
292 // It's going to be better to use the SP or Base Pointer instead. When there
293 // are variable sized objects, we can't reference off of the SP, so we
294 // reserve a Base Pointer.
295 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
296 // Conservatively estimate whether the negative offset from the frame
297 // pointer will be sufficient to reach. If a function has a smallish
298 // frame, it's less likely to have lots of spills and callee saved
299 // space, so it's all more likely to be within range of the frame pointer.
300 // If it's wrong, the scavenger will still enable access to work, it just
302 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
310 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
311 const MachineRegisterInfo *MRI = &MF.getRegInfo();
312 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
313 // We can't realign the stack if:
314 // 1. Dynamic stack realignment is explicitly disabled,
315 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
316 // 3. There are VLAs in the function and the base pointer is disabled.
317 if (!MF.getTarget().Options.RealignStack)
319 if (AFI->isThumb1OnlyFunction())
321 // Stack realignment requires a frame pointer. If we already started
322 // register allocation with frame pointer elimination, it is too late now.
323 if (!MRI->canReserveReg(FramePtr))
325 // We may also need a base pointer if there are dynamic allocas or stack
326 // pointer adjustments around calls.
327 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
329 // A base pointer is required and allowed. Check that it isn't too late to
331 return MRI->canReserveReg(BasePtr);
334 bool ARMBaseRegisterInfo::
335 needsStackRealignment(const MachineFunction &MF) const {
336 const MachineFrameInfo *MFI = MF.getFrameInfo();
337 const Function *F = MF.getFunction();
338 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
339 bool requiresRealignment =
340 ((MFI->getMaxAlignment() > StackAlign) ||
341 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
342 Attribute::StackAlignment));
344 return requiresRealignment && canRealignStack(MF);
347 bool ARMBaseRegisterInfo::
348 cannotEliminateFrame(const MachineFunction &MF) const {
349 const MachineFrameInfo *MFI = MF.getFrameInfo();
350 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
352 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
353 || needsStackRealignment(MF);
357 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
358 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
365 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
366 llvm_unreachable("What is the exception register");
369 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
370 llvm_unreachable("What is the exception handler register");
373 /// emitLoadConstPool - Emits a load from constpool to materialize the
374 /// specified immediate.
375 void ARMBaseRegisterInfo::
376 emitLoadConstPool(MachineBasicBlock &MBB,
377 MachineBasicBlock::iterator &MBBI,
379 unsigned DestReg, unsigned SubIdx, int Val,
380 ARMCC::CondCodes Pred,
381 unsigned PredReg, unsigned MIFlags) const {
382 MachineFunction &MF = *MBB.getParent();
383 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
384 MachineConstantPool *ConstantPool = MF.getConstantPool();
386 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
387 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
389 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
390 .addReg(DestReg, getDefRegState(true), SubIdx)
391 .addConstantPoolIndex(Idx)
392 .addImm(0).addImm(Pred).addReg(PredReg)
393 .setMIFlags(MIFlags);
396 bool ARMBaseRegisterInfo::
397 requiresRegisterScavenging(const MachineFunction &MF) const {
401 bool ARMBaseRegisterInfo::
402 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
406 bool ARMBaseRegisterInfo::
407 requiresFrameIndexScavenging(const MachineFunction &MF) const {
411 bool ARMBaseRegisterInfo::
412 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
416 int64_t ARMBaseRegisterInfo::
417 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
418 const MCInstrDesc &Desc = MI->getDesc();
419 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
420 int64_t InstrOffs = 0;
424 case ARMII::AddrModeT2_i8:
425 case ARMII::AddrModeT2_i12:
426 case ARMII::AddrMode_i12:
427 InstrOffs = MI->getOperand(Idx+1).getImm();
430 case ARMII::AddrMode5: {
432 const MachineOperand &OffOp = MI->getOperand(Idx+1);
433 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
434 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
435 InstrOffs = -InstrOffs;
439 case ARMII::AddrMode2: {
441 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
442 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
443 InstrOffs = -InstrOffs;
446 case ARMII::AddrMode3: {
448 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
449 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
450 InstrOffs = -InstrOffs;
453 case ARMII::AddrModeT1_s: {
455 InstrOffs = MI->getOperand(ImmIdx).getImm();
460 llvm_unreachable("Unsupported addressing mode!");
463 return InstrOffs * Scale;
466 /// needsFrameBaseReg - Returns true if the instruction's frame index
467 /// reference would be better served by a base register other than FP
468 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
469 /// references it should create new base registers for.
470 bool ARMBaseRegisterInfo::
471 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
472 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
473 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
476 // It's the load/store FI references that cause issues, as it can be difficult
477 // to materialize the offset if it won't fit in the literal field. Estimate
478 // based on the size of the local frame and some conservative assumptions
479 // about the rest of the stack frame (note, this is pre-regalloc, so
480 // we don't know everything for certain yet) whether this offset is likely
481 // to be out of range of the immediate. Return true if so.
483 // We only generate virtual base registers for loads and stores, so
484 // return false for everything else.
485 unsigned Opc = MI->getOpcode();
487 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
488 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
489 case ARM::t2LDRi12: case ARM::t2LDRi8:
490 case ARM::t2STRi12: case ARM::t2STRi8:
491 case ARM::VLDRS: case ARM::VLDRD:
492 case ARM::VSTRS: case ARM::VSTRD:
493 case ARM::tSTRspi: case ARM::tLDRspi:
499 // Without a virtual base register, if the function has variable sized
500 // objects, all fixed-size local references will be via the frame pointer,
501 // Approximate the offset and see if it's legal for the instruction.
502 // Note that the incoming offset is based on the SP value at function entry,
503 // so it'll be negative.
504 MachineFunction &MF = *MI->getParent()->getParent();
505 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
506 MachineFrameInfo *MFI = MF.getFrameInfo();
507 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
509 // Estimate an offset from the frame pointer.
510 // Conservatively assume all callee-saved registers get pushed. R4-R6
511 // will be earlier than the FP, so we ignore those.
513 int64_t FPOffset = Offset - 8;
514 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
515 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
517 // Estimate an offset from the stack pointer.
518 // The incoming offset is relating to the SP at the start of the function,
519 // but when we access the local it'll be relative to the SP after local
520 // allocation, so adjust our SP-relative offset by that allocation size.
522 Offset += MFI->getLocalFrameSize();
523 // Assume that we'll have at least some spill slots allocated.
524 // FIXME: This is a total SWAG number. We should run some statistics
525 // and pick a real one.
526 Offset += 128; // 128 bytes of spill slots
528 // If there is a frame pointer, try using it.
529 // The FP is only available if there is no dynamic realignment. We
530 // don't know for sure yet whether we'll need that, so we guess based
531 // on whether there are any local variables that would trigger it.
532 unsigned StackAlign = TFI->getStackAlignment();
533 if (TFI->hasFP(MF) &&
534 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
535 if (isFrameOffsetLegal(MI, FPOffset))
538 // If we can reference via the stack pointer, try that.
539 // FIXME: This (and the code that resolves the references) can be improved
540 // to only disallow SP relative references in the live range of
541 // the VLA(s). In practice, it's unclear how much difference that
542 // would make, but it may be worth doing.
543 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
546 // The offset likely isn't legal, we want to allocate a virtual base register.
550 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
551 /// be a pointer to FrameIdx at the beginning of the basic block.
552 void ARMBaseRegisterInfo::
553 materializeFrameBaseRegister(MachineBasicBlock *MBB,
554 unsigned BaseReg, int FrameIdx,
555 int64_t Offset) const {
556 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
557 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
558 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
560 MachineBasicBlock::iterator Ins = MBB->begin();
561 DebugLoc DL; // Defaults to "unknown"
562 if (Ins != MBB->end())
563 DL = Ins->getDebugLoc();
565 const MachineFunction &MF = *MBB->getParent();
566 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
567 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
568 const MCInstrDesc &MCID = TII.get(ADDriOpc);
569 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
571 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
572 .addFrameIndex(FrameIdx).addImm(Offset));
574 if (!AFI->isThumb1OnlyFunction())
579 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
580 unsigned BaseReg, int64_t Offset) const {
581 MachineInstr &MI = *I;
582 MachineBasicBlock &MBB = *MI.getParent();
583 MachineFunction &MF = *MBB.getParent();
584 const ARMBaseInstrInfo &TII =
585 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
587 int Off = Offset; // ARM doesn't need the general 64-bit offsets
590 assert(!AFI->isThumb1OnlyFunction() &&
591 "This resolveFrameIndex does not support Thumb1!");
593 while (!MI.getOperand(i).isFI()) {
595 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
598 if (!AFI->isThumbFunction())
599 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
601 assert(AFI->isThumb2Function());
602 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
604 assert (Done && "Unable to resolve frame index!");
608 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
609 int64_t Offset) const {
610 const MCInstrDesc &Desc = MI->getDesc();
611 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
614 while (!MI->getOperand(i).isFI()) {
616 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
619 // AddrMode4 and AddrMode6 cannot handle any offset.
620 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
623 unsigned NumBits = 0;
625 bool isSigned = true;
627 case ARMII::AddrModeT2_i8:
628 case ARMII::AddrModeT2_i12:
629 // i8 supports only negative, and i12 supports only positive, so
630 // based on Offset sign, consider the appropriate instruction
639 case ARMII::AddrMode5:
644 case ARMII::AddrMode_i12:
645 case ARMII::AddrMode2:
648 case ARMII::AddrMode3:
651 case ARMII::AddrModeT1_s:
657 llvm_unreachable("Unsupported addressing mode!");
660 Offset += getFrameIndexInstrOffset(MI, i);
661 // Make sure the offset is encodable for instructions that scale the
663 if ((Offset & (Scale-1)) != 0)
666 if (isSigned && Offset < 0)
669 unsigned Mask = (1 << NumBits) - 1;
670 if ((unsigned)Offset <= Mask * Scale)
677 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
678 int SPAdj, unsigned FIOperandNum,
679 RegScavenger *RS) const {
680 MachineInstr &MI = *II;
681 MachineBasicBlock &MBB = *MI.getParent();
682 MachineFunction &MF = *MBB.getParent();
683 const ARMBaseInstrInfo &TII =
684 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
685 const ARMFrameLowering *TFI =
686 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
687 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
688 assert(!AFI->isThumb1OnlyFunction() &&
689 "This eliminateFrameIndex does not support Thumb1!");
690 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
693 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
695 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
696 // call frame setup/destroy instructions have already been eliminated. That
697 // means the stack pointer cannot be used to access the emergency spill slot
698 // when !hasReservedCallFrame().
700 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
701 assert(TFI->hasReservedCallFrame(MF) &&
702 "Cannot use SP to access the emergency spill slot in "
703 "functions without a reserved call frame");
704 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
705 "Cannot use SP to access the emergency spill slot in "
706 "functions with variable sized frame objects");
710 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
712 // Modify MI as necessary to handle as much of 'Offset' as possible
714 if (!AFI->isThumbFunction())
715 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
717 assert(AFI->isThumb2Function());
718 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
723 // If we get here, the immediate doesn't fit into the instruction. We folded
724 // as much as possible above, handle the rest, providing a register that is
727 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
728 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
729 "This code isn't needed if offset already handled!");
731 unsigned ScratchReg = 0;
732 int PIdx = MI.findFirstPredOperandIdx();
733 ARMCC::CondCodes Pred = (PIdx == -1)
734 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
735 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
737 // Must be addrmode4/6.
738 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
740 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
741 if (!AFI->isThumbFunction())
742 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
743 Offset, Pred, PredReg, TII);
745 assert(AFI->isThumb2Function());
746 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
747 Offset, Pred, PredReg, TII);
749 // Update the original instruction to use the scratch register.
750 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);