1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
50 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
58 llvm_unreachable("Unknown ARM register!");
59 case R0: case D0: case Q0: return 0;
60 case R1: case D1: case Q1: return 1;
61 case R2: case D2: case Q2: return 2;
62 case R3: case D3: case Q3: return 3;
63 case R4: case D4: case Q4: return 4;
64 case R5: case D5: case Q5: return 5;
65 case R6: case D6: case Q6: return 6;
66 case R7: case D7: case Q7: return 7;
67 case R8: case D8: case Q8: return 8;
68 case R9: case D9: case Q9: return 9;
69 case R10: case D10: case Q10: return 10;
70 case R11: case D11: case Q11: return 11;
71 case R12: case D12: case Q12: return 12;
72 case SP: case D13: case Q13: return 13;
73 case LR: case D14: case Q14: return 14;
74 case PC: case D15: case Q15: return 15;
93 case S0: case S1: case S2: case S3:
94 case S4: case S5: case S6: case S7:
95 case S8: case S9: case S10: case S11:
96 case S12: case S13: case S14: case S15:
97 case S16: case S17: case S18: case S19:
98 case S20: case S21: case S22: case S23:
99 case S24: case S25: case S26: case S27:
100 case S28: case S29: case S30: case S31: {
104 default: return 0; // Avoid compile time warning.
142 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143 const ARMSubtarget &sti)
144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 static const unsigned CalleeSavedRegs[] = {
152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
160 static const unsigned DarwinCalleeSavedRegs[] = {
161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
164 ARM::R11, ARM::R10, ARM::R8,
166 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
173 BitVector ARMBaseRegisterInfo::
174 getReservedRegs(const MachineFunction &MF) const {
175 // FIXME: avoid re-calculating this everytime.
176 BitVector Reserved(getNumRegs());
177 Reserved.set(ARM::SP);
178 Reserved.set(ARM::PC);
179 if (STI.isTargetDarwin() || hasFP(MF))
180 Reserved.set(FramePtr);
181 // Some targets reserve R9.
182 if (STI.isR9Reserved())
183 Reserved.set(ARM::R9);
187 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
188 unsigned Reg) const {
196 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
200 return STI.isR9Reserved();
206 const TargetRegisterClass *
207 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
208 const TargetRegisterClass *B,
209 unsigned SubIdx) const {
217 if (A->getSize() == 8) {
218 if (B == &ARM::SPR_8RegClass)
219 return &ARM::DPR_8RegClass;
220 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
221 if (A == &ARM::DPR_8RegClass)
223 return &ARM::DPR_VFP2RegClass;
226 if (A->getSize() == 16) {
227 if (B == &ARM::SPR_8RegClass)
228 return &ARM::QPR_8RegClass;
229 return &ARM::QPR_VFP2RegClass;
232 if (A->getSize() == 32) {
233 if (B == &ARM::SPR_8RegClass)
234 return 0; // Do not allow coalescing!
235 return &ARM::QQPR_VFP2RegClass;
238 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
239 return 0; // Do not allow coalescing!
246 if (A->getSize() == 16) {
247 if (B == &ARM::DPR_VFP2RegClass)
248 return &ARM::QPR_VFP2RegClass;
249 if (B == &ARM::DPR_8RegClass)
250 return 0; // Do not allow coalescing!
254 if (A->getSize() == 32) {
255 if (B == &ARM::DPR_VFP2RegClass)
256 return &ARM::QQPR_VFP2RegClass;
257 if (B == &ARM::DPR_8RegClass)
258 return 0; // Do not allow coalescing!
262 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
263 if (B != &ARM::DPRRegClass)
264 return 0; // Do not allow coalescing!
271 // D sub-registers of QQQQ registers.
272 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
274 return 0; // Do not allow coalescing!
280 if (A->getSize() == 32) {
281 if (B == &ARM::QPR_VFP2RegClass)
282 return &ARM::QQPR_VFP2RegClass;
283 if (B == &ARM::QPR_8RegClass)
284 return 0; // Do not allow coalescing!
288 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
289 if (B == &ARM::QPRRegClass)
291 return 0; // Do not allow coalescing!
295 // Q sub-registers of QQQQ registers.
296 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
298 return 0; // Do not allow coalescing!
305 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
306 SmallVectorImpl<unsigned> &SubIndices,
307 unsigned &NewSubIdx) const {
309 unsigned Size = RC->getSize() * 8;
313 NewSubIdx = 0; // Whole register.
314 unsigned NumRegs = SubIndices.size();
316 // 8 D registers -> 1 QQQQ register.
317 return (Size == 512 &&
318 SubIndices[0] == ARM::dsub_0 &&
319 SubIndices[1] == ARM::dsub_1 &&
320 SubIndices[2] == ARM::dsub_2 &&
321 SubIndices[3] == ARM::dsub_3 &&
322 SubIndices[4] == ARM::dsub_4 &&
323 SubIndices[5] == ARM::dsub_5 &&
324 SubIndices[6] == ARM::dsub_6 &&
325 SubIndices[7] == ARM::dsub_7);
326 } else if (NumRegs == 4) {
327 if (SubIndices[0] == ARM::qsub_0) {
328 // 4 Q registers -> 1 QQQQ register.
329 return (Size == 512 &&
330 SubIndices[1] == ARM::qsub_1 &&
331 SubIndices[2] == ARM::qsub_2 &&
332 SubIndices[3] == ARM::qsub_3);
333 } else if (SubIndices[0] == ARM::dsub_0) {
334 // 4 D registers -> 1 QQ register.
336 SubIndices[1] == ARM::dsub_1 &&
337 SubIndices[2] == ARM::dsub_2 &&
338 SubIndices[3] == ARM::dsub_3) {
340 NewSubIdx = ARM::qqsub_0;
343 } else if (SubIndices[0] == ARM::dsub_4) {
344 // 4 D registers -> 1 QQ register (2nd).
346 SubIndices[1] == ARM::dsub_5 &&
347 SubIndices[2] == ARM::dsub_6 &&
348 SubIndices[3] == ARM::dsub_7) {
349 NewSubIdx = ARM::qqsub_1;
352 } else if (SubIndices[0] == ARM::ssub_0) {
353 // 4 S registers -> 1 Q register.
355 SubIndices[1] == ARM::ssub_1 &&
356 SubIndices[2] == ARM::ssub_2 &&
357 SubIndices[3] == ARM::ssub_3) {
359 NewSubIdx = ARM::qsub_0;
363 } else if (NumRegs == 2) {
364 if (SubIndices[0] == ARM::qsub_0) {
365 // 2 Q registers -> 1 QQ register.
366 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
368 NewSubIdx = ARM::qqsub_0;
371 } else if (SubIndices[0] == ARM::qsub_2) {
372 // 2 Q registers -> 1 QQ register (2nd).
373 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
374 NewSubIdx = ARM::qqsub_1;
377 } else if (SubIndices[0] == ARM::dsub_0) {
378 // 2 D registers -> 1 Q register.
379 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
381 NewSubIdx = ARM::qsub_0;
384 } else if (SubIndices[0] == ARM::dsub_2) {
385 // 2 D registers -> 1 Q register (2nd).
386 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
387 NewSubIdx = ARM::qsub_1;
390 } else if (SubIndices[0] == ARM::dsub_4) {
391 // 2 D registers -> 1 Q register (3rd).
392 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
393 NewSubIdx = ARM::qsub_2;
396 } else if (SubIndices[0] == ARM::dsub_6) {
397 // 2 D registers -> 1 Q register (3rd).
398 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
399 NewSubIdx = ARM::qsub_3;
402 } else if (SubIndices[0] == ARM::ssub_0) {
403 // 2 S registers -> 1 D register.
404 if (SubIndices[1] == ARM::ssub_1) {
406 NewSubIdx = ARM::dsub_0;
409 } else if (SubIndices[0] == ARM::ssub_2) {
410 // 2 S registers -> 1 D register (2nd).
411 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
412 NewSubIdx = ARM::dsub_1;
421 const TargetRegisterClass *
422 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
423 return ARM::GPRRegisterClass;
426 /// getAllocationOrder - Returns the register allocation order for a specified
427 /// register class in the form of a pair of TargetRegisterClass iterators.
428 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
429 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
430 unsigned HintType, unsigned HintReg,
431 const MachineFunction &MF) const {
432 // Alternative register allocation orders when favoring even / odd registers
433 // of register pairs.
435 // No FP, R9 is available.
436 static const unsigned GPREven1[] = {
437 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
438 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
441 static const unsigned GPROdd1[] = {
442 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
443 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
447 // FP is R7, R9 is available.
448 static const unsigned GPREven2[] = {
449 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
450 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
453 static const unsigned GPROdd2[] = {
454 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
455 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
459 // FP is R11, R9 is available.
460 static const unsigned GPREven3[] = {
461 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
462 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
465 static const unsigned GPROdd3[] = {
466 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
467 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
471 // No FP, R9 is not available.
472 static const unsigned GPREven4[] = {
473 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
474 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
477 static const unsigned GPROdd4[] = {
478 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
479 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
483 // FP is R7, R9 is not available.
484 static const unsigned GPREven5[] = {
485 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
486 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
489 static const unsigned GPROdd5[] = {
490 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
491 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
495 // FP is R11, R9 is not available.
496 static const unsigned GPREven6[] = {
497 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
498 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
500 static const unsigned GPROdd6[] = {
501 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
502 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
506 if (HintType == ARMRI::RegPairEven) {
507 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
508 // It's no longer possible to fulfill this hint. Return the default
510 return std::make_pair(RC->allocation_order_begin(MF),
511 RC->allocation_order_end(MF));
513 if (!STI.isTargetDarwin() && !hasFP(MF)) {
514 if (!STI.isR9Reserved())
515 return std::make_pair(GPREven1,
516 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
518 return std::make_pair(GPREven4,
519 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
520 } else if (FramePtr == ARM::R7) {
521 if (!STI.isR9Reserved())
522 return std::make_pair(GPREven2,
523 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
525 return std::make_pair(GPREven5,
526 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
527 } else { // FramePtr == ARM::R11
528 if (!STI.isR9Reserved())
529 return std::make_pair(GPREven3,
530 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
532 return std::make_pair(GPREven6,
533 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
535 } else if (HintType == ARMRI::RegPairOdd) {
536 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
537 // It's no longer possible to fulfill this hint. Return the default
539 return std::make_pair(RC->allocation_order_begin(MF),
540 RC->allocation_order_end(MF));
542 if (!STI.isTargetDarwin() && !hasFP(MF)) {
543 if (!STI.isR9Reserved())
544 return std::make_pair(GPROdd1,
545 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
547 return std::make_pair(GPROdd4,
548 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
549 } else if (FramePtr == ARM::R7) {
550 if (!STI.isR9Reserved())
551 return std::make_pair(GPROdd2,
552 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
554 return std::make_pair(GPROdd5,
555 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
556 } else { // FramePtr == ARM::R11
557 if (!STI.isR9Reserved())
558 return std::make_pair(GPROdd3,
559 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
561 return std::make_pair(GPROdd6,
562 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
565 return std::make_pair(RC->allocation_order_begin(MF),
566 RC->allocation_order_end(MF));
569 /// ResolveRegAllocHint - Resolves the specified register allocation hint
570 /// to a physical register. Returns the physical register if it is successful.
572 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
573 const MachineFunction &MF) const {
574 if (Reg == 0 || !isPhysicalRegister(Reg))
578 else if (Type == (unsigned)ARMRI::RegPairOdd)
580 return getRegisterPairOdd(Reg, MF);
581 else if (Type == (unsigned)ARMRI::RegPairEven)
583 return getRegisterPairEven(Reg, MF);
588 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
589 MachineFunction &MF) const {
590 MachineRegisterInfo *MRI = &MF.getRegInfo();
591 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
592 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
593 Hint.first == (unsigned)ARMRI::RegPairEven) &&
594 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
595 // If 'Reg' is one of the even / odd register pair and it's now changed
596 // (e.g. coalesced) into a different register. The other register of the
597 // pair allocation hint must be updated to reflect the relationship
599 unsigned OtherReg = Hint.second;
600 Hint = MRI->getRegAllocationHint(OtherReg);
601 if (Hint.second == Reg)
602 // Make sure the pair has not already divorced.
603 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
607 /// hasFP - Return true if the specified function should have a dedicated frame
608 /// pointer register. This is true if the function has variable sized allocas
609 /// or if frame pointer elimination is disabled.
611 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
612 const MachineFrameInfo *MFI = MF.getFrameInfo();
613 return ((DisableFramePointerElim(MF) && MFI->adjustsStack())||
614 needsStackRealignment(MF) ||
615 MFI->hasVarSizedObjects() ||
616 MFI->isFrameAddressTaken());
619 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
620 const MachineFrameInfo *MFI = MF.getFrameInfo();
621 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
622 return (RealignStack &&
623 !AFI->isThumb1OnlyFunction() &&
624 !MFI->hasVarSizedObjects());
627 bool ARMBaseRegisterInfo::
628 needsStackRealignment(const MachineFunction &MF) const {
629 const MachineFrameInfo *MFI = MF.getFrameInfo();
630 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
631 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
632 return (RealignStack &&
633 !AFI->isThumb1OnlyFunction() &&
634 (MFI->getMaxAlignment() > StackAlign) &&
635 !MFI->hasVarSizedObjects());
638 bool ARMBaseRegisterInfo::
639 cannotEliminateFrame(const MachineFunction &MF) const {
640 const MachineFrameInfo *MFI = MF.getFrameInfo();
641 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
643 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
644 || needsStackRealignment(MF);
647 /// estimateStackSize - Estimate and return the size of the frame.
648 static unsigned estimateStackSize(MachineFunction &MF) {
649 const MachineFrameInfo *FFI = MF.getFrameInfo();
651 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
652 int FixedOff = -FFI->getObjectOffset(i);
653 if (FixedOff > Offset) Offset = FixedOff;
655 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
656 if (FFI->isDeadObjectIndex(i))
658 Offset += FFI->getObjectSize(i);
659 unsigned Align = FFI->getObjectAlignment(i);
660 // Adjust to alignment boundary
661 Offset = (Offset+Align-1)/Align*Align;
663 return (unsigned)Offset;
666 /// estimateRSStackSizeLimit - Look at each instruction that references stack
667 /// frames and return the stack size limit beyond which some of these
668 /// instructions will require a scratch register during their expansion later.
670 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
671 unsigned Limit = (1 << 12) - 1;
672 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
673 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
675 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
676 if (!I->getOperand(i).isFI()) continue;
678 // When using ADDri to get the address of a stack object, 255 is the
679 // largest offset guaranteed to fit in the immediate offset.
680 if (I->getOpcode() == ARM::ADDri) {
681 Limit = std::min(Limit, (1U << 8) - 1);
685 // Otherwise check the addressing mode.
686 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
687 case ARMII::AddrMode3:
688 case ARMII::AddrModeT2_i8:
689 Limit = std::min(Limit, (1U << 8) - 1);
691 case ARMII::AddrMode5:
692 case ARMII::AddrModeT2_i8s4:
693 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
695 case ARMII::AddrModeT2_i12:
696 if (hasFP(MF)) Limit = std::min(Limit, (1U << 8) - 1);
698 case ARMII::AddrMode6:
699 // Addressing mode 6 (load/store) instructions can't encode an
700 // immediate offset for stack references.
705 break; // At most one FI per instruction
714 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
715 RegScavenger *RS) const {
716 // This tells PEI to spill the FP as if it is any other callee-save register
717 // to take advantage the eliminateFrameIndex machinery. This also ensures it
718 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
719 // to combine multiple loads / stores.
720 bool CanEliminateFrame = true;
721 bool CS1Spilled = false;
722 bool LRSpilled = false;
723 unsigned NumGPRSpills = 0;
724 SmallVector<unsigned, 4> UnspilledCS1GPRs;
725 SmallVector<unsigned, 4> UnspilledCS2GPRs;
726 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
728 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
730 // FIXME: It will be better just to find spare register here.
731 if (needsStackRealignment(MF) &&
732 AFI->isThumb2Function())
733 MF.getRegInfo().setPhysRegUsed(ARM::R4);
735 // Spill LR if Thumb1 function uses variable length argument lists.
736 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
737 MF.getRegInfo().setPhysRegUsed(ARM::LR);
739 // Don't spill FP if the frame can be eliminated. This is determined
740 // by scanning the callee-save registers to see if any is used.
741 const unsigned *CSRegs = getCalleeSavedRegs();
742 for (unsigned i = 0; CSRegs[i]; ++i) {
743 unsigned Reg = CSRegs[i];
744 bool Spilled = false;
745 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
746 AFI->setCSRegisterIsSpilled(Reg);
748 CanEliminateFrame = false;
750 // Check alias registers too.
751 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
752 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
754 CanEliminateFrame = false;
759 if (!ARM::GPRRegisterClass->contains(Reg))
765 if (!STI.isTargetDarwin()) {
772 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
787 if (!STI.isTargetDarwin()) {
788 UnspilledCS1GPRs.push_back(Reg);
798 UnspilledCS1GPRs.push_back(Reg);
801 UnspilledCS2GPRs.push_back(Reg);
807 bool ForceLRSpill = false;
808 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
809 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
810 // Force LR to be spilled if the Thumb function size is > 2048. This enables
811 // use of BL to implement far jump. If it turns out that it's not needed
812 // then the branch fix up path will undo it.
813 if (FnSize >= (1 << 11)) {
814 CanEliminateFrame = false;
819 // If any of the stack slot references may be out of range of an immediate
820 // offset, make sure a register (or a spill slot) is available for the
821 // register scavenger. Note that if we're indexing off the frame pointer, the
822 // effective stack size is 4 bytes larger since the FP points to the stack
823 // slot of the previous FP.
824 bool BigStack = RS &&
825 estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
827 bool ExtraCSSpill = false;
828 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
829 AFI->setHasStackFrame(true);
831 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
832 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
833 if (!LRSpilled && CS1Spilled) {
834 MF.getRegInfo().setPhysRegUsed(ARM::LR);
835 AFI->setCSRegisterIsSpilled(ARM::LR);
837 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
838 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
839 ForceLRSpill = false;
843 // Darwin ABI requires FP to point to the stack slot that contains the
845 if (STI.isTargetDarwin() || hasFP(MF)) {
846 MF.getRegInfo().setPhysRegUsed(FramePtr);
850 // If stack and double are 8-byte aligned and we are spilling an odd number
851 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
852 // the integer and double callee save areas.
853 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
854 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
855 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
856 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
857 unsigned Reg = UnspilledCS1GPRs[i];
858 // Don't spill high register if the function is thumb1
859 if (!AFI->isThumb1OnlyFunction() ||
860 isARMLowRegister(Reg) || Reg == ARM::LR) {
861 MF.getRegInfo().setPhysRegUsed(Reg);
862 AFI->setCSRegisterIsSpilled(Reg);
863 if (!isReservedReg(MF, Reg))
868 } else if (!UnspilledCS2GPRs.empty() &&
869 !AFI->isThumb1OnlyFunction()) {
870 unsigned Reg = UnspilledCS2GPRs.front();
871 MF.getRegInfo().setPhysRegUsed(Reg);
872 AFI->setCSRegisterIsSpilled(Reg);
873 if (!isReservedReg(MF, Reg))
878 // Estimate if we might need to scavenge a register at some point in order
879 // to materialize a stack offset. If so, either spill one additional
880 // callee-saved register or reserve a special spill slot to facilitate
881 // register scavenging. Thumb1 needs a spill slot for stack pointer
882 // adjustments also, even when the frame itself is small.
883 if (BigStack && !ExtraCSSpill) {
884 // If any non-reserved CS register isn't spilled, just spill one or two
885 // extra. That should take care of it!
886 unsigned NumExtras = TargetAlign / 4;
887 SmallVector<unsigned, 2> Extras;
888 while (NumExtras && !UnspilledCS1GPRs.empty()) {
889 unsigned Reg = UnspilledCS1GPRs.back();
890 UnspilledCS1GPRs.pop_back();
891 if (!isReservedReg(MF, Reg) &&
892 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
894 Extras.push_back(Reg);
898 // For non-Thumb1 functions, also check for hi-reg CS registers
899 if (!AFI->isThumb1OnlyFunction()) {
900 while (NumExtras && !UnspilledCS2GPRs.empty()) {
901 unsigned Reg = UnspilledCS2GPRs.back();
902 UnspilledCS2GPRs.pop_back();
903 if (!isReservedReg(MF, Reg)) {
904 Extras.push_back(Reg);
909 if (Extras.size() && NumExtras == 0) {
910 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
911 MF.getRegInfo().setPhysRegUsed(Extras[i]);
912 AFI->setCSRegisterIsSpilled(Extras[i]);
914 } else if (!AFI->isThumb1OnlyFunction()) {
915 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
916 // closest to SP or frame pointer.
917 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
918 MachineFrameInfo *MFI = MF.getFrameInfo();
919 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
927 MF.getRegInfo().setPhysRegUsed(ARM::LR);
928 AFI->setCSRegisterIsSpilled(ARM::LR);
929 AFI->setLRIsSpilledForFarJump(true);
933 unsigned ARMBaseRegisterInfo::getRARegister() const {
938 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
939 if (STI.isTargetDarwin() || hasFP(MF))
945 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
946 unsigned &FrameReg) const {
947 const MachineFrameInfo *MFI = MF.getFrameInfo();
948 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
949 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
950 bool isFixed = MFI->isFixedObjectIndex(FI);
953 if (AFI->isGPRCalleeSavedArea1Frame(FI))
954 Offset -= AFI->getGPRCalleeSavedArea1Offset();
955 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
956 Offset -= AFI->getGPRCalleeSavedArea2Offset();
957 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
958 Offset -= AFI->getDPRCalleeSavedAreaOffset();
959 else if (needsStackRealignment(MF)) {
960 // When dynamically realigning the stack, use the frame pointer for
961 // parameters, and the stack pointer for locals.
962 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
964 FrameReg = getFrameRegister(MF);
965 Offset -= AFI->getFramePtrSpillOffset();
967 } else if (hasFP(MF) && AFI->hasStackFrame()) {
968 if (isFixed || MFI->hasVarSizedObjects()) {
969 // Use frame pointer to reference fixed objects unless this is a
970 // frameless function.
971 FrameReg = getFrameRegister(MF);
972 Offset -= AFI->getFramePtrSpillOffset();
973 } else if (AFI->isThumb2Function()) {
974 // In Thumb2 mode, the negative offset is very limited.
975 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
976 if (FPOffset >= -255 && FPOffset < 0) {
977 FrameReg = getFrameRegister(MF);
987 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
990 return getFrameIndexReference(MF, FI, FrameReg);
993 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
994 llvm_unreachable("What is the exception register");
998 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
999 llvm_unreachable("What is the exception handler register");
1003 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1004 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1007 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1008 const MachineFunction &MF) const {
1011 // Return 0 if either register of the pair is a special register.
1020 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
1022 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1024 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1096 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1097 const MachineFunction &MF) const {
1100 // Return 0 if either register of the pair is a special register.
1109 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1111 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1113 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1185 /// emitLoadConstPool - Emits a load from constpool to materialize the
1186 /// specified immediate.
1187 void ARMBaseRegisterInfo::
1188 emitLoadConstPool(MachineBasicBlock &MBB,
1189 MachineBasicBlock::iterator &MBBI,
1191 unsigned DestReg, unsigned SubIdx, int Val,
1192 ARMCC::CondCodes Pred,
1193 unsigned PredReg) const {
1194 MachineFunction &MF = *MBB.getParent();
1195 MachineConstantPool *ConstantPool = MF.getConstantPool();
1197 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1198 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1200 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1201 .addReg(DestReg, getDefRegState(true), SubIdx)
1202 .addConstantPoolIndex(Idx)
1203 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1206 bool ARMBaseRegisterInfo::
1207 requiresRegisterScavenging(const MachineFunction &MF) const {
1211 bool ARMBaseRegisterInfo::
1212 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1216 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1217 // not required, we reserve argument space for call sites in the function
1218 // immediately on entry to the current function. This eliminates the need for
1219 // add/sub sp brackets around call sites. Returns true if the call frame is
1220 // included as part of the stack frame.
1221 bool ARMBaseRegisterInfo::
1222 hasReservedCallFrame(MachineFunction &MF) const {
1223 const MachineFrameInfo *FFI = MF.getFrameInfo();
1224 unsigned CFSize = FFI->getMaxCallFrameSize();
1225 // It's not always a good idea to include the call frame as part of the
1226 // stack frame. ARM (especially Thumb) has small immediate offset to
1227 // address the stack frame. So a large call frame can cause poor codegen
1228 // and may even makes it impossible to scavenge a register.
1229 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1232 return !MF.getFrameInfo()->hasVarSizedObjects();
1235 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1236 // call frame pseudos can be simplified. Unlike most targets, having a FP
1237 // is not sufficient here since we still may reference some objects via SP
1238 // even when FP is available in Thumb2 mode.
1239 bool ARMBaseRegisterInfo::
1240 canSimplifyCallFramePseudos(MachineFunction &MF) const {
1241 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1245 emitSPUpdate(bool isARM,
1246 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1247 DebugLoc dl, const ARMBaseInstrInfo &TII,
1249 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1251 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1252 Pred, PredReg, TII);
1254 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1255 Pred, PredReg, TII);
1259 void ARMBaseRegisterInfo::
1260 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1261 MachineBasicBlock::iterator I) const {
1262 if (!hasReservedCallFrame(MF)) {
1263 // If we have alloca, convert as follows:
1264 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1265 // ADJCALLSTACKUP -> add, sp, sp, amount
1266 MachineInstr *Old = I;
1267 DebugLoc dl = Old->getDebugLoc();
1268 unsigned Amount = Old->getOperand(0).getImm();
1270 // We need to keep the stack aligned properly. To do this, we round the
1271 // amount of space needed for the outgoing arguments up to the next
1272 // alignment boundary.
1273 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1274 Amount = (Amount+Align-1)/Align*Align;
1276 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1277 assert(!AFI->isThumb1OnlyFunction() &&
1278 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1279 bool isARM = !AFI->isThumbFunction();
1281 // Replace the pseudo instruction with a new instruction...
1282 unsigned Opc = Old->getOpcode();
1283 int PIdx = Old->findFirstPredOperandIdx();
1284 ARMCC::CondCodes Pred = (PIdx == -1)
1285 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1286 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1287 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1288 unsigned PredReg = Old->getOperand(2).getReg();
1289 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1291 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1292 unsigned PredReg = Old->getOperand(3).getReg();
1293 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1294 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1302 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1303 int SPAdj, FrameIndexValue *Value,
1304 RegScavenger *RS) const {
1306 MachineInstr &MI = *II;
1307 MachineBasicBlock &MBB = *MI.getParent();
1308 MachineFunction &MF = *MBB.getParent();
1309 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1310 assert(!AFI->isThumb1OnlyFunction() &&
1311 "This eliminateFrameIndex does not support Thumb1!");
1313 while (!MI.getOperand(i).isFI()) {
1315 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1318 int FrameIndex = MI.getOperand(i).getIndex();
1321 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1322 if (FrameReg != ARM::SP)
1326 // Special handling of dbg_value instructions.
1327 if (MI.isDebugValue()) {
1328 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1329 MI.getOperand(i+1).ChangeToImmediate(Offset);
1333 // Modify MI as necessary to handle as much of 'Offset' as possible
1335 if (!AFI->isThumbFunction())
1336 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1338 assert(AFI->isThumb2Function());
1339 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1344 // If we get here, the immediate doesn't fit into the instruction. We folded
1345 // as much as possible above, handle the rest, providing a register that is
1348 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1349 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1350 "This code isn't needed if offset already handled!");
1352 unsigned ScratchReg = 0;
1353 int PIdx = MI.findFirstPredOperandIdx();
1354 ARMCC::CondCodes Pred = (PIdx == -1)
1355 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1356 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1358 // Must be addrmode4/6.
1359 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1361 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1363 Value->first = FrameReg; // use the frame register as a kind indicator
1364 Value->second = Offset;
1366 if (!AFI->isThumbFunction())
1367 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1368 Offset, Pred, PredReg, TII);
1370 assert(AFI->isThumb2Function());
1371 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1372 Offset, Pred, PredReg, TII);
1374 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1375 if (!ReuseFrameIndexVals)
1381 /// Move iterator past the next bunch of callee save load / store ops for
1382 /// the particular spill area (1: integer area 1, 2: integer area 2,
1383 /// 3: fp area, 0: don't care).
1384 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1385 MachineBasicBlock::iterator &MBBI,
1386 int Opc1, int Opc2, unsigned Area,
1387 const ARMSubtarget &STI) {
1388 while (MBBI != MBB.end() &&
1389 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1390 MBBI->getOperand(1).isFI()) {
1393 unsigned Category = 0;
1394 switch (MBBI->getOperand(0).getReg()) {
1395 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1399 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1400 Category = STI.isTargetDarwin() ? 2 : 1;
1402 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1403 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1410 if (Done || Category != Area)
1418 void ARMBaseRegisterInfo::
1419 emitPrologue(MachineFunction &MF) const {
1420 MachineBasicBlock &MBB = MF.front();
1421 MachineBasicBlock::iterator MBBI = MBB.begin();
1422 MachineFrameInfo *MFI = MF.getFrameInfo();
1423 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1424 assert(!AFI->isThumb1OnlyFunction() &&
1425 "This emitPrologue does not support Thumb1!");
1426 bool isARM = !AFI->isThumbFunction();
1427 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1428 unsigned NumBytes = MFI->getStackSize();
1429 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1430 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1432 // Determine the sizes of each callee-save spill areas and record which frame
1433 // belongs to which callee-save spill areas.
1434 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1435 int FramePtrSpillFI = 0;
1437 // Allocate the vararg register save area. This is not counted in NumBytes.
1439 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1441 if (!AFI->hasStackFrame()) {
1443 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1447 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1448 unsigned Reg = CSI[i].getReg();
1449 int FI = CSI[i].getFrameIdx();
1456 if (Reg == FramePtr)
1457 FramePtrSpillFI = FI;
1458 AFI->addGPRCalleeSavedArea1Frame(FI);
1465 if (Reg == FramePtr)
1466 FramePtrSpillFI = FI;
1467 if (STI.isTargetDarwin()) {
1468 AFI->addGPRCalleeSavedArea2Frame(FI);
1471 AFI->addGPRCalleeSavedArea1Frame(FI);
1476 AFI->addDPRCalleeSavedAreaFrame(FI);
1481 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1482 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1483 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1485 // Set FP to point to the stack slot that contains the previous FP.
1486 // For Darwin, FP is R7, which has now been stored in spill area 1.
1487 // Otherwise, if this is not Darwin, all the callee-saved registers go
1488 // into spill area 1, including the FP in R11. In either case, it is
1489 // now safe to emit this assignment.
1490 if (STI.isTargetDarwin() || hasFP(MF)) {
1491 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1492 MachineInstrBuilder MIB =
1493 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1494 .addFrameIndex(FramePtrSpillFI).addImm(0);
1495 AddDefaultCC(AddDefaultPred(MIB));
1498 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1499 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1501 // Build the new SUBri to adjust SP for FP callee-save spill area.
1502 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1503 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1505 // Determine starting offsets of spill areas.
1506 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1507 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1508 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1509 if (STI.isTargetDarwin() || hasFP(MF))
1510 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1512 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1513 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1514 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1516 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1517 NumBytes = DPRCSOffset;
1519 // Adjust SP after all the callee-save spills.
1520 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1523 if (STI.isTargetELF() && hasFP(MF)) {
1524 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1525 AFI->getFramePtrSpillOffset());
1528 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1529 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1530 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1532 // If we need dynamic stack realignment, do it here.
1533 if (needsStackRealignment(MF)) {
1534 unsigned MaxAlign = MFI->getMaxAlignment();
1535 assert (!AFI->isThumb1OnlyFunction());
1536 if (!AFI->isThumbFunction()) {
1537 // Emit bic sp, sp, MaxAlign
1538 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1539 TII.get(ARM::BICri), ARM::SP)
1540 .addReg(ARM::SP, RegState::Kill)
1541 .addImm(MaxAlign-1)));
1543 // We cannot use sp as source/dest register here, thus we're emitting the
1544 // following sequence:
1546 // bic r4, r4, MaxAlign
1548 // FIXME: It will be better just to find spare register here.
1549 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1550 .addReg(ARM::SP, RegState::Kill);
1551 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1552 TII.get(ARM::t2BICri), ARM::R4)
1553 .addReg(ARM::R4, RegState::Kill)
1554 .addImm(MaxAlign-1)));
1555 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1556 .addReg(ARM::R4, RegState::Kill);
1561 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1562 for (unsigned i = 0; CSRegs[i]; ++i)
1563 if (Reg == CSRegs[i])
1568 static bool isCSRestore(MachineInstr *MI,
1569 const ARMBaseInstrInfo &TII,
1570 const unsigned *CSRegs) {
1571 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1572 MI->getOpcode() == (int)ARM::LDR ||
1573 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1574 MI->getOperand(1).isFI() &&
1575 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1578 void ARMBaseRegisterInfo::
1579 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1580 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1581 assert(MBBI->getDesc().isReturn() &&
1582 "Can only insert epilog into returning blocks");
1583 unsigned RetOpcode = MBBI->getOpcode();
1584 DebugLoc dl = MBBI->getDebugLoc();
1585 MachineFrameInfo *MFI = MF.getFrameInfo();
1586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1587 assert(!AFI->isThumb1OnlyFunction() &&
1588 "This emitEpilogue does not support Thumb1!");
1589 bool isARM = !AFI->isThumbFunction();
1591 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1592 int NumBytes = (int)MFI->getStackSize();
1594 if (!AFI->hasStackFrame()) {
1596 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1598 // Unwind MBBI to point to first LDR / VLDRD.
1599 const unsigned *CSRegs = getCalleeSavedRegs();
1600 if (MBBI != MBB.begin()) {
1603 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1604 if (!isCSRestore(MBBI, TII, CSRegs))
1608 // Move SP to start of FP callee save spill area.
1609 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1610 AFI->getGPRCalleeSavedArea2Size() +
1611 AFI->getDPRCalleeSavedAreaSize());
1613 // Darwin ABI requires FP to point to the stack slot that contains the
1615 bool HasFP = hasFP(MF);
1616 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1617 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1618 // Reset SP based on frame pointer only if the stack frame extends beyond
1619 // frame pointer stack slot or target is ELF and the function has FP.
1621 AFI->getGPRCalleeSavedArea2Size() ||
1622 AFI->getDPRCalleeSavedAreaSize() ||
1623 AFI->getDPRCalleeSavedAreaOffset()) {
1626 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1629 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1634 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1636 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1638 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1642 } else if (NumBytes)
1643 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1645 // Move SP to start of integer callee save spill area 2.
1646 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1647 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1649 // Move SP to start of integer callee save spill area 1.
1650 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1651 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1653 // Move SP to SP upon entry to the function.
1654 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1655 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1658 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1659 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1660 // Tail call return: adjust the stack pointer and jump to callee.
1661 MBBI = prior(MBB.end());
1662 MachineOperand &JumpTarget = MBBI->getOperand(0);
1664 // Jump to label or value in register.
1665 if (RetOpcode == ARM::TCRETURNdi) {
1666 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPd)).
1667 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1668 JumpTarget.getTargetFlags());
1669 } else if (RetOpcode == ARM::TCRETURNdiND) {
1670 BuildMI(MBB, MBBI, dl,
1671 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1672 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1673 JumpTarget.getTargetFlags());
1674 } else if (RetOpcode == ARM::TCRETURNri) {
1675 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1676 addReg(JumpTarget.getReg(), RegState::Kill);
1677 } else if (RetOpcode == ARM::TCRETURNriND) {
1678 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1679 addReg(JumpTarget.getReg(), RegState::Kill);
1682 MachineInstr *NewMI = prior(MBBI);
1683 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1684 NewMI->addOperand(MBBI->getOperand(i));
1686 // Delete the pseudo instruction TCRETURN.
1691 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1694 #include "ARMGenRegisterInfo.inc"