1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "ARMGenRegisterInfo.inc"
48 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49 cl::desc("Force use of virtual base registers for stack load/store"));
51 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58 const ARMSubtarget &sti)
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66 return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
70 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71 return (STI.isTargetIOS()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
74 BitVector ARMBaseRegisterInfo::
75 getReservedRegs(const MachineFunction &MF) const {
76 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
78 // FIXME: avoid re-calculating this every time.
79 BitVector Reserved(getNumRegs());
80 Reserved.set(ARM::SP);
81 Reserved.set(ARM::PC);
83 Reserved.set(FramePtr);
84 if (hasBasePointer(MF))
85 Reserved.set(BasePtr);
86 // Some targets reserve R9.
87 if (STI.isR9Reserved())
88 Reserved.set(ARM::R9);
89 // Reserve D16-D31 if the subtarget doesn't support them.
90 if (!STI.hasVFP3() || STI.hasD16()) {
91 assert(ARM::D31 == ARM::D16 + 15);
92 for (unsigned i = 0; i != 16; ++i)
93 Reserved.set(ARM::D16 + i);
98 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
100 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
108 if (hasBasePointer(MF))
113 if (FramePtr == Reg && TFI->hasFP(MF))
117 return STI.isR9Reserved();
124 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
125 SmallVectorImpl<unsigned> &SubIndices,
126 unsigned &NewSubIdx) const {
128 unsigned Size = RC->getSize() * 8;
132 NewSubIdx = 0; // Whole register.
133 unsigned NumRegs = SubIndices.size();
135 // 8 D registers -> 1 QQQQ register.
136 return (Size == 512 &&
137 SubIndices[0] == ARM::dsub_0 &&
138 SubIndices[1] == ARM::dsub_1 &&
139 SubIndices[2] == ARM::dsub_2 &&
140 SubIndices[3] == ARM::dsub_3 &&
141 SubIndices[4] == ARM::dsub_4 &&
142 SubIndices[5] == ARM::dsub_5 &&
143 SubIndices[6] == ARM::dsub_6 &&
144 SubIndices[7] == ARM::dsub_7);
145 } else if (NumRegs == 4) {
146 if (SubIndices[0] == ARM::qsub_0) {
147 // 4 Q registers -> 1 QQQQ register.
148 return (Size == 512 &&
149 SubIndices[1] == ARM::qsub_1 &&
150 SubIndices[2] == ARM::qsub_2 &&
151 SubIndices[3] == ARM::qsub_3);
152 } else if (SubIndices[0] == ARM::dsub_0) {
153 // 4 D registers -> 1 QQ register.
155 SubIndices[1] == ARM::dsub_1 &&
156 SubIndices[2] == ARM::dsub_2 &&
157 SubIndices[3] == ARM::dsub_3) {
159 NewSubIdx = ARM::qqsub_0;
162 } else if (SubIndices[0] == ARM::dsub_4) {
163 // 4 D registers -> 1 QQ register (2nd).
165 SubIndices[1] == ARM::dsub_5 &&
166 SubIndices[2] == ARM::dsub_6 &&
167 SubIndices[3] == ARM::dsub_7) {
168 NewSubIdx = ARM::qqsub_1;
171 } else if (SubIndices[0] == ARM::ssub_0) {
172 // 4 S registers -> 1 Q register.
174 SubIndices[1] == ARM::ssub_1 &&
175 SubIndices[2] == ARM::ssub_2 &&
176 SubIndices[3] == ARM::ssub_3) {
178 NewSubIdx = ARM::qsub_0;
182 } else if (NumRegs == 2) {
183 if (SubIndices[0] == ARM::qsub_0) {
184 // 2 Q registers -> 1 QQ register.
185 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
187 NewSubIdx = ARM::qqsub_0;
190 } else if (SubIndices[0] == ARM::qsub_2) {
191 // 2 Q registers -> 1 QQ register (2nd).
192 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
193 NewSubIdx = ARM::qqsub_1;
196 } else if (SubIndices[0] == ARM::dsub_0) {
197 // 2 D registers -> 1 Q register.
198 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
200 NewSubIdx = ARM::qsub_0;
203 } else if (SubIndices[0] == ARM::dsub_2) {
204 // 2 D registers -> 1 Q register (2nd).
205 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
206 NewSubIdx = ARM::qsub_1;
209 } else if (SubIndices[0] == ARM::dsub_4) {
210 // 2 D registers -> 1 Q register (3rd).
211 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
212 NewSubIdx = ARM::qsub_2;
215 } else if (SubIndices[0] == ARM::dsub_6) {
216 // 2 D registers -> 1 Q register (3rd).
217 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
218 NewSubIdx = ARM::qsub_3;
221 } else if (SubIndices[0] == ARM::ssub_0) {
222 // 2 S registers -> 1 D register.
223 if (SubIndices[1] == ARM::ssub_1) {
225 NewSubIdx = ARM::dsub_0;
228 } else if (SubIndices[0] == ARM::ssub_2) {
229 // 2 S registers -> 1 D register (2nd).
230 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
231 NewSubIdx = ARM::dsub_1;
239 const TargetRegisterClass*
240 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
242 const TargetRegisterClass *Super = RC;
243 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
245 switch (Super->getID()) {
246 case ARM::GPRRegClassID:
247 case ARM::SPRRegClassID:
248 case ARM::DPRRegClassID:
249 case ARM::QPRRegClassID:
250 case ARM::QQPRRegClassID:
251 case ARM::QQQQPRRegClassID:
259 const TargetRegisterClass *
260 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
261 return ARM::GPRRegisterClass;
264 const TargetRegisterClass *
265 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
266 if (RC == &ARM::CCRRegClass)
267 return 0; // Can't copy CCR registers.
272 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
273 MachineFunction &MF) const {
274 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
276 switch (RC->getID()) {
279 case ARM::tGPRRegClassID:
280 return TFI->hasFP(MF) ? 4 : 5;
281 case ARM::GPRRegClassID: {
282 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
283 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
285 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
286 case ARM::DPRRegClassID:
291 /// getRawAllocationOrder - Returns the register allocation order for a
292 /// specified register class with a target-dependent hint.
294 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
295 unsigned HintType, unsigned HintReg,
296 const MachineFunction &MF) const {
297 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
298 // Alternative register allocation orders when favoring even / odd registers
299 // of register pairs.
301 // No FP, R9 is available.
302 static const unsigned GPREven1[] = {
303 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
304 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
307 static const unsigned GPROdd1[] = {
308 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
309 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
313 // FP is R7, R9 is available.
314 static const unsigned GPREven2[] = {
315 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
316 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
319 static const unsigned GPROdd2[] = {
320 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
321 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
325 // FP is R11, R9 is available.
326 static const unsigned GPREven3[] = {
327 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
328 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
331 static const unsigned GPROdd3[] = {
332 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
333 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
337 // No FP, R9 is not available.
338 static const unsigned GPREven4[] = {
339 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
340 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
343 static const unsigned GPROdd4[] = {
344 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
345 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
349 // FP is R7, R9 is not available.
350 static const unsigned GPREven5[] = {
351 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
352 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
355 static const unsigned GPROdd5[] = {
356 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
357 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
361 // FP is R11, R9 is not available.
362 static const unsigned GPREven6[] = {
363 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
364 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
366 static const unsigned GPROdd6[] = {
367 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
368 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
371 // We only support even/odd hints for GPR and rGPR.
372 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
373 return RC->getRawAllocationOrder(MF);
375 if (HintType == ARMRI::RegPairEven) {
376 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
377 // It's no longer possible to fulfill this hint. Return the default
379 return RC->getRawAllocationOrder(MF);
381 if (!TFI->hasFP(MF)) {
382 if (!STI.isR9Reserved())
383 return makeArrayRef(GPREven1);
385 return makeArrayRef(GPREven4);
386 } else if (FramePtr == ARM::R7) {
387 if (!STI.isR9Reserved())
388 return makeArrayRef(GPREven2);
390 return makeArrayRef(GPREven5);
391 } else { // FramePtr == ARM::R11
392 if (!STI.isR9Reserved())
393 return makeArrayRef(GPREven3);
395 return makeArrayRef(GPREven6);
397 } else if (HintType == ARMRI::RegPairOdd) {
398 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
399 // It's no longer possible to fulfill this hint. Return the default
401 return RC->getRawAllocationOrder(MF);
403 if (!TFI->hasFP(MF)) {
404 if (!STI.isR9Reserved())
405 return makeArrayRef(GPROdd1);
407 return makeArrayRef(GPROdd4);
408 } else if (FramePtr == ARM::R7) {
409 if (!STI.isR9Reserved())
410 return makeArrayRef(GPROdd2);
412 return makeArrayRef(GPROdd5);
413 } else { // FramePtr == ARM::R11
414 if (!STI.isR9Reserved())
415 return makeArrayRef(GPROdd3);
417 return makeArrayRef(GPROdd6);
420 return RC->getRawAllocationOrder(MF);
423 /// ResolveRegAllocHint - Resolves the specified register allocation hint
424 /// to a physical register. Returns the physical register if it is successful.
426 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
427 const MachineFunction &MF) const {
428 if (Reg == 0 || !isPhysicalRegister(Reg))
432 else if (Type == (unsigned)ARMRI::RegPairOdd)
434 return getRegisterPairOdd(Reg, MF);
435 else if (Type == (unsigned)ARMRI::RegPairEven)
437 return getRegisterPairEven(Reg, MF);
442 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
443 MachineFunction &MF) const {
444 MachineRegisterInfo *MRI = &MF.getRegInfo();
445 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
446 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
447 Hint.first == (unsigned)ARMRI::RegPairEven) &&
448 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
449 // If 'Reg' is one of the even / odd register pair and it's now changed
450 // (e.g. coalesced) into a different register. The other register of the
451 // pair allocation hint must be updated to reflect the relationship
453 unsigned OtherReg = Hint.second;
454 Hint = MRI->getRegAllocationHint(OtherReg);
455 if (Hint.second == Reg)
456 // Make sure the pair has not already divorced.
457 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
462 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
463 // CortexA9 has a Write-after-write hazard for NEON registers.
464 if (!STI.isCortexA9())
467 switch (RC->getID()) {
468 case ARM::DPRRegClassID:
469 case ARM::DPR_8RegClassID:
470 case ARM::DPR_VFP2RegClassID:
471 case ARM::QPRRegClassID:
472 case ARM::QPR_8RegClassID:
473 case ARM::QPR_VFP2RegClassID:
474 case ARM::SPRRegClassID:
475 case ARM::SPR_8RegClassID:
476 // Avoid reusing S, D, and Q registers.
477 // Don't increase register pressure for QQ and QQQQ.
484 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
485 const MachineFrameInfo *MFI = MF.getFrameInfo();
486 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
488 if (!EnableBasePointer)
491 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
494 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
495 // negative range for ldr/str (255), and thumb1 is positive offsets only.
496 // It's going to be better to use the SP or Base Pointer instead. When there
497 // are variable sized objects, we can't reference off of the SP, so we
498 // reserve a Base Pointer.
499 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
500 // Conservatively estimate whether the negative offset from the frame
501 // pointer will be sufficient to reach. If a function has a smallish
502 // frame, it's less likely to have lots of spills and callee saved
503 // space, so it's all more likely to be within range of the frame pointer.
504 // If it's wrong, the scavenger will still enable access to work, it just
506 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
514 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
515 const MachineFrameInfo *MFI = MF.getFrameInfo();
516 const MachineRegisterInfo *MRI = &MF.getRegInfo();
517 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
518 // We can't realign the stack if:
519 // 1. Dynamic stack realignment is explicitly disabled,
520 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
521 // 3. There are VLAs in the function and the base pointer is disabled.
522 if (!MF.getTarget().Options.RealignStack)
524 if (AFI->isThumb1OnlyFunction())
526 // Stack realignment requires a frame pointer. If we already started
527 // register allocation with frame pointer elimination, it is too late now.
528 if (!MRI->canReserveReg(FramePtr))
530 // We may also need a base pointer if there are dynamic allocas.
531 if (!MFI->hasVarSizedObjects())
533 if (!EnableBasePointer)
535 // A base pointer is required and allowed. Check that it isn't too late to
537 return MRI->canReserveReg(BasePtr);
540 bool ARMBaseRegisterInfo::
541 needsStackRealignment(const MachineFunction &MF) const {
542 const MachineFrameInfo *MFI = MF.getFrameInfo();
543 const Function *F = MF.getFunction();
544 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
545 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
546 F->hasFnAttr(Attribute::StackAlignment));
548 return requiresRealignment && canRealignStack(MF);
551 bool ARMBaseRegisterInfo::
552 cannotEliminateFrame(const MachineFunction &MF) const {
553 const MachineFrameInfo *MFI = MF.getFrameInfo();
554 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
556 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
557 || needsStackRealignment(MF);
561 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
562 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
569 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
570 llvm_unreachable("What is the exception register");
573 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
574 llvm_unreachable("What is the exception handler register");
577 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
578 const MachineFunction &MF) const {
581 // Return 0 if either register of the pair is a special register.
583 case ARM::R1: return ARM::R0;
584 case ARM::R3: return ARM::R2;
585 case ARM::R5: return ARM::R4;
587 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
589 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
590 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
592 case ARM::S1: return ARM::S0;
593 case ARM::S3: return ARM::S2;
594 case ARM::S5: return ARM::S4;
595 case ARM::S7: return ARM::S6;
596 case ARM::S9: return ARM::S8;
597 case ARM::S11: return ARM::S10;
598 case ARM::S13: return ARM::S12;
599 case ARM::S15: return ARM::S14;
600 case ARM::S17: return ARM::S16;
601 case ARM::S19: return ARM::S18;
602 case ARM::S21: return ARM::S20;
603 case ARM::S23: return ARM::S22;
604 case ARM::S25: return ARM::S24;
605 case ARM::S27: return ARM::S26;
606 case ARM::S29: return ARM::S28;
607 case ARM::S31: return ARM::S30;
609 case ARM::D1: return ARM::D0;
610 case ARM::D3: return ARM::D2;
611 case ARM::D5: return ARM::D4;
612 case ARM::D7: return ARM::D6;
613 case ARM::D9: return ARM::D8;
614 case ARM::D11: return ARM::D10;
615 case ARM::D13: return ARM::D12;
616 case ARM::D15: return ARM::D14;
617 case ARM::D17: return ARM::D16;
618 case ARM::D19: return ARM::D18;
619 case ARM::D21: return ARM::D20;
620 case ARM::D23: return ARM::D22;
621 case ARM::D25: return ARM::D24;
622 case ARM::D27: return ARM::D26;
623 case ARM::D29: return ARM::D28;
624 case ARM::D31: return ARM::D30;
630 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
631 const MachineFunction &MF) const {
634 // Return 0 if either register of the pair is a special register.
636 case ARM::R0: return ARM::R1;
637 case ARM::R2: return ARM::R3;
638 case ARM::R4: return ARM::R5;
640 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
642 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
643 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
645 case ARM::S0: return ARM::S1;
646 case ARM::S2: return ARM::S3;
647 case ARM::S4: return ARM::S5;
648 case ARM::S6: return ARM::S7;
649 case ARM::S8: return ARM::S9;
650 case ARM::S10: return ARM::S11;
651 case ARM::S12: return ARM::S13;
652 case ARM::S14: return ARM::S15;
653 case ARM::S16: return ARM::S17;
654 case ARM::S18: return ARM::S19;
655 case ARM::S20: return ARM::S21;
656 case ARM::S22: return ARM::S23;
657 case ARM::S24: return ARM::S25;
658 case ARM::S26: return ARM::S27;
659 case ARM::S28: return ARM::S29;
660 case ARM::S30: return ARM::S31;
662 case ARM::D0: return ARM::D1;
663 case ARM::D2: return ARM::D3;
664 case ARM::D4: return ARM::D5;
665 case ARM::D6: return ARM::D7;
666 case ARM::D8: return ARM::D9;
667 case ARM::D10: return ARM::D11;
668 case ARM::D12: return ARM::D13;
669 case ARM::D14: return ARM::D15;
670 case ARM::D16: return ARM::D17;
671 case ARM::D18: return ARM::D19;
672 case ARM::D20: return ARM::D21;
673 case ARM::D22: return ARM::D23;
674 case ARM::D24: return ARM::D25;
675 case ARM::D26: return ARM::D27;
676 case ARM::D28: return ARM::D29;
677 case ARM::D30: return ARM::D31;
683 /// emitLoadConstPool - Emits a load from constpool to materialize the
684 /// specified immediate.
685 void ARMBaseRegisterInfo::
686 emitLoadConstPool(MachineBasicBlock &MBB,
687 MachineBasicBlock::iterator &MBBI,
689 unsigned DestReg, unsigned SubIdx, int Val,
690 ARMCC::CondCodes Pred,
691 unsigned PredReg, unsigned MIFlags) const {
692 MachineFunction &MF = *MBB.getParent();
693 MachineConstantPool *ConstantPool = MF.getConstantPool();
695 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
696 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
698 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
699 .addReg(DestReg, getDefRegState(true), SubIdx)
700 .addConstantPoolIndex(Idx)
701 .addImm(0).addImm(Pred).addReg(PredReg)
702 .setMIFlags(MIFlags);
705 bool ARMBaseRegisterInfo::
706 requiresRegisterScavenging(const MachineFunction &MF) const {
710 bool ARMBaseRegisterInfo::
711 requiresFrameIndexScavenging(const MachineFunction &MF) const {
715 bool ARMBaseRegisterInfo::
716 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
717 return EnableLocalStackAlloc;
721 emitSPUpdate(bool isARM,
722 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
723 DebugLoc dl, const ARMBaseInstrInfo &TII,
725 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
727 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
730 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
735 void ARMBaseRegisterInfo::
736 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
737 MachineBasicBlock::iterator I) const {
738 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
739 if (!TFI->hasReservedCallFrame(MF)) {
740 // If we have alloca, convert as follows:
741 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
742 // ADJCALLSTACKUP -> add, sp, sp, amount
743 MachineInstr *Old = I;
744 DebugLoc dl = Old->getDebugLoc();
745 unsigned Amount = Old->getOperand(0).getImm();
747 // We need to keep the stack aligned properly. To do this, we round the
748 // amount of space needed for the outgoing arguments up to the next
749 // alignment boundary.
750 unsigned Align = TFI->getStackAlignment();
751 Amount = (Amount+Align-1)/Align*Align;
753 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
754 assert(!AFI->isThumb1OnlyFunction() &&
755 "This eliminateCallFramePseudoInstr does not support Thumb1!");
756 bool isARM = !AFI->isThumbFunction();
758 // Replace the pseudo instruction with a new instruction...
759 unsigned Opc = Old->getOpcode();
760 int PIdx = Old->findFirstPredOperandIdx();
761 ARMCC::CondCodes Pred = (PIdx == -1)
762 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
763 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
764 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
765 unsigned PredReg = Old->getOperand(2).getReg();
766 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
768 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
769 unsigned PredReg = Old->getOperand(3).getReg();
770 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
771 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
778 int64_t ARMBaseRegisterInfo::
779 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
780 const MCInstrDesc &Desc = MI->getDesc();
781 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
782 int64_t InstrOffs = 0;;
786 case ARMII::AddrModeT2_i8:
787 case ARMII::AddrModeT2_i12:
788 case ARMII::AddrMode_i12:
789 InstrOffs = MI->getOperand(Idx+1).getImm();
792 case ARMII::AddrMode5: {
794 const MachineOperand &OffOp = MI->getOperand(Idx+1);
795 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
796 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
797 InstrOffs = -InstrOffs;
801 case ARMII::AddrMode2: {
803 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
804 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
805 InstrOffs = -InstrOffs;
808 case ARMII::AddrMode3: {
810 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
811 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
812 InstrOffs = -InstrOffs;
815 case ARMII::AddrModeT1_s: {
817 InstrOffs = MI->getOperand(ImmIdx).getImm();
822 llvm_unreachable("Unsupported addressing mode!");
825 return InstrOffs * Scale;
828 /// needsFrameBaseReg - Returns true if the instruction's frame index
829 /// reference would be better served by a base register other than FP
830 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
831 /// references it should create new base registers for.
832 bool ARMBaseRegisterInfo::
833 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
834 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
835 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
838 // It's the load/store FI references that cause issues, as it can be difficult
839 // to materialize the offset if it won't fit in the literal field. Estimate
840 // based on the size of the local frame and some conservative assumptions
841 // about the rest of the stack frame (note, this is pre-regalloc, so
842 // we don't know everything for certain yet) whether this offset is likely
843 // to be out of range of the immediate. Return true if so.
845 // We only generate virtual base registers for loads and stores, so
846 // return false for everything else.
847 unsigned Opc = MI->getOpcode();
849 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
850 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
851 case ARM::t2LDRi12: case ARM::t2LDRi8:
852 case ARM::t2STRi12: case ARM::t2STRi8:
853 case ARM::VLDRS: case ARM::VLDRD:
854 case ARM::VSTRS: case ARM::VSTRD:
855 case ARM::tSTRspi: case ARM::tLDRspi:
856 if (ForceAllBaseRegAlloc)
863 // Without a virtual base register, if the function has variable sized
864 // objects, all fixed-size local references will be via the frame pointer,
865 // Approximate the offset and see if it's legal for the instruction.
866 // Note that the incoming offset is based on the SP value at function entry,
867 // so it'll be negative.
868 MachineFunction &MF = *MI->getParent()->getParent();
869 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
870 MachineFrameInfo *MFI = MF.getFrameInfo();
871 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
873 // Estimate an offset from the frame pointer.
874 // Conservatively assume all callee-saved registers get pushed. R4-R6
875 // will be earlier than the FP, so we ignore those.
877 int64_t FPOffset = Offset - 8;
878 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
879 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
881 // Estimate an offset from the stack pointer.
882 // The incoming offset is relating to the SP at the start of the function,
883 // but when we access the local it'll be relative to the SP after local
884 // allocation, so adjust our SP-relative offset by that allocation size.
886 Offset += MFI->getLocalFrameSize();
887 // Assume that we'll have at least some spill slots allocated.
888 // FIXME: This is a total SWAG number. We should run some statistics
889 // and pick a real one.
890 Offset += 128; // 128 bytes of spill slots
892 // If there is a frame pointer, try using it.
893 // The FP is only available if there is no dynamic realignment. We
894 // don't know for sure yet whether we'll need that, so we guess based
895 // on whether there are any local variables that would trigger it.
896 unsigned StackAlign = TFI->getStackAlignment();
897 if (TFI->hasFP(MF) &&
898 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
899 if (isFrameOffsetLegal(MI, FPOffset))
902 // If we can reference via the stack pointer, try that.
903 // FIXME: This (and the code that resolves the references) can be improved
904 // to only disallow SP relative references in the live range of
905 // the VLA(s). In practice, it's unclear how much difference that
906 // would make, but it may be worth doing.
907 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
910 // The offset likely isn't legal, we want to allocate a virtual base register.
914 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
915 /// be a pointer to FrameIdx at the beginning of the basic block.
916 void ARMBaseRegisterInfo::
917 materializeFrameBaseRegister(MachineBasicBlock *MBB,
918 unsigned BaseReg, int FrameIdx,
919 int64_t Offset) const {
920 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
921 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
922 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
924 MachineBasicBlock::iterator Ins = MBB->begin();
925 DebugLoc DL; // Defaults to "unknown"
926 if (Ins != MBB->end())
927 DL = Ins->getDebugLoc();
929 const MCInstrDesc &MCID = TII.get(ADDriOpc);
930 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
931 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
933 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
934 .addFrameIndex(FrameIdx).addImm(Offset));
936 if (!AFI->isThumb1OnlyFunction())
941 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
942 unsigned BaseReg, int64_t Offset) const {
943 MachineInstr &MI = *I;
944 MachineBasicBlock &MBB = *MI.getParent();
945 MachineFunction &MF = *MBB.getParent();
946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
947 int Off = Offset; // ARM doesn't need the general 64-bit offsets
950 assert(!AFI->isThumb1OnlyFunction() &&
951 "This resolveFrameIndex does not support Thumb1!");
953 while (!MI.getOperand(i).isFI()) {
955 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
958 if (!AFI->isThumbFunction())
959 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
961 assert(AFI->isThumb2Function());
962 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
964 assert (Done && "Unable to resolve frame index!");
968 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
969 int64_t Offset) const {
970 const MCInstrDesc &Desc = MI->getDesc();
971 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
974 while (!MI->getOperand(i).isFI()) {
976 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
979 // AddrMode4 and AddrMode6 cannot handle any offset.
980 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
983 unsigned NumBits = 0;
985 bool isSigned = true;
987 case ARMII::AddrModeT2_i8:
988 case ARMII::AddrModeT2_i12:
989 // i8 supports only negative, and i12 supports only positive, so
990 // based on Offset sign, consider the appropriate instruction
999 case ARMII::AddrMode5:
1000 // VFP address mode.
1004 case ARMII::AddrMode_i12:
1005 case ARMII::AddrMode2:
1008 case ARMII::AddrMode3:
1011 case ARMII::AddrModeT1_s:
1017 llvm_unreachable("Unsupported addressing mode!");
1020 Offset += getFrameIndexInstrOffset(MI, i);
1021 // Make sure the offset is encodable for instructions that scale the
1023 if ((Offset & (Scale-1)) != 0)
1026 if (isSigned && Offset < 0)
1029 unsigned Mask = (1 << NumBits) - 1;
1030 if ((unsigned)Offset <= Mask * Scale)
1037 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1038 int SPAdj, RegScavenger *RS) const {
1040 MachineInstr &MI = *II;
1041 MachineBasicBlock &MBB = *MI.getParent();
1042 MachineFunction &MF = *MBB.getParent();
1043 const ARMFrameLowering *TFI =
1044 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1045 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1046 assert(!AFI->isThumb1OnlyFunction() &&
1047 "This eliminateFrameIndex does not support Thumb1!");
1049 while (!MI.getOperand(i).isFI()) {
1051 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1054 int FrameIndex = MI.getOperand(i).getIndex();
1057 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1059 // Special handling of dbg_value instructions.
1060 if (MI.isDebugValue()) {
1061 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1062 MI.getOperand(i+1).ChangeToImmediate(Offset);
1066 // Modify MI as necessary to handle as much of 'Offset' as possible
1068 if (!AFI->isThumbFunction())
1069 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1071 assert(AFI->isThumb2Function());
1072 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1077 // If we get here, the immediate doesn't fit into the instruction. We folded
1078 // as much as possible above, handle the rest, providing a register that is
1081 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1082 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1083 "This code isn't needed if offset already handled!");
1085 unsigned ScratchReg = 0;
1086 int PIdx = MI.findFirstPredOperandIdx();
1087 ARMCC::CondCodes Pred = (PIdx == -1)
1088 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1089 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1091 // Must be addrmode4/6.
1092 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1094 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1095 if (!AFI->isThumbFunction())
1096 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1097 Offset, Pred, PredReg, TII);
1099 assert(AFI->isThumb2Function());
1100 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1101 Offset, Pred, PredReg, TII);
1103 // Update the original instruction to use the scratch register.
1104 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);