1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
41 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
49 llvm_unreachable("Unknown ARM register!");
50 case R0: case D0: case Q0: return 0;
51 case R1: case D1: case Q1: return 1;
52 case R2: case D2: case Q2: return 2;
53 case R3: case D3: case Q3: return 3;
54 case R4: case D4: case Q4: return 4;
55 case R5: case D5: case Q5: return 5;
56 case R6: case D6: case Q6: return 6;
57 case R7: case D7: case Q7: return 7;
58 case R8: case D8: case Q8: return 8;
59 case R9: case D9: case Q9: return 9;
60 case R10: case D10: case Q10: return 10;
61 case R11: case D11: case Q11: return 11;
62 case R12: case D12: case Q12: return 12;
63 case SP: case D13: case Q13: return 13;
64 case LR: case D14: case Q14: return 14;
65 case PC: case D15: case Q15: return 15;
84 case S0: case S1: case S2: case S3:
85 case S4: case S5: case S6: case S7:
86 case S8: case S9: case S10: case S11:
87 case S12: case S13: case S14: case S15:
88 case S16: case S17: case S18: case S19:
89 case S20: case S21: case S22: case S23:
90 case S24: case S25: case S26: case S27:
91 case S28: case S29: case S30: case S31: {
95 default: return 0; // Avoid compile time warning.
133 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
134 const ARMSubtarget &sti)
135 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
137 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
141 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
142 static const unsigned CalleeSavedRegs[] = {
143 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
144 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
146 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
147 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
151 static const unsigned DarwinCalleeSavedRegs[] = {
152 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
154 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::R11, ARM::R10, ARM::R8,
157 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
158 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
161 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
164 const TargetRegisterClass* const *
165 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
166 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
167 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
168 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
169 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
171 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
172 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
176 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
179 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
186 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
189 &ARM::GPRRegClass, &ARM::GPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
196 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
197 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
198 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
199 &ARM::GPRRegClass, &ARM::GPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
206 if (STI.isThumb1Only()) {
207 return STI.isTargetDarwin()
208 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
210 return STI.isTargetDarwin()
211 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
214 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
215 // FIXME: avoid re-calculating this everytime.
216 BitVector Reserved(getNumRegs());
217 Reserved.set(ARM::SP);
218 Reserved.set(ARM::PC);
219 if (STI.isTargetDarwin() || hasFP(MF))
220 Reserved.set(FramePtr);
221 // Some targets reserve R9.
222 if (STI.isR9Reserved())
223 Reserved.set(ARM::R9);
227 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
228 unsigned Reg) const {
236 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
240 return STI.isR9Reserved();
246 const TargetRegisterClass *
247 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
248 return ARM::GPRRegisterClass;
251 /// getAllocationOrder - Returns the register allocation order for a specified
252 /// register class in the form of a pair of TargetRegisterClass iterators.
253 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
254 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
255 unsigned HintType, unsigned HintReg,
256 const MachineFunction &MF) const {
257 // Alternative register allocation orders when favoring even / odd registers
258 // of register pairs.
260 // No FP, R9 is available.
261 static const unsigned GPREven1[] = {
262 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
263 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
266 static const unsigned GPROdd1[] = {
267 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
268 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
272 // FP is R7, R9 is available.
273 static const unsigned GPREven2[] = {
274 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
275 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
278 static const unsigned GPROdd2[] = {
279 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
280 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
284 // FP is R11, R9 is available.
285 static const unsigned GPREven3[] = {
286 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
287 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
290 static const unsigned GPROdd3[] = {
291 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
292 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
296 // No FP, R9 is not available.
297 static const unsigned GPREven4[] = {
298 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
299 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
302 static const unsigned GPROdd4[] = {
303 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
304 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
308 // FP is R7, R9 is not available.
309 static const unsigned GPREven5[] = {
310 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
311 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
314 static const unsigned GPROdd5[] = {
315 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
316 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
320 // FP is R11, R9 is not available.
321 static const unsigned GPREven6[] = {
322 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
323 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
325 static const unsigned GPROdd6[] = {
326 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
327 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
331 if (HintType == ARMRI::RegPairEven) {
332 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
333 // It's no longer possible to fulfill this hint. Return the default
335 return std::make_pair(RC->allocation_order_begin(MF),
336 RC->allocation_order_end(MF));
338 if (!STI.isTargetDarwin() && !hasFP(MF)) {
339 if (!STI.isR9Reserved())
340 return std::make_pair(GPREven1,
341 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
343 return std::make_pair(GPREven4,
344 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
345 } else if (FramePtr == ARM::R7) {
346 if (!STI.isR9Reserved())
347 return std::make_pair(GPREven2,
348 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
350 return std::make_pair(GPREven5,
351 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
352 } else { // FramePtr == ARM::R11
353 if (!STI.isR9Reserved())
354 return std::make_pair(GPREven3,
355 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
357 return std::make_pair(GPREven6,
358 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
360 } else if (HintType == ARMRI::RegPairOdd) {
361 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
362 // It's no longer possible to fulfill this hint. Return the default
364 return std::make_pair(RC->allocation_order_begin(MF),
365 RC->allocation_order_end(MF));
367 if (!STI.isTargetDarwin() && !hasFP(MF)) {
368 if (!STI.isR9Reserved())
369 return std::make_pair(GPROdd1,
370 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
372 return std::make_pair(GPROdd4,
373 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
374 } else if (FramePtr == ARM::R7) {
375 if (!STI.isR9Reserved())
376 return std::make_pair(GPROdd2,
377 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
379 return std::make_pair(GPROdd5,
380 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
381 } else { // FramePtr == ARM::R11
382 if (!STI.isR9Reserved())
383 return std::make_pair(GPROdd3,
384 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
386 return std::make_pair(GPROdd6,
387 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
390 return std::make_pair(RC->allocation_order_begin(MF),
391 RC->allocation_order_end(MF));
394 /// ResolveRegAllocHint - Resolves the specified register allocation hint
395 /// to a physical register. Returns the physical register if it is successful.
397 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
398 const MachineFunction &MF) const {
399 if (Reg == 0 || !isPhysicalRegister(Reg))
403 else if (Type == (unsigned)ARMRI::RegPairOdd)
405 return getRegisterPairOdd(Reg, MF);
406 else if (Type == (unsigned)ARMRI::RegPairEven)
408 return getRegisterPairEven(Reg, MF);
413 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
414 MachineFunction &MF) const {
415 MachineRegisterInfo *MRI = &MF.getRegInfo();
416 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
417 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
418 Hint.first == (unsigned)ARMRI::RegPairEven) &&
419 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
420 // If 'Reg' is one of the even / odd register pair and it's now changed
421 // (e.g. coalesced) into a different register. The other register of the
422 // pair allocation hint must be updated to reflect the relationship
424 unsigned OtherReg = Hint.second;
425 Hint = MRI->getRegAllocationHint(OtherReg);
426 if (Hint.second == Reg)
427 // Make sure the pair has not already divorced.
428 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
432 /// hasFP - Return true if the specified function should have a dedicated frame
433 /// pointer register. This is true if the function has variable sized allocas
434 /// or if frame pointer elimination is disabled.
436 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
437 const MachineFrameInfo *MFI = MF.getFrameInfo();
438 return (NoFramePointerElim ||
439 MFI->hasVarSizedObjects() ||
440 MFI->isFrameAddressTaken());
443 bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
444 const MachineFrameInfo *MFI = MF.getFrameInfo();
445 if (NoFramePointerElim && MFI->hasCalls())
447 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
450 /// estimateStackSize - Estimate and return the size of the frame.
451 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
452 const MachineFrameInfo *FFI = MF.getFrameInfo();
454 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
455 int FixedOff = -FFI->getObjectOffset(i);
456 if (FixedOff > Offset) Offset = FixedOff;
458 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
459 if (FFI->isDeadObjectIndex(i))
461 Offset += FFI->getObjectSize(i);
462 unsigned Align = FFI->getObjectAlignment(i);
463 // Adjust to alignment boundary
464 Offset = (Offset+Align-1)/Align*Align;
466 return (unsigned)Offset;
469 /// estimateRSStackSizeLimit - Look at each instruction that references stack
470 /// frames and return the stack size limit beyond which some of these
471 /// instructions will require scratch register during their expansion later.
473 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
474 unsigned Limit = (1 << 12) - 1;
475 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
476 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
478 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
479 if (!I->getOperand(i).isFI()) continue;
481 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
482 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
483 if (AddrMode == ARMII::AddrMode3 ||
484 AddrMode == ARMII::AddrModeT2_i8)
487 if (AddrMode == ARMII::AddrMode5 ||
488 AddrMode == ARMII::AddrModeT2_i8s4)
489 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
491 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
492 // When the stack offset is negative, we will end up using
493 // the i8 instructions instead.
495 break; // At most one FI per instruction
504 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
505 RegScavenger *RS) const {
506 // This tells PEI to spill the FP as if it is any other callee-save register
507 // to take advantage the eliminateFrameIndex machinery. This also ensures it
508 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
509 // to combine multiple loads / stores.
510 bool CanEliminateFrame = true;
511 bool CS1Spilled = false;
512 bool LRSpilled = false;
513 unsigned NumGPRSpills = 0;
514 SmallVector<unsigned, 4> UnspilledCS1GPRs;
515 SmallVector<unsigned, 4> UnspilledCS2GPRs;
516 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
518 // Don't spill FP if the frame can be eliminated. This is determined
519 // by scanning the callee-save registers to see if any is used.
520 const unsigned *CSRegs = getCalleeSavedRegs();
521 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
522 for (unsigned i = 0; CSRegs[i]; ++i) {
523 unsigned Reg = CSRegs[i];
524 bool Spilled = false;
525 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
526 AFI->setCSRegisterIsSpilled(Reg);
528 CanEliminateFrame = false;
530 // Check alias registers too.
531 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
532 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
534 CanEliminateFrame = false;
539 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
540 CSRegClasses[i] == ARM::tGPRRegisterClass) {
544 if (!STI.isTargetDarwin()) {
551 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
566 if (!STI.isTargetDarwin()) {
567 UnspilledCS1GPRs.push_back(Reg);
577 UnspilledCS1GPRs.push_back(Reg);
580 UnspilledCS2GPRs.push_back(Reg);
587 bool ForceLRSpill = false;
588 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
589 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
590 // Force LR to be spilled if the Thumb function size is > 2048. This enables
591 // use of BL to implement far jump. If it turns out that it's not needed
592 // then the branch fix up path will undo it.
593 if (FnSize >= (1 << 11)) {
594 CanEliminateFrame = false;
599 bool ExtraCSSpill = false;
600 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
601 AFI->setHasStackFrame(true);
603 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
604 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
605 if (!LRSpilled && CS1Spilled) {
606 MF.getRegInfo().setPhysRegUsed(ARM::LR);
607 AFI->setCSRegisterIsSpilled(ARM::LR);
609 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
610 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
611 ForceLRSpill = false;
615 // Darwin ABI requires FP to point to the stack slot that contains the
617 if (STI.isTargetDarwin() || hasFP(MF)) {
618 MF.getRegInfo().setPhysRegUsed(FramePtr);
622 // If stack and double are 8-byte aligned and we are spilling an odd number
623 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
624 // the integer and double callee save areas.
625 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
626 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
627 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
628 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
629 unsigned Reg = UnspilledCS1GPRs[i];
630 // Don't spill high register if the function is thumb1
631 if (!AFI->isThumb1OnlyFunction() ||
632 isARMLowRegister(Reg) || Reg == ARM::LR) {
633 MF.getRegInfo().setPhysRegUsed(Reg);
634 AFI->setCSRegisterIsSpilled(Reg);
635 if (!isReservedReg(MF, Reg))
640 } else if (!UnspilledCS2GPRs.empty() &&
641 !AFI->isThumb1OnlyFunction()) {
642 unsigned Reg = UnspilledCS2GPRs.front();
643 MF.getRegInfo().setPhysRegUsed(Reg);
644 AFI->setCSRegisterIsSpilled(Reg);
645 if (!isReservedReg(MF, Reg))
650 // Estimate if we might need to scavenge a register at some point in order
651 // to materialize a stack offset. If so, either spill one additional
652 // callee-saved register or reserve a special spill slot to facilitate
653 // register scavenging. Thumb1 needs a spill slot for stack pointer
654 // adjustments also, even when the frame itself is small.
655 if (RS && !ExtraCSSpill) {
656 MachineFrameInfo *MFI = MF.getFrameInfo();
657 // If any of the stack slot references may be out of range of an
658 // immediate offset, make sure a register (or a spill slot) is
659 // available for the register scavenger. Note that if we're indexing
660 // off the frame pointer, the effective stack size is 4 bytes larger
661 // since the FP points to the previous FP.
662 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
663 >= estimateRSStackSizeLimit(MF)
664 || AFI->isThumb1OnlyFunction()) {
665 // If any non-reserved CS register isn't spilled, just spill one or two
666 // extra. That should take care of it!
667 unsigned NumExtras = TargetAlign / 4;
668 SmallVector<unsigned, 2> Extras;
669 while (NumExtras && !UnspilledCS1GPRs.empty()) {
670 unsigned Reg = UnspilledCS1GPRs.back();
671 UnspilledCS1GPRs.pop_back();
672 if (!isReservedReg(MF, Reg)) {
673 Extras.push_back(Reg);
677 // For non-Thumb1 functions, also check for hi-reg CS registers
678 if (!AFI->isThumb1OnlyFunction()) {
679 while (NumExtras && !UnspilledCS2GPRs.empty()) {
680 unsigned Reg = UnspilledCS2GPRs.back();
681 UnspilledCS2GPRs.pop_back();
682 if (!isReservedReg(MF, Reg)) {
683 Extras.push_back(Reg);
688 if (Extras.size() && NumExtras == 0) {
689 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
690 MF.getRegInfo().setPhysRegUsed(Extras[i]);
691 AFI->setCSRegisterIsSpilled(Extras[i]);
694 // Reserve a slot closest to SP or frame pointer.
695 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
696 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
697 RC->getAlignment()));
704 MF.getRegInfo().setPhysRegUsed(ARM::LR);
705 AFI->setCSRegisterIsSpilled(ARM::LR);
706 AFI->setLRIsSpilledForFarJump(true);
710 unsigned ARMBaseRegisterInfo::getRARegister() const {
714 unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
715 if (STI.isTargetDarwin() || hasFP(MF))
720 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
721 llvm_unreachable("What is the exception register");
725 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
726 llvm_unreachable("What is the exception handler register");
730 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
731 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
734 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
735 const MachineFunction &MF) const {
738 // Return 0 if either register of the pair is a special register.
744 return STI.isThumb1Only() ? 0 : ARM::R2;
748 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
750 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
752 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
824 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
825 const MachineFunction &MF) const {
828 // Return 0 if either register of the pair is a special register.
834 return STI.isThumb1Only() ? 0 : ARM::R3;
838 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
840 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
842 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
914 /// emitLoadConstPool - Emits a load from constpool to materialize the
915 /// specified immediate.
916 void ARMBaseRegisterInfo::
917 emitLoadConstPool(MachineBasicBlock &MBB,
918 MachineBasicBlock::iterator &MBBI,
920 unsigned DestReg, unsigned SubIdx, int Val,
921 ARMCC::CondCodes Pred,
922 unsigned PredReg) const {
923 MachineFunction &MF = *MBB.getParent();
924 MachineConstantPool *ConstantPool = MF.getConstantPool();
926 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
927 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
929 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
930 .addReg(DestReg, getDefRegState(true), SubIdx)
931 .addConstantPoolIndex(Idx)
932 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
935 bool ARMBaseRegisterInfo::
936 requiresRegisterScavenging(const MachineFunction &MF) const {
940 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
941 // not required, we reserve argument space for call sites in the function
942 // immediately on entry to the current function. This eliminates the need for
943 // add/sub sp brackets around call sites. Returns true if the call frame is
944 // included as part of the stack frame.
945 bool ARMBaseRegisterInfo::
946 hasReservedCallFrame(MachineFunction &MF) const {
947 const MachineFrameInfo *FFI = MF.getFrameInfo();
948 unsigned CFSize = FFI->getMaxCallFrameSize();
949 // It's not always a good idea to include the call frame as part of the
950 // stack frame. ARM (especially Thumb) has small immediate offset to
951 // address the stack frame. So a large call frame can cause poor codegen
952 // and may even makes it impossible to scavenge a register.
953 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
956 return !MF.getFrameInfo()->hasVarSizedObjects();
960 emitSPUpdate(bool isARM,
961 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
962 DebugLoc dl, const ARMBaseInstrInfo &TII,
964 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
966 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
969 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
974 void ARMBaseRegisterInfo::
975 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
976 MachineBasicBlock::iterator I) const {
977 if (!hasReservedCallFrame(MF)) {
978 // If we have alloca, convert as follows:
979 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
980 // ADJCALLSTACKUP -> add, sp, sp, amount
981 MachineInstr *Old = I;
982 DebugLoc dl = Old->getDebugLoc();
983 unsigned Amount = Old->getOperand(0).getImm();
985 // We need to keep the stack aligned properly. To do this, we round the
986 // amount of space needed for the outgoing arguments up to the next
987 // alignment boundary.
988 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
989 Amount = (Amount+Align-1)/Align*Align;
991 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
992 assert(!AFI->isThumb1OnlyFunction() &&
993 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
994 bool isARM = !AFI->isThumbFunction();
996 // Replace the pseudo instruction with a new instruction...
997 unsigned Opc = Old->getOpcode();
998 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
999 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1000 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1001 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1002 unsigned PredReg = Old->getOperand(2).getReg();
1003 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1005 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1006 unsigned PredReg = Old->getOperand(3).getReg();
1007 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1008 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1015 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
1016 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
1017 /// register first and then a spilled callee-saved register if that fails.
1019 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1020 ARMFunctionInfo *AFI) {
1021 unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
1022 assert(!AFI->isThumb1OnlyFunction());
1027 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1028 int SPAdj, RegScavenger *RS) const {
1030 MachineInstr &MI = *II;
1031 MachineBasicBlock &MBB = *MI.getParent();
1032 MachineFunction &MF = *MBB.getParent();
1033 const MachineFrameInfo *MFI = MF.getFrameInfo();
1034 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1035 assert(!AFI->isThumb1OnlyFunction() &&
1036 "This eliminateFrameIndex does not support Thumb1!");
1038 while (!MI.getOperand(i).isFI()) {
1040 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1043 unsigned FrameReg = ARM::SP;
1044 int FrameIndex = MI.getOperand(i).getIndex();
1045 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1047 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1048 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1049 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1050 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1051 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1052 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1053 else if (hasFP(MF) && AFI->hasStackFrame()) {
1054 assert(SPAdj == 0 && "Unexpected stack offset!");
1055 // Use frame pointer to reference fixed objects unless this is a
1056 // frameless function,
1057 FrameReg = getFrameRegister(MF);
1058 Offset -= AFI->getFramePtrSpillOffset();
1061 // modify MI as necessary to handle as much of 'Offset' as possible
1063 if (!AFI->isThumbFunction())
1064 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1066 assert(AFI->isThumb2Function());
1067 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1072 // If we get here, the immediate doesn't fit into the instruction. We folded
1073 // as much as possible above, handle the rest, providing a register that is
1076 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1077 "This code isn't needed if offset already handled!");
1079 // Insert a set of r12 with the full address: r12 = sp + offset
1080 // If the offset we have is too large to fit into the instruction, we need
1081 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1083 unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
1084 if (ScratchReg == 0)
1085 // No register is "free". Scavenge a register.
1086 ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
1087 int PIdx = MI.findFirstPredOperandIdx();
1088 ARMCC::CondCodes Pred = (PIdx == -1)
1089 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1090 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1092 // Must be addrmode4.
1093 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1095 if (!AFI->isThumbFunction())
1096 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1097 Offset, Pred, PredReg, TII);
1099 assert(AFI->isThumb2Function());
1100 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1101 Offset, Pred, PredReg, TII);
1103 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1107 /// Move iterator pass the next bunch of callee save load / store ops for
1108 /// the particular spill area (1: integer area 1, 2: integer area 2,
1109 /// 3: fp area, 0: don't care).
1110 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1111 MachineBasicBlock::iterator &MBBI,
1112 int Opc1, int Opc2, unsigned Area,
1113 const ARMSubtarget &STI) {
1114 while (MBBI != MBB.end() &&
1115 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1116 MBBI->getOperand(1).isFI()) {
1119 unsigned Category = 0;
1120 switch (MBBI->getOperand(0).getReg()) {
1121 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1125 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1126 Category = STI.isTargetDarwin() ? 2 : 1;
1128 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1129 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1136 if (Done || Category != Area)
1144 void ARMBaseRegisterInfo::
1145 emitPrologue(MachineFunction &MF) const {
1146 MachineBasicBlock &MBB = MF.front();
1147 MachineBasicBlock::iterator MBBI = MBB.begin();
1148 MachineFrameInfo *MFI = MF.getFrameInfo();
1149 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1150 assert(!AFI->isThumb1OnlyFunction() &&
1151 "This emitPrologue does not suppor Thumb1!");
1152 bool isARM = !AFI->isThumbFunction();
1153 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1154 unsigned NumBytes = MFI->getStackSize();
1155 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1156 DebugLoc dl = (MBBI != MBB.end() ?
1157 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1159 // Determine the sizes of each callee-save spill areas and record which frame
1160 // belongs to which callee-save spill areas.
1161 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1162 int FramePtrSpillFI = 0;
1164 // Allocate the vararg register save area. This is not counted in NumBytes.
1166 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1168 if (!AFI->hasStackFrame()) {
1170 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1174 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1175 unsigned Reg = CSI[i].getReg();
1176 int FI = CSI[i].getFrameIdx();
1183 if (Reg == FramePtr)
1184 FramePtrSpillFI = FI;
1185 AFI->addGPRCalleeSavedArea1Frame(FI);
1192 if (Reg == FramePtr)
1193 FramePtrSpillFI = FI;
1194 if (STI.isTargetDarwin()) {
1195 AFI->addGPRCalleeSavedArea2Frame(FI);
1198 AFI->addGPRCalleeSavedArea1Frame(FI);
1203 AFI->addDPRCalleeSavedAreaFrame(FI);
1208 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1209 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1210 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1212 // Set FP to point to the stack slot that contains the previous FP.
1213 // For Darwin, FP is R7, which has now been stored in spill area 1.
1214 // Otherwise, if this is not Darwin, all the callee-saved registers go
1215 // into spill area 1, including the FP in R11. In either case, it is
1216 // now safe to emit this assignment.
1217 if (STI.isTargetDarwin() || hasFP(MF)) {
1218 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1219 MachineInstrBuilder MIB =
1220 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1221 .addFrameIndex(FramePtrSpillFI).addImm(0);
1222 AddDefaultCC(AddDefaultPred(MIB));
1225 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1226 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1228 // Build the new SUBri to adjust SP for FP callee-save spill area.
1229 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1230 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1232 // Determine starting offsets of spill areas.
1233 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1234 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1235 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1236 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1237 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1238 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1239 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1241 NumBytes = DPRCSOffset;
1243 // Insert it after all the callee-save spills.
1244 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1245 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1248 if (STI.isTargetELF() && hasFP(MF)) {
1249 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1250 AFI->getFramePtrSpillOffset());
1253 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1254 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1255 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1258 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1259 for (unsigned i = 0; CSRegs[i]; ++i)
1260 if (Reg == CSRegs[i])
1265 static bool isCSRestore(MachineInstr *MI,
1266 const ARMBaseInstrInfo &TII,
1267 const unsigned *CSRegs) {
1268 return ((MI->getOpcode() == (int)ARM::FLDD ||
1269 MI->getOpcode() == (int)ARM::LDR ||
1270 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1271 MI->getOperand(1).isFI() &&
1272 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1275 void ARMBaseRegisterInfo::
1276 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1277 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1278 assert(MBBI->getDesc().isReturn() &&
1279 "Can only insert epilog into returning blocks");
1280 DebugLoc dl = MBBI->getDebugLoc();
1281 MachineFrameInfo *MFI = MF.getFrameInfo();
1282 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1283 assert(!AFI->isThumb1OnlyFunction() &&
1284 "This emitEpilogue does not suppor Thumb1!");
1285 bool isARM = !AFI->isThumbFunction();
1287 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1288 int NumBytes = (int)MFI->getStackSize();
1290 if (!AFI->hasStackFrame()) {
1292 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1294 // Unwind MBBI to point to first LDR / FLDD.
1295 const unsigned *CSRegs = getCalleeSavedRegs();
1296 if (MBBI != MBB.begin()) {
1299 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1300 if (!isCSRestore(MBBI, TII, CSRegs))
1304 // Move SP to start of FP callee save spill area.
1305 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1306 AFI->getGPRCalleeSavedArea2Size() +
1307 AFI->getDPRCalleeSavedAreaSize());
1309 // Darwin ABI requires FP to point to the stack slot that contains the
1311 bool HasFP = hasFP(MF);
1312 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1313 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1314 // Reset SP based on frame pointer only if the stack frame extends beyond
1315 // frame pointer stack slot or target is ELF and the function has FP.
1317 AFI->getGPRCalleeSavedArea2Size() ||
1318 AFI->getDPRCalleeSavedAreaSize() ||
1319 AFI->getDPRCalleeSavedAreaOffset()) {
1322 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1325 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1330 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1332 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1334 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1338 } else if (NumBytes)
1339 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1341 // Move SP to start of integer callee save spill area 2.
1342 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1343 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1345 // Move SP to start of integer callee save spill area 1.
1346 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1347 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1349 // Move SP to SP upon entry to the function.
1350 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1351 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1355 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1358 #include "ARMGenRegisterInfo.inc"