1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45 cl::desc("Force use of virtual base registers for stack load/store"));
47 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned Reg) {
61 llvm_unreachable("Unknown ARM register!");
62 case R0: case S0: case D0: case Q0: return 0;
63 case R1: case S1: case D1: case Q1: return 1;
64 case R2: case S2: case D2: case Q2: return 2;
65 case R3: case S3: case D3: case Q3: return 3;
66 case R4: case S4: case D4: case Q4: return 4;
67 case R5: case S5: case D5: case Q5: return 5;
68 case R6: case S6: case D6: case Q6: return 6;
69 case R7: case S7: case D7: case Q7: return 7;
70 case R8: case S8: case D8: case Q8: return 8;
71 case R9: case S9: case D9: case Q9: return 9;
72 case R10: case S10: case D10: case Q10: return 10;
73 case R11: case S11: case D11: case Q11: return 11;
74 case R12: case S12: case D12: case Q12: return 12;
75 case SP: case S13: case D13: case Q13: return 13;
76 case LR: case S14: case D14: case Q14: return 14;
77 case PC: case S15: case D15: case Q15: return 15;
79 case S16: case D16: return 16;
80 case S17: case D17: return 17;
81 case S18: case D18: return 18;
82 case S19: case D19: return 19;
83 case S20: case D20: return 20;
84 case S21: case D21: return 21;
85 case S22: case D22: return 22;
86 case S23: case D23: return 23;
87 case S24: case D24: return 24;
88 case S25: case D25: return 25;
89 case S26: case D26: return 26;
90 case S27: case D27: return 27;
91 case S28: case D28: return 28;
92 case S29: case D29: return 29;
93 case S30: case D30: return 30;
94 case S31: case D31: return 31;
98 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
99 const ARMSubtarget &sti)
100 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
102 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
107 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
108 static const unsigned CalleeSavedRegs[] = {
109 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
110 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
112 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
113 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
117 static const unsigned DarwinCalleeSavedRegs[] = {
118 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
120 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
121 ARM::R11, ARM::R10, ARM::R8,
123 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
124 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
127 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
130 BitVector ARMBaseRegisterInfo::
131 getReservedRegs(const MachineFunction &MF) const {
132 // FIXME: avoid re-calculating this everytime.
133 BitVector Reserved(getNumRegs());
134 Reserved.set(ARM::SP);
135 Reserved.set(ARM::PC);
136 Reserved.set(ARM::FPSCR);
138 Reserved.set(FramePtr);
139 if (hasBasePointer(MF))
140 Reserved.set(BasePtr);
141 // Some targets reserve R9.
142 if (STI.isR9Reserved())
143 Reserved.set(ARM::R9);
147 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
148 unsigned Reg) const {
155 if (hasBasePointer(MF))
160 if (FramePtr == Reg && hasFP(MF))
164 return STI.isR9Reserved();
170 const TargetRegisterClass *
171 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
172 const TargetRegisterClass *B,
173 unsigned SubIdx) const {
181 if (A->getSize() == 8) {
182 if (B == &ARM::SPR_8RegClass)
183 return &ARM::DPR_8RegClass;
184 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
185 if (A == &ARM::DPR_8RegClass)
187 return &ARM::DPR_VFP2RegClass;
190 if (A->getSize() == 16) {
191 if (B == &ARM::SPR_8RegClass)
192 return &ARM::QPR_8RegClass;
193 return &ARM::QPR_VFP2RegClass;
196 if (A->getSize() == 32) {
197 if (B == &ARM::SPR_8RegClass)
198 return 0; // Do not allow coalescing!
199 return &ARM::QQPR_VFP2RegClass;
202 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
203 return 0; // Do not allow coalescing!
210 if (A->getSize() == 16) {
211 if (B == &ARM::DPR_VFP2RegClass)
212 return &ARM::QPR_VFP2RegClass;
213 if (B == &ARM::DPR_8RegClass)
214 return 0; // Do not allow coalescing!
218 if (A->getSize() == 32) {
219 if (B == &ARM::DPR_VFP2RegClass)
220 return &ARM::QQPR_VFP2RegClass;
221 if (B == &ARM::DPR_8RegClass)
222 return 0; // Do not allow coalescing!
226 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
227 if (B != &ARM::DPRRegClass)
228 return 0; // Do not allow coalescing!
235 // D sub-registers of QQQQ registers.
236 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
238 return 0; // Do not allow coalescing!
244 if (A->getSize() == 32) {
245 if (B == &ARM::QPR_VFP2RegClass)
246 return &ARM::QQPR_VFP2RegClass;
247 if (B == &ARM::QPR_8RegClass)
248 return 0; // Do not allow coalescing!
252 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
253 if (B == &ARM::QPRRegClass)
255 return 0; // Do not allow coalescing!
259 // Q sub-registers of QQQQ registers.
260 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
262 return 0; // Do not allow coalescing!
269 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
270 SmallVectorImpl<unsigned> &SubIndices,
271 unsigned &NewSubIdx) const {
273 unsigned Size = RC->getSize() * 8;
277 NewSubIdx = 0; // Whole register.
278 unsigned NumRegs = SubIndices.size();
280 // 8 D registers -> 1 QQQQ register.
281 return (Size == 512 &&
282 SubIndices[0] == ARM::dsub_0 &&
283 SubIndices[1] == ARM::dsub_1 &&
284 SubIndices[2] == ARM::dsub_2 &&
285 SubIndices[3] == ARM::dsub_3 &&
286 SubIndices[4] == ARM::dsub_4 &&
287 SubIndices[5] == ARM::dsub_5 &&
288 SubIndices[6] == ARM::dsub_6 &&
289 SubIndices[7] == ARM::dsub_7);
290 } else if (NumRegs == 4) {
291 if (SubIndices[0] == ARM::qsub_0) {
292 // 4 Q registers -> 1 QQQQ register.
293 return (Size == 512 &&
294 SubIndices[1] == ARM::qsub_1 &&
295 SubIndices[2] == ARM::qsub_2 &&
296 SubIndices[3] == ARM::qsub_3);
297 } else if (SubIndices[0] == ARM::dsub_0) {
298 // 4 D registers -> 1 QQ register.
300 SubIndices[1] == ARM::dsub_1 &&
301 SubIndices[2] == ARM::dsub_2 &&
302 SubIndices[3] == ARM::dsub_3) {
304 NewSubIdx = ARM::qqsub_0;
307 } else if (SubIndices[0] == ARM::dsub_4) {
308 // 4 D registers -> 1 QQ register (2nd).
310 SubIndices[1] == ARM::dsub_5 &&
311 SubIndices[2] == ARM::dsub_6 &&
312 SubIndices[3] == ARM::dsub_7) {
313 NewSubIdx = ARM::qqsub_1;
316 } else if (SubIndices[0] == ARM::ssub_0) {
317 // 4 S registers -> 1 Q register.
319 SubIndices[1] == ARM::ssub_1 &&
320 SubIndices[2] == ARM::ssub_2 &&
321 SubIndices[3] == ARM::ssub_3) {
323 NewSubIdx = ARM::qsub_0;
327 } else if (NumRegs == 2) {
328 if (SubIndices[0] == ARM::qsub_0) {
329 // 2 Q registers -> 1 QQ register.
330 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
332 NewSubIdx = ARM::qqsub_0;
335 } else if (SubIndices[0] == ARM::qsub_2) {
336 // 2 Q registers -> 1 QQ register (2nd).
337 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
338 NewSubIdx = ARM::qqsub_1;
341 } else if (SubIndices[0] == ARM::dsub_0) {
342 // 2 D registers -> 1 Q register.
343 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
345 NewSubIdx = ARM::qsub_0;
348 } else if (SubIndices[0] == ARM::dsub_2) {
349 // 2 D registers -> 1 Q register (2nd).
350 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
351 NewSubIdx = ARM::qsub_1;
354 } else if (SubIndices[0] == ARM::dsub_4) {
355 // 2 D registers -> 1 Q register (3rd).
356 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
357 NewSubIdx = ARM::qsub_2;
360 } else if (SubIndices[0] == ARM::dsub_6) {
361 // 2 D registers -> 1 Q register (3rd).
362 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
363 NewSubIdx = ARM::qsub_3;
366 } else if (SubIndices[0] == ARM::ssub_0) {
367 // 2 S registers -> 1 D register.
368 if (SubIndices[1] == ARM::ssub_1) {
370 NewSubIdx = ARM::dsub_0;
373 } else if (SubIndices[0] == ARM::ssub_2) {
374 // 2 S registers -> 1 D register (2nd).
375 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
376 NewSubIdx = ARM::dsub_1;
385 const TargetRegisterClass *
386 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
387 return ARM::GPRRegisterClass;
390 /// getAllocationOrder - Returns the register allocation order for a specified
391 /// register class in the form of a pair of TargetRegisterClass iterators.
392 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
393 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
394 unsigned HintType, unsigned HintReg,
395 const MachineFunction &MF) const {
396 // Alternative register allocation orders when favoring even / odd registers
397 // of register pairs.
399 // No FP, R9 is available.
400 static const unsigned GPREven1[] = {
401 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
402 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
405 static const unsigned GPROdd1[] = {
406 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
407 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
411 // FP is R7, R9 is available.
412 static const unsigned GPREven2[] = {
413 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
414 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
417 static const unsigned GPROdd2[] = {
418 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
419 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
423 // FP is R11, R9 is available.
424 static const unsigned GPREven3[] = {
425 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
426 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
429 static const unsigned GPROdd3[] = {
430 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
431 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
435 // No FP, R9 is not available.
436 static const unsigned GPREven4[] = {
437 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
438 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
441 static const unsigned GPROdd4[] = {
442 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
443 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
447 // FP is R7, R9 is not available.
448 static const unsigned GPREven5[] = {
449 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
450 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
453 static const unsigned GPROdd5[] = {
454 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
455 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
459 // FP is R11, R9 is not available.
460 static const unsigned GPREven6[] = {
461 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
462 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
464 static const unsigned GPROdd6[] = {
465 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
466 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
470 if (HintType == ARMRI::RegPairEven) {
471 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
472 // It's no longer possible to fulfill this hint. Return the default
474 return std::make_pair(RC->allocation_order_begin(MF),
475 RC->allocation_order_end(MF));
478 if (!STI.isR9Reserved())
479 return std::make_pair(GPREven1,
480 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
482 return std::make_pair(GPREven4,
483 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
484 } else if (FramePtr == ARM::R7) {
485 if (!STI.isR9Reserved())
486 return std::make_pair(GPREven2,
487 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
489 return std::make_pair(GPREven5,
490 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
491 } else { // FramePtr == ARM::R11
492 if (!STI.isR9Reserved())
493 return std::make_pair(GPREven3,
494 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
496 return std::make_pair(GPREven6,
497 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
499 } else if (HintType == ARMRI::RegPairOdd) {
500 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
501 // It's no longer possible to fulfill this hint. Return the default
503 return std::make_pair(RC->allocation_order_begin(MF),
504 RC->allocation_order_end(MF));
507 if (!STI.isR9Reserved())
508 return std::make_pair(GPROdd1,
509 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
511 return std::make_pair(GPROdd4,
512 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
513 } else if (FramePtr == ARM::R7) {
514 if (!STI.isR9Reserved())
515 return std::make_pair(GPROdd2,
516 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
518 return std::make_pair(GPROdd5,
519 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
520 } else { // FramePtr == ARM::R11
521 if (!STI.isR9Reserved())
522 return std::make_pair(GPROdd3,
523 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
525 return std::make_pair(GPROdd6,
526 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
529 return std::make_pair(RC->allocation_order_begin(MF),
530 RC->allocation_order_end(MF));
533 /// ResolveRegAllocHint - Resolves the specified register allocation hint
534 /// to a physical register. Returns the physical register if it is successful.
536 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
537 const MachineFunction &MF) const {
538 if (Reg == 0 || !isPhysicalRegister(Reg))
542 else if (Type == (unsigned)ARMRI::RegPairOdd)
544 return getRegisterPairOdd(Reg, MF);
545 else if (Type == (unsigned)ARMRI::RegPairEven)
547 return getRegisterPairEven(Reg, MF);
552 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
553 MachineFunction &MF) const {
554 MachineRegisterInfo *MRI = &MF.getRegInfo();
555 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
556 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
557 Hint.first == (unsigned)ARMRI::RegPairEven) &&
558 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
559 // If 'Reg' is one of the even / odd register pair and it's now changed
560 // (e.g. coalesced) into a different register. The other register of the
561 // pair allocation hint must be updated to reflect the relationship
563 unsigned OtherReg = Hint.second;
564 Hint = MRI->getRegAllocationHint(OtherReg);
565 if (Hint.second == Reg)
566 // Make sure the pair has not already divorced.
567 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
571 /// hasFP - Return true if the specified function should have a dedicated frame
572 /// pointer register. This is true if the function has variable sized allocas
573 /// or if frame pointer elimination is disabled.
575 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
576 // Mac OS X requires FP not to be clobbered for backtracing purpose.
577 if (STI.isTargetDarwin())
580 const MachineFrameInfo *MFI = MF.getFrameInfo();
581 // Always eliminate non-leaf frame pointers.
582 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
583 needsStackRealignment(MF) ||
584 MFI->hasVarSizedObjects() ||
585 MFI->isFrameAddressTaken());
588 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
589 const MachineFrameInfo *MFI = MF.getFrameInfo();
590 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
592 if (!EnableBasePointer)
595 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
598 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
599 // negative range for ldr/str (255), and thumb1 is positive offsets only.
600 // It's going to be better to use the SP or Base Pointer instead. When there
601 // are variable sized objects, we can't reference off of the SP, so we
602 // reserve a Base Pointer.
603 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
604 // Conservatively estimate whether the negative offset from the frame
605 // pointer will be sufficient to reach. If a function has a smallish
606 // frame, it's less likely to have lots of spills and callee saved
607 // space, so it's all more likely to be within range of the frame pointer.
608 // If it's wrong, the scavenger will still enable access to work, it just
610 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
618 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
619 const MachineFrameInfo *MFI = MF.getFrameInfo();
620 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
621 // We can't realign the stack if:
622 // 1. Dynamic stack realignment is explicitly disabled,
623 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
624 // 3. There are VLAs in the function and the base pointer is disabled.
625 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
626 (!MFI->hasVarSizedObjects() || EnableBasePointer));
629 bool ARMBaseRegisterInfo::
630 needsStackRealignment(const MachineFunction &MF) const {
631 const MachineFrameInfo *MFI = MF.getFrameInfo();
632 const Function *F = MF.getFunction();
633 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
634 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
635 F->hasFnAttr(Attribute::StackAlignment));
637 return requiresRealignment && canRealignStack(MF);
640 bool ARMBaseRegisterInfo::
641 cannotEliminateFrame(const MachineFunction &MF) const {
642 const MachineFrameInfo *MFI = MF.getFrameInfo();
643 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
645 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
646 || needsStackRealignment(MF);
649 /// estimateStackSize - Estimate and return the size of the frame.
650 static unsigned estimateStackSize(MachineFunction &MF) {
651 const MachineFrameInfo *FFI = MF.getFrameInfo();
653 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
654 int FixedOff = -FFI->getObjectOffset(i);
655 if (FixedOff > Offset) Offset = FixedOff;
657 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
658 if (FFI->isDeadObjectIndex(i))
660 Offset += FFI->getObjectSize(i);
661 unsigned Align = FFI->getObjectAlignment(i);
662 // Adjust to alignment boundary
663 Offset = (Offset+Align-1)/Align*Align;
665 return (unsigned)Offset;
668 /// estimateRSStackSizeLimit - Look at each instruction that references stack
669 /// frames and return the stack size limit beyond which some of these
670 /// instructions will require a scratch register during their expansion later.
672 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
673 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
674 unsigned Limit = (1 << 12) - 1;
675 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
676 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
678 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
679 if (!I->getOperand(i).isFI()) continue;
681 // When using ADDri to get the address of a stack object, 255 is the
682 // largest offset guaranteed to fit in the immediate offset.
683 if (I->getOpcode() == ARM::ADDri) {
684 Limit = std::min(Limit, (1U << 8) - 1);
688 // Otherwise check the addressing mode.
689 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
690 case ARMII::AddrMode3:
691 case ARMII::AddrModeT2_i8:
692 Limit = std::min(Limit, (1U << 8) - 1);
694 case ARMII::AddrMode5:
695 case ARMII::AddrModeT2_i8s4:
696 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
698 case ARMII::AddrModeT2_i12:
699 // i12 supports only positive offset so these will be converted to
700 // i8 opcodes. See llvm::rewriteT2FrameIndex.
701 if (hasFP(MF) && AFI->hasStackFrame())
702 Limit = std::min(Limit, (1U << 8) - 1);
704 case ARMII::AddrMode6:
705 // Addressing mode 6 (load/store) instructions can't encode an
706 // immediate offset for stack references.
711 break; // At most one FI per instruction
719 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
720 const ARMBaseInstrInfo &TII) {
722 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
724 const MachineBasicBlock &MBB = *MBBI;
725 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
727 FnSize += TII.GetInstSizeInBytes(I);
733 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
734 RegScavenger *RS) const {
735 // This tells PEI to spill the FP as if it is any other callee-save register
736 // to take advantage the eliminateFrameIndex machinery. This also ensures it
737 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
738 // to combine multiple loads / stores.
739 bool CanEliminateFrame = true;
740 bool CS1Spilled = false;
741 bool LRSpilled = false;
742 unsigned NumGPRSpills = 0;
743 SmallVector<unsigned, 4> UnspilledCS1GPRs;
744 SmallVector<unsigned, 4> UnspilledCS2GPRs;
745 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
746 MachineFrameInfo *MFI = MF.getFrameInfo();
748 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
750 // FIXME: It will be better just to find spare register here.
751 if (needsStackRealignment(MF) &&
752 AFI->isThumb2Function())
753 MF.getRegInfo().setPhysRegUsed(ARM::R4);
755 // Spill LR if Thumb1 function uses variable length argument lists.
756 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
757 MF.getRegInfo().setPhysRegUsed(ARM::LR);
759 // Spill the BasePtr if it's used.
760 if (hasBasePointer(MF))
761 MF.getRegInfo().setPhysRegUsed(BasePtr);
763 // Don't spill FP if the frame can be eliminated. This is determined
764 // by scanning the callee-save registers to see if any is used.
765 const unsigned *CSRegs = getCalleeSavedRegs();
766 for (unsigned i = 0; CSRegs[i]; ++i) {
767 unsigned Reg = CSRegs[i];
768 bool Spilled = false;
769 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
770 AFI->setCSRegisterIsSpilled(Reg);
772 CanEliminateFrame = false;
774 // Check alias registers too.
775 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
776 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
778 CanEliminateFrame = false;
783 if (!ARM::GPRRegisterClass->contains(Reg))
789 if (!STI.isTargetDarwin()) {
796 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
811 if (!STI.isTargetDarwin()) {
812 UnspilledCS1GPRs.push_back(Reg);
822 UnspilledCS1GPRs.push_back(Reg);
825 UnspilledCS2GPRs.push_back(Reg);
831 bool ForceLRSpill = false;
832 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
833 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
834 // Force LR to be spilled if the Thumb function size is > 2048. This enables
835 // use of BL to implement far jump. If it turns out that it's not needed
836 // then the branch fix up path will undo it.
837 if (FnSize >= (1 << 11)) {
838 CanEliminateFrame = false;
843 // If any of the stack slot references may be out of range of an immediate
844 // offset, make sure a register (or a spill slot) is available for the
845 // register scavenger. Note that if we're indexing off the frame pointer, the
846 // effective stack size is 4 bytes larger since the FP points to the stack
847 // slot of the previous FP. Also, if we have variable sized objects in the
848 // function, stack slot references will often be negative, and some of
849 // our instructions are positive-offset only, so conservatively consider
850 // that case to want a spill slot (or register) as well. Similarly, if
851 // the function adjusts the stack pointer during execution and the
852 // adjustments aren't already part of our stack size estimate, our offset
853 // calculations may be off, so be conservative.
854 // FIXME: We could add logic to be more precise about negative offsets
855 // and which instructions will need a scratch register for them. Is it
856 // worth the effort and added fragility?
859 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
860 estimateRSStackSizeLimit(MF)))
861 || MFI->hasVarSizedObjects()
862 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
864 bool ExtraCSSpill = false;
865 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
866 AFI->setHasStackFrame(true);
868 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
869 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
870 if (!LRSpilled && CS1Spilled) {
871 MF.getRegInfo().setPhysRegUsed(ARM::LR);
872 AFI->setCSRegisterIsSpilled(ARM::LR);
874 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
875 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
876 ForceLRSpill = false;
881 MF.getRegInfo().setPhysRegUsed(FramePtr);
885 // If stack and double are 8-byte aligned and we are spilling an odd number
886 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
887 // the integer and double callee save areas.
888 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
889 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
890 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
891 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
892 unsigned Reg = UnspilledCS1GPRs[i];
893 // Don't spill high register if the function is thumb1
894 if (!AFI->isThumb1OnlyFunction() ||
895 isARMLowRegister(Reg) || Reg == ARM::LR) {
896 MF.getRegInfo().setPhysRegUsed(Reg);
897 AFI->setCSRegisterIsSpilled(Reg);
898 if (!isReservedReg(MF, Reg))
903 } else if (!UnspilledCS2GPRs.empty() &&
904 !AFI->isThumb1OnlyFunction()) {
905 unsigned Reg = UnspilledCS2GPRs.front();
906 MF.getRegInfo().setPhysRegUsed(Reg);
907 AFI->setCSRegisterIsSpilled(Reg);
908 if (!isReservedReg(MF, Reg))
913 // Estimate if we might need to scavenge a register at some point in order
914 // to materialize a stack offset. If so, either spill one additional
915 // callee-saved register or reserve a special spill slot to facilitate
916 // register scavenging. Thumb1 needs a spill slot for stack pointer
917 // adjustments also, even when the frame itself is small.
918 if (BigStack && !ExtraCSSpill) {
919 // If any non-reserved CS register isn't spilled, just spill one or two
920 // extra. That should take care of it!
921 unsigned NumExtras = TargetAlign / 4;
922 SmallVector<unsigned, 2> Extras;
923 while (NumExtras && !UnspilledCS1GPRs.empty()) {
924 unsigned Reg = UnspilledCS1GPRs.back();
925 UnspilledCS1GPRs.pop_back();
926 if (!isReservedReg(MF, Reg) &&
927 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
929 Extras.push_back(Reg);
933 // For non-Thumb1 functions, also check for hi-reg CS registers
934 if (!AFI->isThumb1OnlyFunction()) {
935 while (NumExtras && !UnspilledCS2GPRs.empty()) {
936 unsigned Reg = UnspilledCS2GPRs.back();
937 UnspilledCS2GPRs.pop_back();
938 if (!isReservedReg(MF, Reg)) {
939 Extras.push_back(Reg);
944 if (Extras.size() && NumExtras == 0) {
945 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
946 MF.getRegInfo().setPhysRegUsed(Extras[i]);
947 AFI->setCSRegisterIsSpilled(Extras[i]);
949 } else if (!AFI->isThumb1OnlyFunction()) {
950 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
951 // closest to SP or frame pointer.
952 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
953 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
961 MF.getRegInfo().setPhysRegUsed(ARM::LR);
962 AFI->setCSRegisterIsSpilled(ARM::LR);
963 AFI->setLRIsSpilledForFarJump(true);
967 unsigned ARMBaseRegisterInfo::getRARegister() const {
972 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
978 // Provide a base+offset reference to an FI slot for debug info. It's the
979 // same as what we use for resolving the code-gen references for now.
980 // FIXME: This can go wrong when references are SP-relative and simple call
981 // frames aren't used.
983 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
984 unsigned &FrameReg) const {
985 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
989 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
993 const MachineFrameInfo *MFI = MF.getFrameInfo();
994 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
995 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
996 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
997 bool isFixed = MFI->isFixedObjectIndex(FI);
1001 if (AFI->isGPRCalleeSavedArea1Frame(FI))
1002 return Offset - AFI->getGPRCalleeSavedArea1Offset();
1003 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1004 return Offset - AFI->getGPRCalleeSavedArea2Offset();
1005 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1006 return Offset - AFI->getDPRCalleeSavedAreaOffset();
1008 // When dynamically realigning the stack, use the frame pointer for
1009 // parameters, and the stack/base pointer for locals.
1010 if (needsStackRealignment(MF)) {
1011 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1013 FrameReg = getFrameRegister(MF);
1015 } else if (MFI->hasVarSizedObjects()) {
1016 assert(hasBasePointer(MF) &&
1017 "VLAs and dynamic stack alignment, but missing base pointer!");
1023 // If there is a frame pointer, use it when we can.
1024 if (hasFP(MF) && AFI->hasStackFrame()) {
1025 // Use frame pointer to reference fixed objects. Use it for locals if
1026 // there are VLAs (and thus the SP isn't reliable as a base).
1027 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
1028 FrameReg = getFrameRegister(MF);
1030 } else if (MFI->hasVarSizedObjects()) {
1031 assert(hasBasePointer(MF) && "missing base pointer!");
1032 // Use the base register since we have it.
1034 } else if (AFI->isThumb2Function()) {
1035 // In Thumb2 mode, the negative offset is very limited. Try to avoid
1036 // out of range references.
1037 if (FPOffset >= -255 && FPOffset < 0) {
1038 FrameReg = getFrameRegister(MF);
1041 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1042 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1043 FrameReg = getFrameRegister(MF);
1047 // Use the base pointer if we have one.
1048 if (hasBasePointer(MF))
1054 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1057 return getFrameIndexReference(MF, FI, FrameReg);
1060 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1061 llvm_unreachable("What is the exception register");
1065 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1066 llvm_unreachable("What is the exception handler register");
1070 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1071 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1074 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1075 const MachineFunction &MF) const {
1078 // Return 0 if either register of the pair is a special register.
1087 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1090 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1092 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1164 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1165 const MachineFunction &MF) const {
1168 // Return 0 if either register of the pair is a special register.
1177 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1180 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1182 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1254 /// emitLoadConstPool - Emits a load from constpool to materialize the
1255 /// specified immediate.
1256 void ARMBaseRegisterInfo::
1257 emitLoadConstPool(MachineBasicBlock &MBB,
1258 MachineBasicBlock::iterator &MBBI,
1260 unsigned DestReg, unsigned SubIdx, int Val,
1261 ARMCC::CondCodes Pred,
1262 unsigned PredReg) const {
1263 MachineFunction &MF = *MBB.getParent();
1264 MachineConstantPool *ConstantPool = MF.getConstantPool();
1266 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1267 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1269 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1270 .addReg(DestReg, getDefRegState(true), SubIdx)
1271 .addConstantPoolIndex(Idx)
1272 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1275 bool ARMBaseRegisterInfo::
1276 requiresRegisterScavenging(const MachineFunction &MF) const {
1280 bool ARMBaseRegisterInfo::
1281 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1285 bool ARMBaseRegisterInfo::
1286 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1287 return EnableLocalStackAlloc;
1290 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1291 // not required, we reserve argument space for call sites in the function
1292 // immediately on entry to the current function. This eliminates the need for
1293 // add/sub sp brackets around call sites. Returns true if the call frame is
1294 // included as part of the stack frame.
1295 bool ARMBaseRegisterInfo::
1296 hasReservedCallFrame(const MachineFunction &MF) const {
1297 const MachineFrameInfo *FFI = MF.getFrameInfo();
1298 unsigned CFSize = FFI->getMaxCallFrameSize();
1299 // It's not always a good idea to include the call frame as part of the
1300 // stack frame. ARM (especially Thumb) has small immediate offset to
1301 // address the stack frame. So a large call frame can cause poor codegen
1302 // and may even makes it impossible to scavenge a register.
1303 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1306 return !MF.getFrameInfo()->hasVarSizedObjects();
1309 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1310 // call frame pseudos can be simplified. Unlike most targets, having a FP
1311 // is not sufficient here since we still may reference some objects via SP
1312 // even when FP is available in Thumb2 mode.
1313 bool ARMBaseRegisterInfo::
1314 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1315 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1319 emitSPUpdate(bool isARM,
1320 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1321 DebugLoc dl, const ARMBaseInstrInfo &TII,
1323 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1325 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1326 Pred, PredReg, TII);
1328 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1329 Pred, PredReg, TII);
1333 void ARMBaseRegisterInfo::
1334 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1335 MachineBasicBlock::iterator I) const {
1336 if (!hasReservedCallFrame(MF)) {
1337 // If we have alloca, convert as follows:
1338 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1339 // ADJCALLSTACKUP -> add, sp, sp, amount
1340 MachineInstr *Old = I;
1341 DebugLoc dl = Old->getDebugLoc();
1342 unsigned Amount = Old->getOperand(0).getImm();
1344 // We need to keep the stack aligned properly. To do this, we round the
1345 // amount of space needed for the outgoing arguments up to the next
1346 // alignment boundary.
1347 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1348 Amount = (Amount+Align-1)/Align*Align;
1350 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1351 assert(!AFI->isThumb1OnlyFunction() &&
1352 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1353 bool isARM = !AFI->isThumbFunction();
1355 // Replace the pseudo instruction with a new instruction...
1356 unsigned Opc = Old->getOpcode();
1357 int PIdx = Old->findFirstPredOperandIdx();
1358 ARMCC::CondCodes Pred = (PIdx == -1)
1359 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1360 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1361 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1362 unsigned PredReg = Old->getOperand(2).getReg();
1363 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1365 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1366 unsigned PredReg = Old->getOperand(3).getReg();
1367 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1368 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1375 int64_t ARMBaseRegisterInfo::
1376 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1377 const TargetInstrDesc &Desc = MI->getDesc();
1378 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1379 int64_t InstrOffs = 0;;
1381 unsigned ImmIdx = 0;
1383 case ARMII::AddrModeT2_i8:
1384 case ARMII::AddrModeT2_i12:
1385 // i8 supports only negative, and i12 supports only positive, so
1386 // based on Offset sign, consider the appropriate instruction
1387 InstrOffs = MI->getOperand(Idx+1).getImm();
1390 case ARMII::AddrMode5: {
1391 // VFP address mode.
1392 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1393 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1394 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1395 InstrOffs = -InstrOffs;
1399 case ARMII::AddrMode2: {
1401 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1402 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1403 InstrOffs = -InstrOffs;
1406 case ARMII::AddrMode3: {
1408 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1409 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1410 InstrOffs = -InstrOffs;
1413 case ARMII::AddrModeT1_s: {
1415 InstrOffs = MI->getOperand(ImmIdx).getImm();
1420 llvm_unreachable("Unsupported addressing mode!");
1424 return InstrOffs * Scale;
1427 /// needsFrameBaseReg - Returns true if the instruction's frame index
1428 /// reference would be better served by a base register other than FP
1429 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1430 /// references it should create new base registers for.
1431 bool ARMBaseRegisterInfo::
1432 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1433 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1434 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1437 // It's the load/store FI references that cause issues, as it can be difficult
1438 // to materialize the offset if it won't fit in the literal field. Estimate
1439 // based on the size of the local frame and some conservative assumptions
1440 // about the rest of the stack frame (note, this is pre-regalloc, so
1441 // we don't know everything for certain yet) whether this offset is likely
1442 // to be out of range of the immediate. Return true if so.
1444 // We only generate virtual base registers for loads and stores, so
1445 // return false for everything else.
1446 unsigned Opc = MI->getOpcode();
1448 case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1449 case ARM::STR: case ARM::STRH: case ARM::STRB:
1450 case ARM::t2LDRi12: case ARM::t2LDRi8:
1451 case ARM::t2STRi12: case ARM::t2STRi8:
1452 case ARM::VLDRS: case ARM::VLDRD:
1453 case ARM::VSTRS: case ARM::VSTRD:
1454 case ARM::tSTRspi: case ARM::tLDRspi:
1455 if (ForceAllBaseRegAlloc)
1462 // Without a virtual base register, if the function has variable sized
1463 // objects, all fixed-size local references will be via the frame pointer,
1464 // Approximate the offset and see if it's legal for the instruction.
1465 // Note that the incoming offset is based on the SP value at function entry,
1466 // so it'll be negative.
1467 MachineFunction &MF = *MI->getParent()->getParent();
1468 MachineFrameInfo *MFI = MF.getFrameInfo();
1469 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1471 // Estimate an offset from the frame pointer.
1472 // Conservatively assume all callee-saved registers get pushed. R4-R6
1473 // will be earlier than the FP, so we ignore those.
1475 int64_t FPOffset = Offset - 8;
1476 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1477 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1479 // Estimate an offset from the stack pointer.
1480 // The incoming offset is relating to the SP at the start of the function,
1481 // but when we access the local it'll be relative to the SP after local
1482 // allocation, so adjust our SP-relative offset by that allocation size.
1484 Offset += MFI->getLocalFrameSize();
1485 // Assume that we'll have at least some spill slots allocated.
1486 // FIXME: This is a total SWAG number. We should run some statistics
1487 // and pick a real one.
1488 Offset += 128; // 128 bytes of spill slots
1490 // If there is a frame pointer, try using it.
1491 // The FP is only available if there is no dynamic realignment. We
1492 // don't know for sure yet whether we'll need that, so we guess based
1493 // on whether there are any local variables that would trigger it.
1494 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1496 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1497 if (isFrameOffsetLegal(MI, FPOffset))
1500 // If we can reference via the stack pointer, try that.
1501 // FIXME: This (and the code that resolves the references) can be improved
1502 // to only disallow SP relative references in the live range of
1503 // the VLA(s). In practice, it's unclear how much difference that
1504 // would make, but it may be worth doing.
1505 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1508 // The offset likely isn't legal, we want to allocate a virtual base register.
1512 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1513 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1514 void ARMBaseRegisterInfo::
1515 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1516 int FrameIdx, int64_t Offset) const {
1517 ARMFunctionInfo *AFI =
1518 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1519 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1520 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1522 MachineInstrBuilder MIB =
1523 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1524 .addFrameIndex(FrameIdx).addImm(Offset);
1525 if (!AFI->isThumb1OnlyFunction())
1526 AddDefaultCC(AddDefaultPred(MIB));
1530 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1531 unsigned BaseReg, int64_t Offset) const {
1532 MachineInstr &MI = *I;
1533 MachineBasicBlock &MBB = *MI.getParent();
1534 MachineFunction &MF = *MBB.getParent();
1535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1536 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1539 assert(!AFI->isThumb1OnlyFunction() &&
1540 "This resolveFrameIndex does not support Thumb1!");
1542 while (!MI.getOperand(i).isFI()) {
1544 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1547 if (!AFI->isThumbFunction())
1548 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1550 assert(AFI->isThumb2Function());
1551 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1553 assert (Done && "Unable to resolve frame index!");
1556 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1557 int64_t Offset) const {
1558 const TargetInstrDesc &Desc = MI->getDesc();
1559 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1562 while (!MI->getOperand(i).isFI()) {
1564 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1567 // AddrMode4 and AddrMode6 cannot handle any offset.
1568 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1571 unsigned NumBits = 0;
1573 bool isSigned = true;
1575 case ARMII::AddrModeT2_i8:
1576 case ARMII::AddrModeT2_i12:
1577 // i8 supports only negative, and i12 supports only positive, so
1578 // based on Offset sign, consider the appropriate instruction
1587 case ARMII::AddrMode5:
1588 // VFP address mode.
1592 case ARMII::AddrMode2:
1595 case ARMII::AddrMode3:
1598 case ARMII::AddrModeT1_s:
1604 llvm_unreachable("Unsupported addressing mode!");
1608 Offset += getFrameIndexInstrOffset(MI, i);
1609 // Make sure the offset is encodable for instructions that scale the
1611 if ((Offset & (Scale-1)) != 0)
1614 if (isSigned && Offset < 0)
1617 unsigned Mask = (1 << NumBits) - 1;
1618 if ((unsigned)Offset <= Mask * Scale)
1625 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1626 int SPAdj, RegScavenger *RS) const {
1628 MachineInstr &MI = *II;
1629 MachineBasicBlock &MBB = *MI.getParent();
1630 MachineFunction &MF = *MBB.getParent();
1631 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1632 assert(!AFI->isThumb1OnlyFunction() &&
1633 "This eliminateFrameIndex does not support Thumb1!");
1635 while (!MI.getOperand(i).isFI()) {
1637 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1640 int FrameIndex = MI.getOperand(i).getIndex();
1643 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1645 // Special handling of dbg_value instructions.
1646 if (MI.isDebugValue()) {
1647 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1648 MI.getOperand(i+1).ChangeToImmediate(Offset);
1652 // Modify MI as necessary to handle as much of 'Offset' as possible
1654 if (!AFI->isThumbFunction())
1655 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1657 assert(AFI->isThumb2Function());
1658 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1663 // If we get here, the immediate doesn't fit into the instruction. We folded
1664 // as much as possible above, handle the rest, providing a register that is
1667 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1668 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1669 "This code isn't needed if offset already handled!");
1671 unsigned ScratchReg = 0;
1672 int PIdx = MI.findFirstPredOperandIdx();
1673 ARMCC::CondCodes Pred = (PIdx == -1)
1674 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1675 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1677 // Must be addrmode4/6.
1678 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1680 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1681 if (!AFI->isThumbFunction())
1682 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1683 Offset, Pred, PredReg, TII);
1685 assert(AFI->isThumb2Function());
1686 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1687 Offset, Pred, PredReg, TII);
1689 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1693 /// Move iterator past the next bunch of callee save load / store ops for
1694 /// the particular spill area (1: integer area 1, 2: integer area 2,
1695 /// 3: fp area, 0: don't care).
1696 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1697 MachineBasicBlock::iterator &MBBI,
1698 int Opc1, int Opc2, unsigned Area,
1699 const ARMSubtarget &STI) {
1700 while (MBBI != MBB.end() &&
1701 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1702 MBBI->getOperand(1).isFI()) {
1705 unsigned Category = 0;
1706 switch (MBBI->getOperand(0).getReg()) {
1707 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1711 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1712 Category = STI.isTargetDarwin() ? 2 : 1;
1714 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1715 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1722 if (Done || Category != Area)
1730 void ARMBaseRegisterInfo::
1731 emitPrologue(MachineFunction &MF) const {
1732 MachineBasicBlock &MBB = MF.front();
1733 MachineBasicBlock::iterator MBBI = MBB.begin();
1734 MachineFrameInfo *MFI = MF.getFrameInfo();
1735 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1736 assert(!AFI->isThumb1OnlyFunction() &&
1737 "This emitPrologue does not support Thumb1!");
1738 bool isARM = !AFI->isThumbFunction();
1739 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1740 unsigned NumBytes = MFI->getStackSize();
1741 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1742 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1744 // Determine the sizes of each callee-save spill areas and record which frame
1745 // belongs to which callee-save spill areas.
1746 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1747 int FramePtrSpillFI = 0;
1749 // Allocate the vararg register save area. This is not counted in NumBytes.
1751 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1753 if (!AFI->hasStackFrame()) {
1755 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1759 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1760 unsigned Reg = CSI[i].getReg();
1761 int FI = CSI[i].getFrameIdx();
1768 if (Reg == FramePtr)
1769 FramePtrSpillFI = FI;
1770 AFI->addGPRCalleeSavedArea1Frame(FI);
1777 if (Reg == FramePtr)
1778 FramePtrSpillFI = FI;
1779 if (STI.isTargetDarwin()) {
1780 AFI->addGPRCalleeSavedArea2Frame(FI);
1783 AFI->addGPRCalleeSavedArea1Frame(FI);
1788 AFI->addDPRCalleeSavedAreaFrame(FI);
1793 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1794 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1795 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1797 // Set FP to point to the stack slot that contains the previous FP.
1798 // For Darwin, FP is R7, which has now been stored in spill area 1.
1799 // Otherwise, if this is not Darwin, all the callee-saved registers go
1800 // into spill area 1, including the FP in R11. In either case, it is
1801 // now safe to emit this assignment.
1802 bool HasFP = hasFP(MF);
1804 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1805 MachineInstrBuilder MIB =
1806 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1807 .addFrameIndex(FramePtrSpillFI).addImm(0);
1808 AddDefaultCC(AddDefaultPred(MIB));
1811 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1812 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1814 // Build the new SUBri to adjust SP for FP callee-save spill area.
1815 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1816 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1818 // Determine starting offsets of spill areas.
1819 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1820 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1821 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1823 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1825 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1826 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1827 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1829 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1830 NumBytes = DPRCSOffset;
1832 // Adjust SP after all the callee-save spills.
1833 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1835 AFI->setShouldRestoreSPFromFP(true);
1838 if (STI.isTargetELF() && hasFP(MF)) {
1839 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1840 AFI->getFramePtrSpillOffset());
1841 AFI->setShouldRestoreSPFromFP(true);
1844 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1845 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1846 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1848 // If we need dynamic stack realignment, do it here. Be paranoid and make
1849 // sure if we also have VLAs, we have a base pointer for frame access.
1850 if (needsStackRealignment(MF)) {
1851 unsigned MaxAlign = MFI->getMaxAlignment();
1852 assert (!AFI->isThumb1OnlyFunction());
1853 if (!AFI->isThumbFunction()) {
1854 // Emit bic sp, sp, MaxAlign
1855 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1856 TII.get(ARM::BICri), ARM::SP)
1857 .addReg(ARM::SP, RegState::Kill)
1858 .addImm(MaxAlign-1)));
1860 // We cannot use sp as source/dest register here, thus we're emitting the
1861 // following sequence:
1863 // bic r4, r4, MaxAlign
1865 // FIXME: It will be better just to find spare register here.
1866 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1867 .addReg(ARM::SP, RegState::Kill);
1868 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1869 TII.get(ARM::t2BICri), ARM::R4)
1870 .addReg(ARM::R4, RegState::Kill)
1871 .addImm(MaxAlign-1)));
1872 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1873 .addReg(ARM::R4, RegState::Kill);
1876 AFI->setShouldRestoreSPFromFP(true);
1879 // If we need a base pointer, set it up here. It's whatever the value
1880 // of the stack pointer is at this point. Any variable size objects
1881 // will be allocated after this, so we can still use the base pointer
1882 // to reference locals.
1883 if (hasBasePointer(MF)) {
1885 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1887 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1889 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1893 // If the frame has variable sized objects then the epilogue must restore
1895 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1896 AFI->setShouldRestoreSPFromFP(true);
1899 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1900 for (unsigned i = 0; CSRegs[i]; ++i)
1901 if (Reg == CSRegs[i])
1906 static bool isCSRestore(MachineInstr *MI,
1907 const ARMBaseInstrInfo &TII,
1908 const unsigned *CSRegs) {
1909 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1910 MI->getOpcode() == (int)ARM::LDR ||
1911 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1912 MI->getOperand(1).isFI() &&
1913 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1916 void ARMBaseRegisterInfo::
1917 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1918 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1919 assert(MBBI->getDesc().isReturn() &&
1920 "Can only insert epilog into returning blocks");
1921 unsigned RetOpcode = MBBI->getOpcode();
1922 DebugLoc dl = MBBI->getDebugLoc();
1923 MachineFrameInfo *MFI = MF.getFrameInfo();
1924 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1925 assert(!AFI->isThumb1OnlyFunction() &&
1926 "This emitEpilogue does not support Thumb1!");
1927 bool isARM = !AFI->isThumbFunction();
1929 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1930 int NumBytes = (int)MFI->getStackSize();
1932 if (!AFI->hasStackFrame()) {
1934 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1936 // Unwind MBBI to point to first LDR / VLDRD.
1937 const unsigned *CSRegs = getCalleeSavedRegs();
1938 if (MBBI != MBB.begin()) {
1941 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1942 if (!isCSRestore(MBBI, TII, CSRegs))
1946 // Move SP to start of FP callee save spill area.
1947 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1948 AFI->getGPRCalleeSavedArea2Size() +
1949 AFI->getDPRCalleeSavedAreaSize());
1951 // Reset SP based on frame pointer only if the stack frame extends beyond
1952 // frame pointer stack slot or target is ELF and the function has FP.
1953 if (AFI->shouldRestoreSPFromFP()) {
1954 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1957 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1960 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1965 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1966 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1968 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1971 } else if (NumBytes)
1972 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1974 // Move SP to start of integer callee save spill area 2.
1975 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1976 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1978 // Move SP to start of integer callee save spill area 1.
1979 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1980 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1982 // Move SP to SP upon entry to the function.
1983 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1984 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1987 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1988 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1989 // Tail call return: adjust the stack pointer and jump to callee.
1990 MBBI = prior(MBB.end());
1991 MachineOperand &JumpTarget = MBBI->getOperand(0);
1993 // Jump to label or value in register.
1994 if (RetOpcode == ARM::TCRETURNdi) {
1995 BuildMI(MBB, MBBI, dl,
1996 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1997 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1998 JumpTarget.getTargetFlags());
1999 } else if (RetOpcode == ARM::TCRETURNdiND) {
2000 BuildMI(MBB, MBBI, dl,
2001 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
2002 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
2003 JumpTarget.getTargetFlags());
2004 } else if (RetOpcode == ARM::TCRETURNri) {
2005 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
2006 addReg(JumpTarget.getReg(), RegState::Kill);
2007 } else if (RetOpcode == ARM::TCRETURNriND) {
2008 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
2009 addReg(JumpTarget.getReg(), RegState::Kill);
2012 MachineInstr *NewMI = prior(MBBI);
2013 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
2014 NewMI->addOperand(MBBI->getOperand(i));
2016 // Delete the pseudo instruction TCRETURN.
2021 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
2024 #include "ARMGenRegisterInfo.inc"