1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
49 const ARMBaseInstrInfo &TII;
50 const ARMSubtarget &STI;
52 /// FramePtr - ARM physical register used as frame ptr.
55 // Can be only subclassed.
56 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &STI);
59 // Return the opcode that implements 'Op', or 0 if no opcode
60 unsigned getOpcode(int Op) const;
63 /// getRegisterNumbering - Given the enum value for some register, e.g.
64 /// ARM::LR, return the number that it corresponds to (e.g. 14). It
65 /// also returns true in isSPVFP if the register is a single precision
67 static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
69 /// Code Generation virtual methods...
70 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
72 const TargetRegisterClass* const*
73 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
75 BitVector getReservedRegs(const MachineFunction &MF) const;
77 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
79 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
80 getAllocationOrder(const TargetRegisterClass *RC,
81 unsigned HintType, unsigned HintReg,
82 const MachineFunction &MF) const;
84 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
85 const MachineFunction &MF) const;
87 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
88 MachineFunction &MF) const;
90 bool hasFP(const MachineFunction &MF) const;
92 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
93 RegScavenger *RS = NULL) const;
95 // Debug information queries.
96 unsigned getRARegister() const;
97 unsigned getFrameRegister(MachineFunction &MF) const;
99 // Exception handling queries.
100 unsigned getEHExceptionRegister() const;
101 unsigned getEHHandlerRegister() const;
103 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
105 bool isLowRegister(unsigned Reg) const;
108 /// emitLoadConstPool - Emits a load from constpool to materialize the
109 /// specified immediate.
110 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator &MBBI,
113 unsigned DestReg, unsigned SubIdx,
115 ARMCC::CondCodes Pred = ARMCC::AL,
116 unsigned PredReg = 0) const;
118 /// Code Generation virtual methods...
119 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
121 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
123 virtual bool hasReservedCallFrame(MachineFunction &MF) const;
125 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
126 MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator I) const;
129 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
130 int SPAdj, RegScavenger *RS = NULL) const;
132 virtual void emitPrologue(MachineFunction &MF) const;
133 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
136 unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
138 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
140 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
143 } // end namespace llvm