1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "ARMGenRegisterInfo.h.inc"
23 class ARMBaseInstrInfo;
26 /// Register allocation hints.
34 /// isARMLowRegister - Returns true if the register is low register r0-r7.
36 static inline bool isARMLowRegister(unsigned Reg) {
39 case R0: case R1: case R2: case R3:
40 case R4: case R5: case R6: case R7:
47 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
48 /// or a stack/pc register that we should push/pop.
49 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
52 case R0: case R1: case R2: case R3:
53 case R4: case R5: case R6: case R7:
54 case LR: case SP: case PC:
56 case R8: case R9: case R10: case R11:
57 // For darwin we want r7 and lr to be next to each other.
64 static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
67 case R8: case R9: case R10: case R11:
68 // Darwin has this second area.
75 static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
78 case D15: case D14: case D13: case D12:
79 case D11: case D10: case D9: case D8:
86 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
88 const ARMBaseInstrInfo &TII;
89 const ARMSubtarget &STI;
91 /// FramePtr - ARM physical register used as frame ptr.
94 /// BasePtr - ARM physical register used as a base ptr in complex stack
95 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
96 /// variable size stack objects.
99 // Can be only subclassed.
100 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
101 const ARMSubtarget &STI);
103 // Return the opcode that implements 'Op', or 0 if no opcode
104 unsigned getOpcode(int Op) const;
107 /// Code Generation virtual methods...
108 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
110 BitVector getReservedRegs(const MachineFunction &MF) const;
112 /// getMatchingSuperRegClass - Return a subclass of the specified register
113 /// class A so that each register in it has a sub-register of the
114 /// specified sub-register index which is in the specified register class B.
115 virtual const TargetRegisterClass *
116 getMatchingSuperRegClass(const TargetRegisterClass *A,
117 const TargetRegisterClass *B, unsigned Idx) const;
119 /// canCombineSubRegIndices - Given a register class and a list of
120 /// subregister indices, return true if it's possible to combine the
121 /// subregister indices into one that corresponds to a larger
122 /// subregister. Return the new subregister index by reference. Note the
123 /// new index may be zero if the given subregisters can be combined to
124 /// form the whole register.
125 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
126 SmallVectorImpl<unsigned> &SubIndices,
127 unsigned &NewSubIdx) const;
129 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
131 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
132 getAllocationOrder(const TargetRegisterClass *RC,
133 unsigned HintType, unsigned HintReg,
134 const MachineFunction &MF) const;
136 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
137 const MachineFunction &MF) const;
139 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
140 MachineFunction &MF) const;
142 bool hasBasePointer(const MachineFunction &MF) const;
144 bool canRealignStack(const MachineFunction &MF) const;
145 bool needsStackRealignment(const MachineFunction &MF) const;
146 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
147 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
148 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
149 unsigned BaseReg, int FrameIdx,
150 int64_t Offset) const;
151 void resolveFrameIndex(MachineBasicBlock::iterator I,
152 unsigned BaseReg, int64_t Offset) const;
153 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
155 bool cannotEliminateFrame(const MachineFunction &MF) const;
157 // Debug information queries.
158 unsigned getRARegister() const;
159 unsigned getFrameRegister(const MachineFunction &MF) const;
160 unsigned getBaseRegister() const { return BasePtr; }
162 // Exception handling queries.
163 unsigned getEHExceptionRegister() const;
164 unsigned getEHHandlerRegister() const;
166 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
168 bool isLowRegister(unsigned Reg) const;
171 /// emitLoadConstPool - Emits a load from constpool to materialize the
172 /// specified immediate.
173 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
174 MachineBasicBlock::iterator &MBBI,
176 unsigned DestReg, unsigned SubIdx,
178 ARMCC::CondCodes Pred = ARMCC::AL,
179 unsigned PredReg = 0) const;
181 /// Code Generation virtual methods...
182 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
184 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
186 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
188 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
190 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
191 MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator I) const;
194 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
195 int SPAdj, RegScavenger *RS = NULL) const;
198 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
200 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
203 } // end namespace llvm