1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
25 class ARMBaseInstrInfo;
28 /// Register allocation hints.
36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
37 /// or a stack/pc register that we should push/pop.
38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 case LR: case SP: case PC:
45 case R8: case R9: case R10: case R11:
46 // For iOS we want r7 and lr to be next to each other.
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
56 case R8: case R9: case R10: case R11:
57 // iOS has this second area.
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
67 case D15: case D14: case D13: case D12:
68 case D11: case D10: case D9: case D8:
75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
77 const ARMSubtarget &STI;
79 /// FramePtr - ARM physical register used as frame ptr.
82 /// BasePtr - ARM physical register used as a base ptr in complex stack
83 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
84 /// variable size stack objects.
87 // Can be only subclassed.
88 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
90 // Return the opcode that implements 'Op', or 0 if no opcode
91 unsigned getOpcode(int Op) const;
94 /// Code Generation virtual methods...
95 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
96 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
97 const uint32_t *getNoPreservedMask() const;
99 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
100 /// case that 'returned' is on an i32 first argument if the calling convention
101 /// is one that can (partially) model this attribute with a preserved mask
102 /// (i.e. it is a calling convention that uses the same register for the first
103 /// i32 argument and an i32 return value)
105 /// Should return NULL in the case that the calling convention does not have
107 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
109 BitVector getReservedRegs(const MachineFunction &MF) const;
111 const TargetRegisterClass*
112 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
113 const TargetRegisterClass*
114 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
116 const TargetRegisterClass*
117 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
119 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
120 MachineFunction &MF) const;
122 void getRegAllocationHints(unsigned VirtReg,
123 ArrayRef<MCPhysReg> Order,
124 SmallVectorImpl<MCPhysReg> &Hints,
125 const MachineFunction &MF,
126 const VirtRegMap *VRM) const;
128 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
129 MachineFunction &MF) const;
131 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
133 bool hasBasePointer(const MachineFunction &MF) const;
135 bool canRealignStack(const MachineFunction &MF) const;
136 bool needsStackRealignment(const MachineFunction &MF) const;
137 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
138 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
139 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
140 unsigned BaseReg, int FrameIdx,
141 int64_t Offset) const;
142 void resolveFrameIndex(MachineBasicBlock::iterator I,
143 unsigned BaseReg, int64_t Offset) const;
144 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
146 bool cannotEliminateFrame(const MachineFunction &MF) const;
148 // Debug information queries.
149 unsigned getFrameRegister(const MachineFunction &MF) const;
150 unsigned getBaseRegister() const { return BasePtr; }
152 // Exception handling queries.
153 unsigned getEHExceptionRegister() const;
154 unsigned getEHHandlerRegister() const;
156 bool isLowRegister(unsigned Reg) const;
159 /// emitLoadConstPool - Emits a load from constpool to materialize the
160 /// specified immediate.
161 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator &MBBI,
164 unsigned DestReg, unsigned SubIdx,
166 ARMCC::CondCodes Pred = ARMCC::AL,
167 unsigned PredReg = 0,
168 unsigned MIFlags = MachineInstr::NoFlags)const;
170 /// Code Generation virtual methods...
171 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
173 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
175 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
177 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
179 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
180 int SPAdj, unsigned FIOperandNum,
181 RegScavenger *RS = NULL) const;
184 } // end namespace llvm