1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
24 /// Register allocation hints.
32 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
33 /// or a stack/pc register that we should push/pop.
34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
37 case R0: case R1: case R2: case R3:
38 case R4: case R5: case R6: case R7:
39 case LR: case SP: case PC:
41 case R8: case R9: case R10: case R11: case R12:
42 // For iOS we want r7 and lr to be next to each other.
49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
52 case R8: case R9: case R10: case R11: case R12:
53 // iOS has this second area.
60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
63 case D15: case D14: case D13: case D12:
64 case D11: case D10: case D9: case D8:
71 static inline bool isCalleeSavedRegister(unsigned Reg,
72 const MCPhysReg *CSRegs) {
73 for (unsigned i = 0; CSRegs[i]; ++i)
79 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
81 /// BasePtr - ARM physical register used as a base ptr in complex stack
82 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
83 /// variable size stack objects.
86 // Can be only subclassed.
87 explicit ARMBaseRegisterInfo();
89 // Return the opcode that implements 'Op', or 0 if no opcode
90 unsigned getOpcode(int Op) const;
93 /// Code Generation virtual methods...
94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
95 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
96 CallingConv::ID) const override;
97 const uint32_t *getNoPreservedMask() const;
99 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
100 /// case that 'returned' is on an i32 first argument if the calling convention
101 /// is one that can (partially) model this attribute with a preserved mask
102 /// (i.e. it is a calling convention that uses the same register for the first
103 /// i32 argument and an i32 return value)
105 /// Should return NULL in the case that the calling convention does not have
107 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
108 CallingConv::ID) const;
110 BitVector getReservedRegs(const MachineFunction &MF) const override;
112 const TargetRegisterClass *
113 getPointerRegClass(const MachineFunction &MF,
114 unsigned Kind = 0) const override;
115 const TargetRegisterClass *
116 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
118 const TargetRegisterClass *
119 getLargestLegalSuperClass(const TargetRegisterClass *RC,
120 const MachineFunction &MF) const override;
122 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
123 MachineFunction &MF) const override;
125 void getRegAllocationHints(unsigned VirtReg,
126 ArrayRef<MCPhysReg> Order,
127 SmallVectorImpl<MCPhysReg> &Hints,
128 const MachineFunction &MF,
129 const VirtRegMap *VRM,
130 const LiveRegMatrix *Matrix) const override;
132 void updateRegAllocHint(unsigned Reg, unsigned NewReg,
133 MachineFunction &MF) const override;
135 bool hasBasePointer(const MachineFunction &MF) const;
137 bool canRealignStack(const MachineFunction &MF) const override;
138 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
139 int Idx) const override;
140 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
141 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
142 unsigned BaseReg, int FrameIdx,
143 int64_t Offset) const override;
144 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
145 int64_t Offset) const override;
146 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
147 int64_t Offset) const override;
149 bool cannotEliminateFrame(const MachineFunction &MF) const;
151 // Debug information queries.
152 unsigned getFrameRegister(const MachineFunction &MF) const override;
153 unsigned getBaseRegister() const { return BasePtr; }
155 bool isLowRegister(unsigned Reg) const;
158 /// emitLoadConstPool - Emits a load from constpool to materialize the
159 /// specified immediate.
160 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator &MBBI,
162 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
163 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
164 unsigned PredReg = 0,
165 unsigned MIFlags = MachineInstr::NoFlags)const;
167 /// Code Generation virtual methods...
168 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
170 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
172 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
174 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
176 void eliminateFrameIndex(MachineBasicBlock::iterator II,
177 int SPAdj, unsigned FIOperandNum,
178 RegScavenger *RS = nullptr) const override;
180 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
181 bool shouldCoalesce(MachineInstr *MI,
182 const TargetRegisterClass *SrcRC,
184 const TargetRegisterClass *DstRC,
186 const TargetRegisterClass *NewRC) const override;
189 } // end namespace llvm