1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
25 class ARMBaseInstrInfo;
28 /// Register allocation hints.
36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
37 /// or a stack/pc register that we should push/pop.
38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 case LR: case SP: case PC:
45 case R8: case R9: case R10: case R11:
46 // For iOS we want r7 and lr to be next to each other.
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
56 case R8: case R9: case R10: case R11:
57 // iOS has this second area.
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
67 case D15: case D14: case D13: case D12:
68 case D11: case D10: case D9: case D8:
75 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
77 const ARMBaseInstrInfo &TII;
78 const ARMSubtarget &STI;
80 /// FramePtr - ARM physical register used as frame ptr.
83 /// BasePtr - ARM physical register used as a base ptr in complex stack
84 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
85 /// variable size stack objects.
88 // Can be only subclassed.
89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
90 const ARMSubtarget &STI);
92 // Return the opcode that implements 'Op', or 0 if no opcode
93 unsigned getOpcode(int Op) const;
96 /// Code Generation virtual methods...
97 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
98 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
100 BitVector getReservedRegs(const MachineFunction &MF) const;
102 /// canCombineSubRegIndices - Given a register class and a list of
103 /// subregister indices, return true if it's possible to combine the
104 /// subregister indices into one that corresponds to a larger
105 /// subregister. Return the new subregister index by reference. Note the
106 /// new index may be zero if the given subregisters can be combined to
107 /// form the whole register.
108 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
109 SmallVectorImpl<unsigned> &SubIndices,
110 unsigned &NewSubIdx) const;
112 const TargetRegisterClass*
113 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
114 const TargetRegisterClass*
115 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
117 const TargetRegisterClass*
118 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
120 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
121 MachineFunction &MF) const;
123 ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC,
124 unsigned HintType, unsigned HintReg,
125 const MachineFunction &MF) const;
127 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
128 const MachineFunction &MF) const;
130 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
131 MachineFunction &MF) const;
133 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
135 bool hasBasePointer(const MachineFunction &MF) const;
137 bool canRealignStack(const MachineFunction &MF) const;
138 bool needsStackRealignment(const MachineFunction &MF) const;
139 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
140 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
141 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
142 unsigned BaseReg, int FrameIdx,
143 int64_t Offset) const;
144 void resolveFrameIndex(MachineBasicBlock::iterator I,
145 unsigned BaseReg, int64_t Offset) const;
146 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
148 bool cannotEliminateFrame(const MachineFunction &MF) const;
150 // Debug information queries.
151 unsigned getFrameRegister(const MachineFunction &MF) const;
152 unsigned getBaseRegister() const { return BasePtr; }
154 // Exception handling queries.
155 unsigned getEHExceptionRegister() const;
156 unsigned getEHHandlerRegister() const;
158 bool isLowRegister(unsigned Reg) const;
161 /// emitLoadConstPool - Emits a load from constpool to materialize the
162 /// specified immediate.
163 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator &MBBI,
166 unsigned DestReg, unsigned SubIdx,
168 ARMCC::CondCodes Pred = ARMCC::AL,
169 unsigned PredReg = 0,
170 unsigned MIFlags = MachineInstr::NoFlags)const;
172 /// Code Generation virtual methods...
173 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
175 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
177 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
179 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
181 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
183 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
184 MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator I) const;
187 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
188 int SPAdj, RegScavenger *RS = NULL) const;
191 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
193 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
196 } // end namespace llvm