1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
25 class ARMBaseInstrInfo;
28 /// Register allocation hints.
36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
37 /// or a stack/pc register that we should push/pop.
38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 case LR: case SP: case PC:
45 case R8: case R9: case R10: case R11:
46 // For iOS we want r7 and lr to be next to each other.
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
56 case R8: case R9: case R10: case R11:
57 // iOS has this second area.
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
67 case D15: case D14: case D13: case D12:
68 case D11: case D10: case D9: case D8:
75 static inline bool isCalleeSavedRegister(unsigned Reg,
76 const MCPhysReg *CSRegs) {
77 for (unsigned i = 0; CSRegs[i]; ++i)
83 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
85 const ARMSubtarget &STI;
87 /// FramePtr - ARM physical register used as frame ptr.
90 /// BasePtr - ARM physical register used as a base ptr in complex stack
91 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
92 /// variable size stack objects.
95 // Can be only subclassed.
96 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI);
98 // Return the opcode that implements 'Op', or 0 if no opcode
99 unsigned getOpcode(int Op) const;
102 /// Code Generation virtual methods...
103 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
104 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
105 const uint32_t *getNoPreservedMask() const;
107 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
108 /// case that 'returned' is on an i32 first argument if the calling convention
109 /// is one that can (partially) model this attribute with a preserved mask
110 /// (i.e. it is a calling convention that uses the same register for the first
111 /// i32 argument and an i32 return value)
113 /// Should return NULL in the case that the calling convention does not have
115 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
117 BitVector getReservedRegs(const MachineFunction &MF) const;
119 const TargetRegisterClass*
120 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
121 const TargetRegisterClass*
122 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
124 const TargetRegisterClass*
125 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
127 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
128 MachineFunction &MF) const;
130 void getRegAllocationHints(unsigned VirtReg,
131 ArrayRef<MCPhysReg> Order,
132 SmallVectorImpl<MCPhysReg> &Hints,
133 const MachineFunction &MF,
134 const VirtRegMap *VRM) const;
136 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
137 MachineFunction &MF) const;
139 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
141 bool hasBasePointer(const MachineFunction &MF) const;
143 bool canRealignStack(const MachineFunction &MF) const;
144 bool needsStackRealignment(const MachineFunction &MF) const;
145 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
146 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
147 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
148 unsigned BaseReg, int FrameIdx,
149 int64_t Offset) const;
150 void resolveFrameIndex(MachineBasicBlock::iterator I,
151 unsigned BaseReg, int64_t Offset) const;
152 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
154 bool cannotEliminateFrame(const MachineFunction &MF) const;
156 // Debug information queries.
157 unsigned getFrameRegister(const MachineFunction &MF) const;
158 unsigned getBaseRegister() const { return BasePtr; }
160 bool isLowRegister(unsigned Reg) const;
163 /// emitLoadConstPool - Emits a load from constpool to materialize the
164 /// specified immediate.
165 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
166 MachineBasicBlock::iterator &MBBI,
168 unsigned DestReg, unsigned SubIdx,
170 ARMCC::CondCodes Pred = ARMCC::AL,
171 unsigned PredReg = 0,
172 unsigned MIFlags = MachineInstr::NoFlags)const;
174 /// Code Generation virtual methods...
175 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
177 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
179 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
181 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
183 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
184 int SPAdj, unsigned FIOperandNum,
185 RegScavenger *RS = NULL) const;
188 } // end namespace llvm