1 //===- ARMCallingConv.td - Calling Conventions for ARM ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for ARM architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>:
14 CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
16 /// CCIfAlign - Match of the original alignment of the arg
17 class CCIfAlign<string Align, CCAction A>:
18 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
20 //===----------------------------------------------------------------------===//
21 // ARM APCS Calling Convention
22 //===----------------------------------------------------------------------===//
23 def CC_ARM_APCS : CallingConv<[
25 CCIfType<[i8, i16], CCPromoteToType<i32>>,
27 // f64 is passed in pairs of GPRs, possibly split onto the stack
28 CCIfType<[f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
30 CCIfType<[f32], CCBitConvertToType<i32>>,
31 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
33 CCIfType<[i32], CCAssignToStack<4, 4>>,
34 CCIfType<[f64], CCAssignToStack<8, 4>>
37 def RetCC_ARM_APCS : CallingConv<[
38 CCIfType<[f32], CCBitConvertToType<i32>>,
39 CCIfType<[f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
41 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
42 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
45 //===----------------------------------------------------------------------===//
46 // ARM AAPCS (EABI) Calling Convention, common parts
47 //===----------------------------------------------------------------------===//
49 def CC_ARM_AAPCS_Common : CallingConv<[
51 CCIfType<[i8, i16], CCPromoteToType<i32>>,
53 // i64/f64 is passed in even pairs of GPRs
54 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
55 // (and the same is true for f64 if VFP is not enabled)
56 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
57 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
58 "ArgFlags.getOrigAlign() != 8",
59 CCAssignToReg<[R0, R1, R2, R3]>>>,
61 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
62 CCIfType<[f64], CCAssignToStack<8, 8>>
65 def RetCC_ARM_AAPCS_Common : CallingConv<[
66 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
67 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
70 //===----------------------------------------------------------------------===//
71 // ARM AAPCS (EABI) Calling Convention
72 //===----------------------------------------------------------------------===//
74 def CC_ARM_AAPCS : CallingConv<[
75 CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
76 CCIfType<[f32], CCBitConvertToType<i32>>,
77 CCDelegateTo<CC_ARM_AAPCS_Common>
80 def RetCC_ARM_AAPCS : CallingConv<[
81 CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
82 CCIfType<[f32], CCBitConvertToType<i32>>,
83 CCDelegateTo<RetCC_ARM_AAPCS_Common>
86 //===----------------------------------------------------------------------===//
87 // ARM AAPCS-VFP (EABI) Calling Convention
88 //===----------------------------------------------------------------------===//
90 def CC_ARM_AAPCS_VFP : CallingConv<[
91 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
92 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
93 S9, S10, S11, S12, S13, S14, S15]>>,
94 CCDelegateTo<CC_ARM_AAPCS_Common>
97 def RetCC_ARM_AAPCS_VFP : CallingConv<[
98 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
99 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
100 S9, S10, S11, S12, S13, S14, S15]>>,
101 CCDelegateTo<RetCC_ARM_AAPCS_Common>