1 //===- ARMCallingConv.td - Calling Conventions for ARM ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for ARM architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>:
14 CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
16 /// CCIfAlign - Match of the original alignment of the arg
17 class CCIfAlign<string Align, CCAction A>:
18 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
20 //===----------------------------------------------------------------------===//
21 // ARM APCS Calling Convention
22 //===----------------------------------------------------------------------===//
23 def CC_ARM_APCS : CallingConv<[
25 CCIfType<[i8, i16], CCPromoteToType<i32>>,
27 // Handle all vector types as either f64 or v2f64.
28 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
29 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
31 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
32 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
34 CCIfType<[f32], CCBitConvertToType<i32>>,
35 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
37 CCIfType<[i32], CCAssignToStack<4, 4>>,
38 CCIfType<[f64], CCAssignToStack<8, 4>>,
39 CCIfType<[v2f64], CCAssignToStack<16, 4>>
42 def RetCC_ARM_APCS : CallingConv<[
43 CCIfType<[f32], CCBitConvertToType<i32>>,
45 // Handle all vector types as either f64 or v2f64.
46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
55 //===----------------------------------------------------------------------===//
56 // ARM AAPCS (EABI) Calling Convention, common parts
57 //===----------------------------------------------------------------------===//
59 def CC_ARM_AAPCS_Common : CallingConv<[
61 CCIfType<[i8, i16], CCPromoteToType<i32>>,
63 // i64/f64 is passed in even pairs of GPRs
64 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
65 // (and the same is true for f64 if VFP is not enabled)
66 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
67 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
68 "ArgFlags.getOrigAlign() != 8",
69 CCAssignToReg<[R0, R1, R2, R3]>>>,
71 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
72 CCIfType<[f64], CCAssignToStack<8, 8>>,
73 CCIfType<[v2f64], CCAssignToStack<16, 8>>
76 def RetCC_ARM_AAPCS_Common : CallingConv<[
77 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
78 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
81 //===----------------------------------------------------------------------===//
82 // ARM AAPCS (EABI) Calling Convention
83 //===----------------------------------------------------------------------===//
85 def CC_ARM_AAPCS : CallingConv<[
86 // Handle all vector types as either f64 or v2f64.
87 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
88 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
90 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
91 CCIfType<[f32], CCBitConvertToType<i32>>,
92 CCDelegateTo<CC_ARM_AAPCS_Common>
95 def RetCC_ARM_AAPCS : CallingConv<[
96 // Handle all vector types as either f64 or v2f64.
97 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
98 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
100 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
101 CCIfType<[f32], CCBitConvertToType<i32>>,
102 CCDelegateTo<RetCC_ARM_AAPCS_Common>
105 //===----------------------------------------------------------------------===//
106 // ARM AAPCS-VFP (EABI) Calling Convention
107 //===----------------------------------------------------------------------===//
109 def CC_ARM_AAPCS_VFP : CallingConv<[
110 // Handle all vector types as either f64 or v2f64.
111 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
114 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
115 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
116 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
117 S9, S10, S11, S12, S13, S14, S15]>>,
118 CCDelegateTo<CC_ARM_AAPCS_Common>
121 def RetCC_ARM_AAPCS_VFP : CallingConv<[
122 // Handle all vector types as either f64 or v2f64.
123 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
124 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
126 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
127 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
128 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
129 S9, S10, S11, S12, S13, S14, S15]>>,
130 CCDelegateTo<RetCC_ARM_AAPCS_Common>