1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for ARM architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfAlign - Match of the original alignment of the arg
13 class CCIfAlign<string Align, CCAction A>:
14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
16 //===----------------------------------------------------------------------===//
17 // ARM APCS Calling Convention
18 //===----------------------------------------------------------------------===//
19 def CC_ARM_APCS : CallingConv<[
21 // Handles byval parameters.
22 CCIfByVal<CCPassByVal<4, 4>>,
24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
26 // Handle all vector types as either f64 or v2f64.
27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
33 CCIfType<[f32], CCBitConvertToType<i32>>,
34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
36 CCIfType<[i32], CCAssignToStack<4, 4>>,
37 CCIfType<[f64], CCAssignToStack<8, 4>>,
38 CCIfType<[v2f64], CCAssignToStack<16, 4>>
41 def RetCC_ARM_APCS : CallingConv<[
42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
43 CCIfType<[f32], CCBitConvertToType<i32>>,
45 // Handle all vector types as either f64 or v2f64.
46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
55 //===----------------------------------------------------------------------===//
56 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
57 //===----------------------------------------------------------------------===//
58 def FastCC_ARM_APCS : CallingConv<[
59 // Handle all vector types as either f64 or v2f64.
60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
63 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
64 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
65 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
66 S9, S10, S11, S12, S13, S14, S15]>>,
67 CCDelegateTo<CC_ARM_APCS>
70 def RetFastCC_ARM_APCS : CallingConv<[
71 // Handle all vector types as either f64 or v2f64.
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
76 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
77 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
78 S9, S10, S11, S12, S13, S14, S15]>>,
79 CCDelegateTo<RetCC_ARM_APCS>
83 //===----------------------------------------------------------------------===//
84 // ARM AAPCS (EABI) Calling Convention, common parts
85 //===----------------------------------------------------------------------===//
87 def CC_ARM_AAPCS_Common : CallingConv<[
89 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
91 // i64/f64 is passed in even pairs of GPRs
92 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
93 // (and the same is true for f64 if VFP is not enabled)
94 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
95 CCIfType<[i32], CCIf<"State.getNextStackOffset() == 0 &&"
96 "ArgFlags.getOrigAlign() != 8",
97 CCAssignToReg<[R0, R1, R2, R3]>>>,
99 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>,
100 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
101 CCIfType<[f64], CCAssignToStack<8, 8>>,
102 CCIfType<[v2f64], CCAssignToStack<16, 8>>
105 def RetCC_ARM_AAPCS_Common : CallingConv<[
106 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
107 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
108 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
111 //===----------------------------------------------------------------------===//
112 // ARM AAPCS (EABI) Calling Convention
113 //===----------------------------------------------------------------------===//
115 def CC_ARM_AAPCS : CallingConv<[
116 // Handle all vector types as either f64 or v2f64.
117 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
118 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
120 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
121 CCIfType<[f32], CCBitConvertToType<i32>>,
122 CCDelegateTo<CC_ARM_AAPCS_Common>
125 def RetCC_ARM_AAPCS : CallingConv<[
126 // Handle all vector types as either f64 or v2f64.
127 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
128 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
130 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
131 CCIfType<[f32], CCBitConvertToType<i32>>,
132 CCDelegateTo<RetCC_ARM_AAPCS_Common>
135 //===----------------------------------------------------------------------===//
136 // ARM AAPCS-VFP (EABI) Calling Convention
137 // Also used for FastCC (when VFP2 or later is available)
138 //===----------------------------------------------------------------------===//
140 def CC_ARM_AAPCS_VFP : CallingConv<[
141 // Handle all vector types as either f64 or v2f64.
142 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
143 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
145 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
146 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
147 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
148 S9, S10, S11, S12, S13, S14, S15]>>,
149 CCDelegateTo<CC_ARM_AAPCS_Common>
152 def RetCC_ARM_AAPCS_VFP : CallingConv<[
153 // Handle all vector types as either f64 or v2f64.
154 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
155 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
157 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
158 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
159 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
160 S9, S10, S11, S12, S13, S14, S15]>>,
161 CCDelegateTo<RetCC_ARM_AAPCS_Common>
164 //===----------------------------------------------------------------------===//
165 // Callee-saved register lists.
166 //===----------------------------------------------------------------------===//
168 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
169 (sequence "D%u", 15, 8))>;
171 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
172 // Also save R7-R4 first to match the stack frame fixed spill areas.
173 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;