1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
212 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
216 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
220 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
227 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
229 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
231 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
232 unsigned Op) const { return 0; }
233 unsigned getMsbOpValue(const MachineInstr &MI,
234 unsigned Op) const { return 0; }
235 unsigned getSsatBitPosValue(const MachineInstr &MI,
236 unsigned Op) const { return 0; }
237 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
239 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
242 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
245 // {12} = (U)nsigned (add == '1', sub == '0')
247 const MachineOperand &MO = MI.getOperand(Op);
248 const MachineOperand &MO1 = MI.getOperand(Op + 1);
250 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
253 unsigned Reg = getARMRegisterNumbering(MO.getReg());
254 int32_t Imm12 = MO1.getImm();
256 Binary = Imm12 & 0xfff;
259 Binary |= (Reg << 13);
263 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
267 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
269 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
273 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
275 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
277 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
279 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
281 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
283 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
285 // {12} = (U)nsigned (add == '1', sub == '0')
287 const MachineOperand &MO = MI.getOperand(Op);
288 const MachineOperand &MO1 = MI.getOperand(Op + 1);
290 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
293 unsigned Reg = getARMRegisterNumbering(MO.getReg());
294 int32_t Imm12 = MO1.getImm();
296 // Special value for #-0
297 if (Imm12 == INT32_MIN)
300 // Immediate is always encoded as positive. The 'U' bit controls add vs
308 uint32_t Binary = Imm12 & 0xfff;
311 Binary |= (Reg << 13);
314 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
317 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
320 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
322 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
324 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
326 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
329 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
330 /// machine operand requires relocation, record the relocation and return
332 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
335 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
337 unsigned getShiftOp(unsigned Imm) const ;
339 /// Routines that handle operands which add machine relocations which are
340 /// fixed up by the relocation stage.
341 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
342 bool MayNeedFarStub, bool Indirect,
343 intptr_t ACPV = 0) const;
344 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
345 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
346 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
347 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
348 intptr_t JTBase = 0) const;
352 char ARMCodeEmitter::ID = 0;
354 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
355 /// code to the specified MCE object.
356 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
357 JITCodeEmitter &JCE) {
358 return new ARMCodeEmitter(TM, JCE);
361 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
362 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
363 MF.getTarget().getRelocationModel() != Reloc::Static) &&
364 "JIT relocation model must be set to static or default!");
365 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
366 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
367 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
368 Subtarget = &TM.getSubtarget<ARMSubtarget>();
369 MCPEs = &MF.getConstantPool()->getConstants();
371 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
372 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
373 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
374 JTI->Initialize(MF, IsPIC);
375 MMI = &getAnalysis<MachineModuleInfo>();
376 MCE.setModuleInfo(MMI);
379 DEBUG(errs() << "JITTing function '"
380 << MF.getFunction()->getName() << "'\n");
381 MCE.startFunction(MF);
382 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
384 MCE.StartMachineBasicBlock(MBB);
385 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
389 } while (MCE.finishFunction(MF));
394 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
396 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
397 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
398 default: llvm_unreachable("Unknown shift opc!");
399 case ARM_AM::asr: return 2;
400 case ARM_AM::lsl: return 0;
401 case ARM_AM::lsr: return 1;
403 case ARM_AM::rrx: return 3;
408 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
409 /// machine operand requires relocation, record the relocation and return zero.
410 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
411 const MachineOperand &MO,
413 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
414 && "Relocation to this function should be for movt or movw");
417 return static_cast<unsigned>(MO.getImm());
418 else if (MO.isGlobal())
419 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
420 else if (MO.isSymbol())
421 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
423 emitMachineBasicBlock(MO.getMBB(), Reloc);
428 llvm_unreachable("Unsupported operand type for movw/movt");
433 /// getMachineOpValue - Return binary encoding of operand. If the machine
434 /// operand requires relocation, record the relocation and return zero.
435 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
436 const MachineOperand &MO) const {
438 return getARMRegisterNumbering(MO.getReg());
440 return static_cast<unsigned>(MO.getImm());
441 else if (MO.isGlobal())
442 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
443 else if (MO.isSymbol())
444 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
445 else if (MO.isCPI()) {
446 const TargetInstrDesc &TID = MI.getDesc();
447 // For VFP load, the immediate offset is multiplied by 4.
448 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
449 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
450 emitConstPoolAddress(MO.getIndex(), Reloc);
451 } else if (MO.isJTI())
452 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
454 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
456 llvm_unreachable("Unable to encode MachineOperand!");
460 /// emitGlobalAddress - Emit the specified address to the code stream.
462 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
463 bool MayNeedFarStub, bool Indirect,
464 intptr_t ACPV) const {
465 MachineRelocation MR = Indirect
466 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
467 const_cast<GlobalValue *>(GV),
468 ACPV, MayNeedFarStub)
469 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
470 const_cast<GlobalValue *>(GV), ACPV,
472 MCE.addRelocation(MR);
475 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
476 /// be emitted to the current location in the function, and allow it to be PC
478 void ARMCodeEmitter::
479 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
480 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
484 /// emitConstPoolAddress - Arrange for the address of an constant pool
485 /// to be emitted to the current location in the function, and allow it to be PC
487 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
488 // Tell JIT emitter we'll resolve the address.
489 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
490 Reloc, CPI, 0, true));
493 /// emitJumpTableAddress - Arrange for the address of a jump table to
494 /// be emitted to the current location in the function, and allow it to be PC
496 void ARMCodeEmitter::
497 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
498 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
499 Reloc, JTIndex, 0, true));
502 /// emitMachineBasicBlock - Emit the specified address basic block.
503 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
505 intptr_t JTBase) const {
506 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
510 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
511 DEBUG(errs() << " 0x";
512 errs().write_hex(Binary) << "\n");
513 MCE.emitWordLE(Binary);
516 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
517 DEBUG(errs() << " 0x";
518 errs().write_hex(Binary) << "\n");
519 MCE.emitDWordLE(Binary);
522 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
523 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
525 MCE.processDebugLoc(MI.getDebugLoc(), true);
527 ++NumEmitted; // Keep track of the # of mi's emitted
528 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
530 llvm_unreachable("Unhandled instruction encoding format!");
534 if (MI.getOpcode() == ARM::LEApcrelJT) {
535 // Materialize jumptable address.
536 emitLEApcrelJTInstruction(MI);
539 llvm_unreachable("Unhandled instruction encoding!");
542 emitPseudoInstruction(MI);
545 case ARMII::DPSoRegFrm:
546 emitDataProcessingInstruction(MI);
550 emitLoadStoreInstruction(MI);
552 case ARMII::LdMiscFrm:
553 case ARMII::StMiscFrm:
554 emitMiscLoadStoreInstruction(MI);
556 case ARMII::LdStMulFrm:
557 emitLoadStoreMultipleInstruction(MI);
560 emitMulFrmInstruction(MI);
563 emitExtendInstruction(MI);
565 case ARMII::ArithMiscFrm:
566 emitMiscArithInstruction(MI);
569 emitSaturateInstruction(MI);
572 emitBranchInstruction(MI);
574 case ARMII::BrMiscFrm:
575 emitMiscBranchInstruction(MI);
578 case ARMII::VFPUnaryFrm:
579 case ARMII::VFPBinaryFrm:
580 emitVFPArithInstruction(MI);
582 case ARMII::VFPConv1Frm:
583 case ARMII::VFPConv2Frm:
584 case ARMII::VFPConv3Frm:
585 case ARMII::VFPConv4Frm:
586 case ARMII::VFPConv5Frm:
587 emitVFPConversionInstruction(MI);
589 case ARMII::VFPLdStFrm:
590 emitVFPLoadStoreInstruction(MI);
592 case ARMII::VFPLdStMulFrm:
593 emitVFPLoadStoreMultipleInstruction(MI);
596 // NEON instructions.
597 case ARMII::NGetLnFrm:
598 case ARMII::NSetLnFrm:
599 emitNEONLaneInstruction(MI);
602 emitNEONDupInstruction(MI);
604 case ARMII::N1RegModImmFrm:
605 emitNEON1RegModImmInstruction(MI);
607 case ARMII::N2RegFrm:
608 emitNEON2RegInstruction(MI);
610 case ARMII::N3RegFrm:
611 emitNEON3RegInstruction(MI);
614 MCE.processDebugLoc(MI.getDebugLoc(), false);
617 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
618 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
619 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
620 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
622 // Remember the CONSTPOOL_ENTRY address for later relocation.
623 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
625 // Emit constpool island entry. In most cases, the actual values will be
626 // resolved and relocated after code emission.
627 if (MCPE.isMachineConstantPoolEntry()) {
628 ARMConstantPoolValue *ACPV =
629 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
631 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
632 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
634 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
635 const GlobalValue *GV = ACPV->getGV();
637 Reloc::Model RelocM = TM.getRelocationModel();
638 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
640 Subtarget->GVIsIndirectSymbol(GV, RelocM),
643 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
647 const Constant *CV = MCPE.Val.ConstVal;
650 errs() << " ** Constant pool #" << CPI << " @ "
651 << (void*)MCE.getCurrentPCValue() << " ";
652 if (const Function *F = dyn_cast<Function>(CV))
653 errs() << F->getName();
659 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
660 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
662 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
663 uint32_t Val = uint32_t(*CI->getValue().getRawData());
665 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
666 if (CFP->getType()->isFloatTy())
667 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
668 else if (CFP->getType()->isDoubleTy())
669 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
671 llvm_unreachable("Unable to handle this constantpool entry!");
674 llvm_unreachable("Unable to handle this constantpool entry!");
679 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
680 const MachineOperand &MO0 = MI.getOperand(0);
681 const MachineOperand &MO1 = MI.getOperand(1);
683 // Emit the 'movw' instruction.
684 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
686 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
688 // Set the conditional execution predicate.
689 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
692 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
694 // Encode imm16 as imm4:imm12
695 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
696 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
699 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
700 // Emit the 'movt' instruction.
701 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
703 // Set the conditional execution predicate.
704 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
707 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
709 // Encode imm16 as imm4:imm1, same as movw above.
710 Binary |= Hi16 & 0xFFF;
711 Binary |= ((Hi16 >> 12) & 0xF) << 16;
715 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
716 const MachineOperand &MO0 = MI.getOperand(0);
717 const MachineOperand &MO1 = MI.getOperand(1);
718 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
719 "Not a valid so_imm value!");
720 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
721 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
723 // Emit the 'mov' instruction.
724 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
726 // Set the conditional execution predicate.
727 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
730 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
733 // Set bit I(25) to identify this is the immediate form of <shifter_op>
734 Binary |= 1 << ARMII::I_BitShift;
735 Binary |= getMachineSoImmOpValue(V1);
738 // Now the 'orr' instruction.
739 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
741 // Set the conditional execution predicate.
742 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
745 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
748 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
751 // Set bit I(25) to identify this is the immediate form of <shifter_op>
752 Binary |= 1 << ARMII::I_BitShift;
753 Binary |= getMachineSoImmOpValue(V2);
757 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
758 // It's basically add r, pc, (LJTI - $+8)
760 const TargetInstrDesc &TID = MI.getDesc();
762 // Emit the 'add' instruction.
763 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
765 // Set the conditional execution predicate
766 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
768 // Encode S bit if MI modifies CPSR.
769 Binary |= getAddrModeSBit(MI, TID);
772 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
774 // Encode Rn which is PC.
775 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
777 // Encode the displacement.
778 Binary |= 1 << ARMII::I_BitShift;
779 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
784 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
785 unsigned Opcode = MI.getDesc().Opcode;
787 // Part of binary is determined by TableGn.
788 unsigned Binary = getBinaryCodeForInstr(MI);
790 // Set the conditional execution predicate
791 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
793 // Encode S bit if MI modifies CPSR.
794 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
795 Binary |= 1 << ARMII::S_BitShift;
797 // Encode register def if there is one.
798 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
800 // Encode the shift operation.
807 case ARM::MOVsrl_flag:
809 Binary |= (0x2 << 4) | (1 << 7);
811 case ARM::MOVsra_flag:
813 Binary |= (0x4 << 4) | (1 << 7);
817 // Encode register Rm.
818 Binary |= getMachineOpValue(MI, 1);
823 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
824 DEBUG(errs() << " ** LPC" << LabelID << " @ "
825 << (void*)MCE.getCurrentPCValue() << '\n');
826 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
829 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
830 unsigned Opcode = MI.getDesc().Opcode;
833 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
835 case ARM::BMOVPCRX_CALL:
837 case ARM::BMOVPCRXr9_CALL: {
838 // First emit mov lr, pc
839 unsigned Binary = 0x01a0e00f;
840 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
843 // and then emit the branch.
844 emitMiscBranchInstruction(MI);
847 case TargetOpcode::INLINEASM: {
848 // We allow inline assembler nodes with empty bodies - they can
849 // implicitly define registers, which is ok for JIT.
850 if (MI.getOperand(0).getSymbolName()[0]) {
851 report_fatal_error("JIT does not support inline asm!");
855 case TargetOpcode::PROLOG_LABEL:
856 case TargetOpcode::EH_LABEL:
857 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
859 case TargetOpcode::IMPLICIT_DEF:
860 case TargetOpcode::KILL:
863 case ARM::CONSTPOOL_ENTRY:
864 emitConstPoolInstruction(MI);
867 // Remember of the address of the PC label for relocation later.
868 addPCLabel(MI.getOperand(2).getImm());
869 // PICADD is just an add instruction that implicitly read pc.
870 emitDataProcessingInstruction(MI, 0, ARM::PC);
877 // Remember of the address of the PC label for relocation later.
878 addPCLabel(MI.getOperand(2).getImm());
879 // These are just load / store instructions that implicitly read pc.
880 emitLoadStoreInstruction(MI, 0, ARM::PC);
887 // Remember of the address of the PC label for relocation later.
888 addPCLabel(MI.getOperand(2).getImm());
889 // These are just load / store instructions that implicitly read pc.
890 emitMiscLoadStoreInstruction(MI, ARM::PC);
895 // Two instructions to materialize a constant.
896 if (Subtarget->hasV6T2Ops())
897 emitMOVi32immInstruction(MI);
899 emitMOVi2piecesInstruction(MI);
902 case ARM::LEApcrelJT:
903 // Materialize jumptable address.
904 emitLEApcrelJTInstruction(MI);
907 case ARM::MOVsrl_flag:
908 case ARM::MOVsra_flag:
909 emitPseudoMoveInstruction(MI);
914 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
915 const TargetInstrDesc &TID,
916 const MachineOperand &MO,
918 unsigned Binary = getMachineOpValue(MI, MO);
920 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
921 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
922 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
924 // Encode the shift opcode.
926 unsigned Rs = MO1.getReg();
928 // Set shift operand (bit[7:4]).
933 // RRX - 0110 and bit[11:8] clear.
935 default: llvm_unreachable("Unknown shift opc!");
936 case ARM_AM::lsl: SBits = 0x1; break;
937 case ARM_AM::lsr: SBits = 0x3; break;
938 case ARM_AM::asr: SBits = 0x5; break;
939 case ARM_AM::ror: SBits = 0x7; break;
940 case ARM_AM::rrx: SBits = 0x6; break;
943 // Set shift operand (bit[6:4]).
949 default: llvm_unreachable("Unknown shift opc!");
950 case ARM_AM::lsl: SBits = 0x0; break;
951 case ARM_AM::lsr: SBits = 0x2; break;
952 case ARM_AM::asr: SBits = 0x4; break;
953 case ARM_AM::ror: SBits = 0x6; break;
956 Binary |= SBits << 4;
957 if (SOpc == ARM_AM::rrx)
960 // Encode the shift operation Rs or shift_imm (except rrx).
962 // Encode Rs bit[11:8].
963 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
964 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
967 // Encode shift_imm bit[11:7].
968 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
971 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
972 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
973 assert(SoImmVal != -1 && "Not a valid so_imm value!");
975 // Encode rotate_imm.
976 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
977 << ARMII::SoRotImmShift;
980 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
984 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
985 const TargetInstrDesc &TID) const {
986 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){
987 const MachineOperand &MO = MI.getOperand(i-1);
988 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
989 return 1 << ARMII::S_BitShift;
994 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
996 unsigned ImplicitRn) {
997 const TargetInstrDesc &TID = MI.getDesc();
999 // Part of binary is determined by TableGn.
1000 unsigned Binary = getBinaryCodeForInstr(MI);
1002 // Set the conditional execution predicate
1003 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1005 // Encode S bit if MI modifies CPSR.
1006 Binary |= getAddrModeSBit(MI, TID);
1008 // Encode register def if there is one.
1009 unsigned NumDefs = TID.getNumDefs();
1012 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1013 else if (ImplicitRd)
1014 // Special handling for implicit use (e.g. PC).
1015 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1017 if (TID.Opcode == ARM::MOVi16) {
1018 // Get immediate from MI.
1019 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1020 ARM::reloc_arm_movw);
1021 // Encode imm which is the same as in emitMOVi32immInstruction().
1022 Binary |= Lo16 & 0xFFF;
1023 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1026 } else if(TID.Opcode == ARM::MOVTi16) {
1027 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1028 ARM::reloc_arm_movt) >> 16);
1029 Binary |= Hi16 & 0xFFF;
1030 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1033 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1034 uint32_t v = ~MI.getOperand(2).getImm();
1035 int32_t lsb = CountTrailingZeros_32(v);
1036 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1037 // Instr{20-16} = msb, Instr{11-7} = lsb
1038 Binary |= (msb & 0x1F) << 16;
1039 Binary |= (lsb & 0x1F) << 7;
1042 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1043 // Encode Rn in Instr{0-3}
1044 Binary |= getMachineOpValue(MI, OpIdx++);
1046 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1047 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1049 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1050 Binary |= (widthm1 & 0x1F) << 16;
1051 Binary |= (lsb & 0x1F) << 7;
1056 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1057 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1060 // Encode first non-shifter register operand if there is one.
1061 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1064 // Special handling for implicit use (e.g. PC).
1065 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1067 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1072 // Encode shifter operand.
1073 const MachineOperand &MO = MI.getOperand(OpIdx);
1074 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1076 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1081 // Encode register Rm.
1082 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1087 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1092 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1093 unsigned ImplicitRd,
1094 unsigned ImplicitRn) {
1095 const TargetInstrDesc &TID = MI.getDesc();
1096 unsigned Form = TID.TSFlags & ARMII::FormMask;
1097 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1099 // Part of binary is determined by TableGn.
1100 unsigned Binary = getBinaryCodeForInstr(MI);
1102 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1103 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1104 MI.getOpcode() == ARM::STRi12) {
1109 // Set the conditional execution predicate
1110 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1114 // Operand 0 of a pre- and post-indexed store is the address base
1115 // writeback. Skip it.
1116 bool Skipped = false;
1117 if (IsPrePost && Form == ARMII::StFrm) {
1122 // Set first operand
1124 // Special handling for implicit use (e.g. PC).
1125 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1127 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1129 // Set second operand
1131 // Special handling for implicit use (e.g. PC).
1132 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1134 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1136 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1137 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1140 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1141 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1142 ? 0 : MI.getOperand(OpIdx+1).getImm();
1144 // Set bit U(23) according to sign of immed value (positive or negative).
1145 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1147 if (!MO2.getReg()) { // is immediate
1148 if (ARM_AM::getAM2Offset(AM2Opc))
1149 // Set the value of offset_12 field
1150 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1155 // Set bit I(25), because this is not in immediate encoding.
1156 Binary |= 1 << ARMII::I_BitShift;
1157 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1158 // Set bit[3:0] to the corresponding Rm register
1159 Binary |= getARMRegisterNumbering(MO2.getReg());
1161 // If this instr is in scaled register offset/index instruction, set
1162 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1163 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1164 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1165 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1171 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1172 unsigned ImplicitRn) {
1173 const TargetInstrDesc &TID = MI.getDesc();
1174 unsigned Form = TID.TSFlags & ARMII::FormMask;
1175 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1177 // Part of binary is determined by TableGn.
1178 unsigned Binary = getBinaryCodeForInstr(MI);
1180 // Set the conditional execution predicate
1181 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1185 // Operand 0 of a pre- and post-indexed store is the address base
1186 // writeback. Skip it.
1187 bool Skipped = false;
1188 if (IsPrePost && Form == ARMII::StMiscFrm) {
1193 // Set first operand
1194 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1196 // Skip LDRD and STRD's second operand.
1197 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1200 // Set second operand
1202 // Special handling for implicit use (e.g. PC).
1203 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1205 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1207 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1208 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1211 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1212 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1213 ? 0 : MI.getOperand(OpIdx+1).getImm();
1215 // Set bit U(23) according to sign of immed value (positive or negative)
1216 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1219 // If this instr is in register offset/index encoding, set bit[3:0]
1220 // to the corresponding Rm register.
1222 Binary |= getARMRegisterNumbering(MO2.getReg());
1227 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1228 Binary |= 1 << ARMII::AM3_I_BitShift;
1229 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1231 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1232 Binary |= (ImmOffs & 0xF); // immedL
1238 static unsigned getAddrModeUPBits(unsigned Mode) {
1239 unsigned Binary = 0;
1241 // Set addressing mode by modifying bits U(23) and P(24)
1242 // IA - Increment after - bit U = 1 and bit P = 0
1243 // IB - Increment before - bit U = 1 and bit P = 1
1244 // DA - Decrement after - bit U = 0 and bit P = 0
1245 // DB - Decrement before - bit U = 0 and bit P = 1
1247 default: llvm_unreachable("Unknown addressing sub-mode!");
1248 case ARM_AM::da: break;
1249 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1250 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1251 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1257 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1258 const TargetInstrDesc &TID = MI.getDesc();
1259 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1261 // Part of binary is determined by TableGn.
1262 unsigned Binary = getBinaryCodeForInstr(MI);
1264 // Set the conditional execution predicate
1265 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1267 // Skip operand 0 of an instruction with base register update.
1272 // Set base address operand
1273 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1275 // Set addressing mode by modifying bits U(23) and P(24)
1276 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1277 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1281 Binary |= 0x1 << ARMII::W_BitShift;
1284 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1285 const MachineOperand &MO = MI.getOperand(i);
1286 if (!MO.isReg() || MO.isImplicit())
1288 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1289 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1291 Binary |= 0x1 << RegNum;
1297 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1298 const TargetInstrDesc &TID = MI.getDesc();
1300 // Part of binary is determined by TableGn.
1301 unsigned Binary = getBinaryCodeForInstr(MI);
1303 // Set the conditional execution predicate
1304 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1306 // Encode S bit if MI modifies CPSR.
1307 Binary |= getAddrModeSBit(MI, TID);
1309 // 32x32->64bit operations have two destination registers. The number
1310 // of register definitions will tell us if that's what we're dealing with.
1312 if (TID.getNumDefs() == 2)
1313 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1316 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1319 Binary |= getMachineOpValue(MI, OpIdx++);
1322 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1324 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1325 // it as Rn (for multiply, that's in the same offset as RdLo.
1326 if (TID.getNumOperands() > OpIdx &&
1327 !TID.OpInfo[OpIdx].isPredicate() &&
1328 !TID.OpInfo[OpIdx].isOptionalDef())
1329 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1334 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1335 const TargetInstrDesc &TID = MI.getDesc();
1337 // Part of binary is determined by TableGn.
1338 unsigned Binary = getBinaryCodeForInstr(MI);
1340 // Set the conditional execution predicate
1341 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1346 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1348 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1349 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1351 // Two register operand form.
1353 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1356 Binary |= getMachineOpValue(MI, MO2);
1359 Binary |= getMachineOpValue(MI, MO1);
1362 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1363 if (MI.getOperand(OpIdx).isImm() &&
1364 !TID.OpInfo[OpIdx].isPredicate() &&
1365 !TID.OpInfo[OpIdx].isOptionalDef())
1366 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1371 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1372 const TargetInstrDesc &TID = MI.getDesc();
1374 // Part of binary is determined by TableGn.
1375 unsigned Binary = getBinaryCodeForInstr(MI);
1377 // Set the conditional execution predicate
1378 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1380 // PKH instructions are finished at this point
1381 if (TID.Opcode == ARM::PKHBT || TID.Opcode == ARM::PKHTB) {
1389 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1391 const MachineOperand &MO = MI.getOperand(OpIdx++);
1392 if (OpIdx == TID.getNumOperands() ||
1393 TID.OpInfo[OpIdx].isPredicate() ||
1394 TID.OpInfo[OpIdx].isOptionalDef()) {
1395 // Encode Rm and it's done.
1396 Binary |= getMachineOpValue(MI, MO);
1402 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1405 Binary |= getMachineOpValue(MI, OpIdx++);
1407 // Encode shift_imm.
1408 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1409 if (TID.Opcode == ARM::PKHTB) {
1410 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1414 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1415 Binary |= ShiftAmt << ARMII::ShiftShift;
1420 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1421 const TargetInstrDesc &TID = MI.getDesc();
1423 // Part of binary is determined by TableGen.
1424 unsigned Binary = getBinaryCodeForInstr(MI);
1426 // Set the conditional execution predicate
1427 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1430 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1432 // Encode saturate bit position.
1433 unsigned Pos = MI.getOperand(1).getImm();
1434 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1436 assert((Pos < 16 || (Pos < 32 &&
1437 TID.Opcode != ARM::SSAT16 &&
1438 TID.Opcode != ARM::USAT16)) &&
1439 "saturate bit position out of range");
1440 Binary |= Pos << 16;
1443 Binary |= getMachineOpValue(MI, 2);
1445 // Encode shift_imm.
1446 if (TID.getNumOperands() == 4) {
1447 unsigned ShiftOp = MI.getOperand(3).getImm();
1448 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1449 if (Opc == ARM_AM::asr)
1451 unsigned ShiftAmt = MI.getOperand(3).getImm();
1452 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1454 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1455 Binary |= ShiftAmt << ARMII::ShiftShift;
1461 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1462 const TargetInstrDesc &TID = MI.getDesc();
1464 if (TID.Opcode == ARM::TPsoft) {
1465 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1468 // Part of binary is determined by TableGn.
1469 unsigned Binary = getBinaryCodeForInstr(MI);
1471 // Set the conditional execution predicate
1472 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1474 // Set signed_immed_24 field
1475 Binary |= getMachineOpValue(MI, 0);
1480 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1481 // Remember the base address of the inline jump table.
1482 uintptr_t JTBase = MCE.getCurrentPCValue();
1483 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1484 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1487 // Now emit the jump table entries.
1488 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1489 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1491 // DestBB address - JT base.
1492 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1494 // Absolute DestBB address.
1495 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1500 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1501 const TargetInstrDesc &TID = MI.getDesc();
1503 // Handle jump tables.
1504 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1505 // First emit a ldr pc, [] instruction.
1506 emitDataProcessingInstruction(MI, ARM::PC);
1508 // Then emit the inline jump table.
1510 (TID.Opcode == ARM::BR_JTr)
1511 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1512 emitInlineJumpTable(JTIndex);
1514 } else if (TID.Opcode == ARM::BR_JTm) {
1515 // First emit a ldr pc, [] instruction.
1516 emitLoadStoreInstruction(MI, ARM::PC);
1518 // Then emit the inline jump table.
1519 emitInlineJumpTable(MI.getOperand(3).getIndex());
1523 // Part of binary is determined by TableGn.
1524 unsigned Binary = getBinaryCodeForInstr(MI);
1526 // Set the conditional execution predicate
1527 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1529 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1530 // The return register is LR.
1531 Binary |= getARMRegisterNumbering(ARM::LR);
1533 // otherwise, set the return register
1534 Binary |= getMachineOpValue(MI, 0);
1539 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1540 unsigned RegD = MI.getOperand(OpIdx).getReg();
1541 unsigned Binary = 0;
1542 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1543 RegD = getARMRegisterNumbering(RegD);
1545 Binary |= RegD << ARMII::RegRdShift;
1547 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1548 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1553 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1554 unsigned RegN = MI.getOperand(OpIdx).getReg();
1555 unsigned Binary = 0;
1556 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1557 RegN = getARMRegisterNumbering(RegN);
1559 Binary |= RegN << ARMII::RegRnShift;
1561 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1562 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1567 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1568 unsigned RegM = MI.getOperand(OpIdx).getReg();
1569 unsigned Binary = 0;
1570 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1571 RegM = getARMRegisterNumbering(RegM);
1575 Binary |= ((RegM & 0x1E) >> 1);
1576 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1581 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1582 const TargetInstrDesc &TID = MI.getDesc();
1584 // Part of binary is determined by TableGn.
1585 unsigned Binary = getBinaryCodeForInstr(MI);
1587 // Set the conditional execution predicate
1588 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1591 assert((Binary & ARMII::D_BitShift) == 0 &&
1592 (Binary & ARMII::N_BitShift) == 0 &&
1593 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1596 Binary |= encodeVFPRd(MI, OpIdx++);
1598 // If this is a two-address operand, skip it, e.g. FMACD.
1599 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1603 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1604 Binary |= encodeVFPRn(MI, OpIdx++);
1606 if (OpIdx == TID.getNumOperands() ||
1607 TID.OpInfo[OpIdx].isPredicate() ||
1608 TID.OpInfo[OpIdx].isOptionalDef()) {
1609 // FCMPEZD etc. has only one operand.
1615 Binary |= encodeVFPRm(MI, OpIdx);
1620 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1621 const TargetInstrDesc &TID = MI.getDesc();
1622 unsigned Form = TID.TSFlags & ARMII::FormMask;
1624 // Part of binary is determined by TableGn.
1625 unsigned Binary = getBinaryCodeForInstr(MI);
1627 // Set the conditional execution predicate
1628 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1632 case ARMII::VFPConv1Frm:
1633 case ARMII::VFPConv2Frm:
1634 case ARMII::VFPConv3Frm:
1636 Binary |= encodeVFPRd(MI, 0);
1638 case ARMII::VFPConv4Frm:
1640 Binary |= encodeVFPRn(MI, 0);
1642 case ARMII::VFPConv5Frm:
1644 Binary |= encodeVFPRm(MI, 0);
1650 case ARMII::VFPConv1Frm:
1652 Binary |= encodeVFPRm(MI, 1);
1654 case ARMII::VFPConv2Frm:
1655 case ARMII::VFPConv3Frm:
1657 Binary |= encodeVFPRn(MI, 1);
1659 case ARMII::VFPConv4Frm:
1660 case ARMII::VFPConv5Frm:
1662 Binary |= encodeVFPRd(MI, 1);
1666 if (Form == ARMII::VFPConv5Frm)
1668 Binary |= encodeVFPRn(MI, 2);
1669 else if (Form == ARMII::VFPConv3Frm)
1671 Binary |= encodeVFPRm(MI, 2);
1676 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1677 // Part of binary is determined by TableGn.
1678 unsigned Binary = getBinaryCodeForInstr(MI);
1680 // Set the conditional execution predicate
1681 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1686 Binary |= encodeVFPRd(MI, OpIdx++);
1688 // Encode address base.
1689 const MachineOperand &Base = MI.getOperand(OpIdx++);
1690 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1692 // If there is a non-zero immediate offset, encode it.
1694 const MachineOperand &Offset = MI.getOperand(OpIdx);
1695 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1696 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1697 Binary |= 1 << ARMII::U_BitShift;
1704 // If immediate offset is omitted, default to +0.
1705 Binary |= 1 << ARMII::U_BitShift;
1711 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1712 const TargetInstrDesc &TID = MI.getDesc();
1713 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1715 // Part of binary is determined by TableGn.
1716 unsigned Binary = getBinaryCodeForInstr(MI);
1718 // Set the conditional execution predicate
1719 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1721 // Skip operand 0 of an instruction with base register update.
1726 // Set base address operand
1727 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1729 // Set addressing mode by modifying bits U(23) and P(24)
1730 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1731 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1735 Binary |= 0x1 << ARMII::W_BitShift;
1737 // First register is encoded in Dd.
1738 Binary |= encodeVFPRd(MI, OpIdx+2);
1740 // Count the number of registers.
1741 unsigned NumRegs = 1;
1742 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1743 const MachineOperand &MO = MI.getOperand(i);
1744 if (!MO.isReg() || MO.isImplicit())
1748 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1749 // Otherwise, it will be 0, in the case of 32-bit registers.
1751 Binary |= NumRegs * 2;
1758 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1759 unsigned RegD = MI.getOperand(OpIdx).getReg();
1760 unsigned Binary = 0;
1761 RegD = getARMRegisterNumbering(RegD);
1762 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1763 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1767 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1768 unsigned RegN = MI.getOperand(OpIdx).getReg();
1769 unsigned Binary = 0;
1770 RegN = getARMRegisterNumbering(RegN);
1771 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1772 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1776 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1777 unsigned RegM = MI.getOperand(OpIdx).getReg();
1778 unsigned Binary = 0;
1779 RegM = getARMRegisterNumbering(RegM);
1780 Binary |= (RegM & 0xf);
1781 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1785 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1786 /// data-processing instruction to the corresponding Thumb encoding.
1787 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1788 assert((Binary & 0xfe000000) == 0xf2000000 &&
1789 "not an ARM NEON data-processing instruction");
1790 unsigned UBit = (Binary >> 24) & 1;
1791 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1794 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1795 unsigned Binary = getBinaryCodeForInstr(MI);
1797 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1798 const TargetInstrDesc &TID = MI.getDesc();
1799 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1803 } else { // ARMII::NSetLnFrm
1809 // Set the conditional execution predicate
1810 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1812 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1813 RegT = getARMRegisterNumbering(RegT);
1814 Binary |= (RegT << ARMII::RegRdShift);
1815 Binary |= encodeNEONRn(MI, RegNOpIdx);
1818 if ((Binary & (1 << 22)) != 0)
1819 LaneShift = 0; // 8-bit elements
1820 else if ((Binary & (1 << 5)) != 0)
1821 LaneShift = 1; // 16-bit elements
1823 LaneShift = 2; // 32-bit elements
1825 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1826 unsigned Opc1 = Lane >> 2;
1827 unsigned Opc2 = Lane & 3;
1828 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1829 Binary |= (Opc1 << 21);
1830 Binary |= (Opc2 << 5);
1835 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1836 unsigned Binary = getBinaryCodeForInstr(MI);
1838 // Set the conditional execution predicate
1839 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1841 unsigned RegT = MI.getOperand(1).getReg();
1842 RegT = getARMRegisterNumbering(RegT);
1843 Binary |= (RegT << ARMII::RegRdShift);
1844 Binary |= encodeNEONRn(MI, 0);
1848 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1849 unsigned Binary = getBinaryCodeForInstr(MI);
1850 // Destination register is encoded in Dd.
1851 Binary |= encodeNEONRd(MI, 0);
1852 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1853 unsigned Imm = MI.getOperand(1).getImm();
1854 unsigned Op = (Imm >> 12) & 1;
1855 unsigned Cmode = (Imm >> 8) & 0xf;
1856 unsigned I = (Imm >> 7) & 1;
1857 unsigned Imm3 = (Imm >> 4) & 0x7;
1858 unsigned Imm4 = Imm & 0xf;
1859 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1861 Binary = convertNEONDataProcToThumb(Binary);
1865 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1866 const TargetInstrDesc &TID = MI.getDesc();
1867 unsigned Binary = getBinaryCodeForInstr(MI);
1868 // Destination register is encoded in Dd; source register in Dm.
1870 Binary |= encodeNEONRd(MI, OpIdx++);
1871 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1873 Binary |= encodeNEONRm(MI, OpIdx);
1875 Binary = convertNEONDataProcToThumb(Binary);
1876 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1880 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1881 const TargetInstrDesc &TID = MI.getDesc();
1882 unsigned Binary = getBinaryCodeForInstr(MI);
1883 // Destination register is encoded in Dd; source registers in Dn and Dm.
1885 Binary |= encodeNEONRd(MI, OpIdx++);
1886 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1888 Binary |= encodeNEONRn(MI, OpIdx++);
1889 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1891 Binary |= encodeNEONRm(MI, OpIdx);
1893 Binary = convertNEONDataProcToThumb(Binary);
1894 // FIXME: This does not handle VMOVDneon or VMOVQ.
1898 #include "ARMGenCodeEmitter.inc"