1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class Emitter : public MachineFunctionPass, public ARMCodeEmitter {
60 const ARMInstrInfo *II;
62 const ARMSubtarget *Subtarget;
65 const std::vector<MachineConstantPoolEntry> *MCPEs;
66 const std::vector<MachineJumpTableEntry> *MJTEs;
69 void getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addRequired<MachineModuleInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
76 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
77 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
78 MCE(mce), MCPEs(0), MJTEs(0),
79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
80 Emitter(TargetMachine &tm, CodeEmitter &mce,
81 const ARMInstrInfo &ii, const TargetData &td)
82 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
83 MCE(mce), MCPEs(0), MJTEs(0),
84 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
86 bool runOnMachineFunction(MachineFunction &MF);
88 virtual const char *getPassName() const {
89 return "ARM Machine Code Emitter";
92 void emitInstruction(const MachineInstr &MI);
96 void emitWordLE(unsigned Binary);
98 void emitDWordLE(uint64_t Binary);
100 void emitConstPoolInstruction(const MachineInstr &MI);
102 void emitMOVi2piecesInstruction(const MachineInstr &MI);
104 void emitLEApcrelJTInstruction(const MachineInstr &MI);
106 void emitPseudoMoveInstruction(const MachineInstr &MI);
108 void addPCLabel(unsigned LabelID);
110 void emitPseudoInstruction(const MachineInstr &MI);
112 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
113 const TargetInstrDesc &TID,
114 const MachineOperand &MO,
117 unsigned getMachineSoImmOpValue(unsigned SoImm);
119 unsigned getAddrModeSBit(const MachineInstr &MI,
120 const TargetInstrDesc &TID) const;
122 void emitDataProcessingInstruction(const MachineInstr &MI,
123 unsigned ImplicitRd = 0,
124 unsigned ImplicitRn = 0);
126 void emitLoadStoreInstruction(const MachineInstr &MI,
127 unsigned ImplicitRd = 0,
128 unsigned ImplicitRn = 0);
130 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
131 unsigned ImplicitRn = 0);
133 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
135 void emitMulFrmInstruction(const MachineInstr &MI);
137 void emitExtendInstruction(const MachineInstr &MI);
139 void emitMiscArithInstruction(const MachineInstr &MI);
141 void emitBranchInstruction(const MachineInstr &MI);
143 void emitInlineJumpTable(unsigned JTIndex);
145 void emitMiscBranchInstruction(const MachineInstr &MI);
147 void emitVFPArithInstruction(const MachineInstr &MI);
149 void emitVFPConversionInstruction(const MachineInstr &MI);
151 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
153 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
155 void emitMiscInstruction(const MachineInstr &MI);
157 /// getMachineOpValue - Return binary encoding of operand. If the machine
158 /// operand requires relocation, record the relocation and return zero.
159 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
160 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
161 return getMachineOpValue(MI, MI.getOperand(OpIdx));
164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166 unsigned getShiftOp(unsigned Imm) const ;
168 /// Routines that handle operands which add machine relocations which are
169 /// fixed up by the relocation stage.
170 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
171 bool MayNeedFarStub, bool Indirect,
173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177 intptr_t JTBase = 0);
179 template <class CodeEmitter>
180 char Emitter<CodeEmitter>::ID = 0;
183 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
184 /// to the specified MCE object.
186 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
187 MachineCodeEmitter &MCE) {
188 return new Emitter<MachineCodeEmitter>(TM, MCE);
190 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
191 JITCodeEmitter &JCE) {
192 return new Emitter<JITCodeEmitter>(TM, JCE);
194 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
195 ObjectCodeEmitter &OCE) {
196 return new Emitter<ObjectCodeEmitter>(TM, OCE);
199 template<class CodeEmitter>
200 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
201 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
202 MF.getTarget().getRelocationModel() != Reloc::Static) &&
203 "JIT relocation model must be set to static or default!");
204 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
205 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
206 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
207 Subtarget = &TM.getSubtarget<ARMSubtarget>();
208 MCPEs = &MF.getConstantPool()->getConstants();
209 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
210 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
211 JTI->Initialize(MF, IsPIC);
212 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
215 DEBUG(errs() << "JITTing function '"
216 << MF.getFunction()->getName() << "'\n");
217 MCE.startFunction(MF);
218 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
220 MCE.StartMachineBasicBlock(MBB);
221 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
225 } while (MCE.finishFunction(MF));
230 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
232 template<class CodeEmitter>
233 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
234 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
235 default: llvm_unreachable("Unknown shift opc!");
236 case ARM_AM::asr: return 2;
237 case ARM_AM::lsl: return 0;
238 case ARM_AM::lsr: return 1;
240 case ARM_AM::rrx: return 3;
245 /// getMachineOpValue - Return binary encoding of operand. If the machine
246 /// operand requires relocation, record the relocation and return zero.
247 template<class CodeEmitter>
248 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
249 const MachineOperand &MO) {
251 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
253 return static_cast<unsigned>(MO.getImm());
254 else if (MO.isGlobal())
255 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
256 else if (MO.isSymbol())
257 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
258 else if (MO.isCPI()) {
259 const TargetInstrDesc &TID = MI.getDesc();
260 // For VFP load, the immediate offset is multiplied by 4.
261 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
262 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
263 emitConstPoolAddress(MO.getIndex(), Reloc);
264 } else if (MO.isJTI())
265 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
267 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
277 /// emitGlobalAddress - Emit the specified address to the code stream.
279 template<class CodeEmitter>
280 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
281 bool MayNeedFarStub, bool Indirect,
283 MachineRelocation MR = Indirect
284 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
285 GV, ACPV, MayNeedFarStub)
286 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
287 GV, ACPV, MayNeedFarStub);
288 MCE.addRelocation(MR);
291 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
292 /// be emitted to the current location in the function, and allow it to be PC
294 template<class CodeEmitter>
295 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
297 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
301 /// emitConstPoolAddress - Arrange for the address of an constant pool
302 /// to be emitted to the current location in the function, and allow it to be PC
304 template<class CodeEmitter>
305 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
307 // Tell JIT emitter we'll resolve the address.
308 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
309 Reloc, CPI, 0, true));
312 /// emitJumpTableAddress - Arrange for the address of a jump table to
313 /// be emitted to the current location in the function, and allow it to be PC
315 template<class CodeEmitter>
316 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
318 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
319 Reloc, JTIndex, 0, true));
322 /// emitMachineBasicBlock - Emit the specified address basic block.
323 template<class CodeEmitter>
324 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
325 unsigned Reloc, intptr_t JTBase) {
326 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
330 template<class CodeEmitter>
331 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
332 DEBUG(errs() << " 0x";
333 errs().write_hex(Binary) << "\n");
334 MCE.emitWordLE(Binary);
337 template<class CodeEmitter>
338 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
339 DEBUG(errs() << " 0x";
340 errs().write_hex(Binary) << "\n");
341 MCE.emitDWordLE(Binary);
344 template<class CodeEmitter>
345 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
346 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
348 MCE.processDebugLoc(MI.getDebugLoc(), true);
350 NumEmitted++; // Keep track of the # of mi's emitted
351 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
353 llvm_unreachable("Unhandled instruction encoding format!");
357 emitPseudoInstruction(MI);
360 case ARMII::DPSoRegFrm:
361 emitDataProcessingInstruction(MI);
365 emitLoadStoreInstruction(MI);
367 case ARMII::LdMiscFrm:
368 case ARMII::StMiscFrm:
369 emitMiscLoadStoreInstruction(MI);
371 case ARMII::LdStMulFrm:
372 emitLoadStoreMultipleInstruction(MI);
375 emitMulFrmInstruction(MI);
378 emitExtendInstruction(MI);
380 case ARMII::ArithMiscFrm:
381 emitMiscArithInstruction(MI);
384 emitBranchInstruction(MI);
386 case ARMII::BrMiscFrm:
387 emitMiscBranchInstruction(MI);
390 case ARMII::VFPUnaryFrm:
391 case ARMII::VFPBinaryFrm:
392 emitVFPArithInstruction(MI);
394 case ARMII::VFPConv1Frm:
395 case ARMII::VFPConv2Frm:
396 case ARMII::VFPConv3Frm:
397 case ARMII::VFPConv4Frm:
398 case ARMII::VFPConv5Frm:
399 emitVFPConversionInstruction(MI);
401 case ARMII::VFPLdStFrm:
402 emitVFPLoadStoreInstruction(MI);
404 case ARMII::VFPLdStMulFrm:
405 emitVFPLoadStoreMultipleInstruction(MI);
407 case ARMII::VFPMiscFrm:
408 emitMiscInstruction(MI);
411 MCE.processDebugLoc(MI.getDebugLoc(), false);
414 template<class CodeEmitter>
415 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
416 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
417 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
418 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
420 // Remember the CONSTPOOL_ENTRY address for later relocation.
421 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
423 // Emit constpool island entry. In most cases, the actual values will be
424 // resolved and relocated after code emission.
425 if (MCPE.isMachineConstantPoolEntry()) {
426 ARMConstantPoolValue *ACPV =
427 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
429 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
430 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
432 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
433 GlobalValue *GV = ACPV->getGV();
435 Reloc::Model RelocM = TM.getRelocationModel();
436 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
438 Subtarget->GVIsIndirectSymbol(GV, RelocM),
441 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
445 Constant *CV = MCPE.Val.ConstVal;
448 errs() << " ** Constant pool #" << CPI << " @ "
449 << (void*)MCE.getCurrentPCValue() << " ";
450 if (const Function *F = dyn_cast<Function>(CV))
451 errs() << F->getName();
457 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
458 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
460 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
461 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
463 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
464 if (CFP->getType()->isFloatTy())
465 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
466 else if (CFP->getType()->isDoubleTy())
467 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
469 llvm_unreachable("Unable to handle this constantpool entry!");
472 llvm_unreachable("Unable to handle this constantpool entry!");
477 template<class CodeEmitter>
478 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
479 const MachineOperand &MO0 = MI.getOperand(0);
480 const MachineOperand &MO1 = MI.getOperand(1);
481 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
482 "Not a valid so_imm value!");
483 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
484 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
486 // Emit the 'mov' instruction.
487 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
489 // Set the conditional execution predicate.
490 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
493 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
496 // Set bit I(25) to identify this is the immediate form of <shifter_op>
497 Binary |= 1 << ARMII::I_BitShift;
498 Binary |= getMachineSoImmOpValue(V1);
501 // Now the 'orr' instruction.
502 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
504 // Set the conditional execution predicate.
505 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
508 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
511 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
514 // Set bit I(25) to identify this is the immediate form of <shifter_op>
515 Binary |= 1 << ARMII::I_BitShift;
516 Binary |= getMachineSoImmOpValue(V2);
520 template<class CodeEmitter>
521 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
522 // It's basically add r, pc, (LJTI - $+8)
524 const TargetInstrDesc &TID = MI.getDesc();
526 // Emit the 'add' instruction.
527 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
529 // Set the conditional execution predicate
530 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
532 // Encode S bit if MI modifies CPSR.
533 Binary |= getAddrModeSBit(MI, TID);
536 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
538 // Encode Rn which is PC.
539 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
541 // Encode the displacement.
542 Binary |= 1 << ARMII::I_BitShift;
543 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
548 template<class CodeEmitter>
549 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
550 unsigned Opcode = MI.getDesc().Opcode;
552 // Part of binary is determined by TableGn.
553 unsigned Binary = getBinaryCodeForInstr(MI);
555 // Set the conditional execution predicate
556 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
558 // Encode S bit if MI modifies CPSR.
559 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
560 Binary |= 1 << ARMII::S_BitShift;
562 // Encode register def if there is one.
563 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
565 // Encode the shift operation.
572 case ARM::MOVsrl_flag:
574 Binary |= (0x2 << 4) | (1 << 7);
576 case ARM::MOVsra_flag:
578 Binary |= (0x4 << 4) | (1 << 7);
582 // Encode register Rm.
583 Binary |= getMachineOpValue(MI, 1);
588 template<class CodeEmitter>
589 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
590 DEBUG(errs() << " ** LPC" << LabelID << " @ "
591 << (void*)MCE.getCurrentPCValue() << '\n');
592 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
595 template<class CodeEmitter>
596 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
597 unsigned Opcode = MI.getDesc().Opcode;
600 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
601 // FIXME: Add support for MOVimm32.
602 case TargetInstrInfo::INLINEASM: {
603 // We allow inline assembler nodes with empty bodies - they can
604 // implicitly define registers, which is ok for JIT.
605 if (MI.getOperand(0).getSymbolName()[0]) {
606 llvm_report_error("JIT does not support inline asm!");
610 case TargetInstrInfo::DBG_LABEL:
611 case TargetInstrInfo::EH_LABEL:
612 MCE.emitLabel(MI.getOperand(0).getImm());
614 case TargetInstrInfo::IMPLICIT_DEF:
615 case TargetInstrInfo::KILL:
618 case ARM::CONSTPOOL_ENTRY:
619 emitConstPoolInstruction(MI);
622 // Remember of the address of the PC label for relocation later.
623 addPCLabel(MI.getOperand(2).getImm());
624 // PICADD is just an add instruction that implicitly read pc.
625 emitDataProcessingInstruction(MI, 0, ARM::PC);
632 // Remember of the address of the PC label for relocation later.
633 addPCLabel(MI.getOperand(2).getImm());
634 // These are just load / store instructions that implicitly read pc.
635 emitLoadStoreInstruction(MI, 0, ARM::PC);
642 // Remember of the address of the PC label for relocation later.
643 addPCLabel(MI.getOperand(2).getImm());
644 // These are just load / store instructions that implicitly read pc.
645 emitMiscLoadStoreInstruction(MI, ARM::PC);
648 case ARM::MOVi2pieces:
649 // Two instructions to materialize a constant.
650 emitMOVi2piecesInstruction(MI);
652 case ARM::LEApcrelJT:
653 // Materialize jumptable address.
654 emitLEApcrelJTInstruction(MI);
657 case ARM::MOVsrl_flag:
658 case ARM::MOVsra_flag:
659 emitPseudoMoveInstruction(MI);
664 template<class CodeEmitter>
665 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
666 const MachineInstr &MI,
667 const TargetInstrDesc &TID,
668 const MachineOperand &MO,
670 unsigned Binary = getMachineOpValue(MI, MO);
672 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
673 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
674 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
676 // Encode the shift opcode.
678 unsigned Rs = MO1.getReg();
680 // Set shift operand (bit[7:4]).
685 // RRX - 0110 and bit[11:8] clear.
687 default: llvm_unreachable("Unknown shift opc!");
688 case ARM_AM::lsl: SBits = 0x1; break;
689 case ARM_AM::lsr: SBits = 0x3; break;
690 case ARM_AM::asr: SBits = 0x5; break;
691 case ARM_AM::ror: SBits = 0x7; break;
692 case ARM_AM::rrx: SBits = 0x6; break;
695 // Set shift operand (bit[6:4]).
701 default: llvm_unreachable("Unknown shift opc!");
702 case ARM_AM::lsl: SBits = 0x0; break;
703 case ARM_AM::lsr: SBits = 0x2; break;
704 case ARM_AM::asr: SBits = 0x4; break;
705 case ARM_AM::ror: SBits = 0x6; break;
708 Binary |= SBits << 4;
709 if (SOpc == ARM_AM::rrx)
712 // Encode the shift operation Rs or shift_imm (except rrx).
714 // Encode Rs bit[11:8].
715 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
717 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
720 // Encode shift_imm bit[11:7].
721 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
724 template<class CodeEmitter>
725 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
726 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
727 assert(SoImmVal != -1 && "Not a valid so_imm value!");
729 // Encode rotate_imm.
730 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
731 << ARMII::SoRotImmShift;
734 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
738 template<class CodeEmitter>
739 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
740 const TargetInstrDesc &TID) const {
741 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
742 const MachineOperand &MO = MI.getOperand(i-1);
743 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
744 return 1 << ARMII::S_BitShift;
749 template<class CodeEmitter>
750 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
751 const MachineInstr &MI,
753 unsigned ImplicitRn) {
754 const TargetInstrDesc &TID = MI.getDesc();
756 if (TID.Opcode == ARM::BFC) {
757 llvm_report_error("ARMv6t2 JIT is not yet supported.");
760 // Part of binary is determined by TableGn.
761 unsigned Binary = getBinaryCodeForInstr(MI);
763 // Set the conditional execution predicate
764 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
766 // Encode S bit if MI modifies CPSR.
767 Binary |= getAddrModeSBit(MI, TID);
769 // Encode register def if there is one.
770 unsigned NumDefs = TID.getNumDefs();
773 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
775 // Special handling for implicit use (e.g. PC).
776 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
777 << ARMII::RegRdShift);
779 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
780 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
783 // Encode first non-shifter register operand if there is one.
784 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
787 // Special handling for implicit use (e.g. PC).
788 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
789 << ARMII::RegRnShift);
791 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
796 // Encode shifter operand.
797 const MachineOperand &MO = MI.getOperand(OpIdx);
798 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
800 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
805 // Encode register Rm.
806 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
811 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
816 template<class CodeEmitter>
817 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
818 const MachineInstr &MI,
820 unsigned ImplicitRn) {
821 const TargetInstrDesc &TID = MI.getDesc();
822 unsigned Form = TID.TSFlags & ARMII::FormMask;
823 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
825 // Part of binary is determined by TableGn.
826 unsigned Binary = getBinaryCodeForInstr(MI);
828 // Set the conditional execution predicate
829 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
833 // Operand 0 of a pre- and post-indexed store is the address base
834 // writeback. Skip it.
835 bool Skipped = false;
836 if (IsPrePost && Form == ARMII::StFrm) {
843 // Special handling for implicit use (e.g. PC).
844 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
845 << ARMII::RegRdShift);
847 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
849 // Set second operand
851 // Special handling for implicit use (e.g. PC).
852 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
853 << ARMII::RegRnShift);
855 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
857 // If this is a two-address operand, skip it. e.g. LDR_PRE.
858 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
861 const MachineOperand &MO2 = MI.getOperand(OpIdx);
862 unsigned AM2Opc = (ImplicitRn == ARM::PC)
863 ? 0 : MI.getOperand(OpIdx+1).getImm();
865 // Set bit U(23) according to sign of immed value (positive or negative).
866 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
868 if (!MO2.getReg()) { // is immediate
869 if (ARM_AM::getAM2Offset(AM2Opc))
870 // Set the value of offset_12 field
871 Binary |= ARM_AM::getAM2Offset(AM2Opc);
876 // Set bit I(25), because this is not in immediate enconding.
877 Binary |= 1 << ARMII::I_BitShift;
878 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
879 // Set bit[3:0] to the corresponding Rm register
880 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
882 // If this instr is in scaled register offset/index instruction, set
883 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
884 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
885 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
886 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
892 template<class CodeEmitter>
893 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
894 unsigned ImplicitRn) {
895 const TargetInstrDesc &TID = MI.getDesc();
896 unsigned Form = TID.TSFlags & ARMII::FormMask;
897 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
899 // Part of binary is determined by TableGn.
900 unsigned Binary = getBinaryCodeForInstr(MI);
902 // Set the conditional execution predicate
903 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
907 // Operand 0 of a pre- and post-indexed store is the address base
908 // writeback. Skip it.
909 bool Skipped = false;
910 if (IsPrePost && Form == ARMII::StMiscFrm) {
916 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
918 // Skip LDRD and STRD's second operand.
919 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
922 // Set second operand
924 // Special handling for implicit use (e.g. PC).
925 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
926 << ARMII::RegRnShift);
928 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
930 // If this is a two-address operand, skip it. e.g. LDRH_POST.
931 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
934 const MachineOperand &MO2 = MI.getOperand(OpIdx);
935 unsigned AM3Opc = (ImplicitRn == ARM::PC)
936 ? 0 : MI.getOperand(OpIdx+1).getImm();
938 // Set bit U(23) according to sign of immed value (positive or negative)
939 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
942 // If this instr is in register offset/index encoding, set bit[3:0]
943 // to the corresponding Rm register.
945 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
950 // This instr is in immediate offset/index encoding, set bit 22 to 1.
951 Binary |= 1 << ARMII::AM3_I_BitShift;
952 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
954 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
955 Binary |= (ImmOffs & 0xF); // immedL
961 static unsigned getAddrModeUPBits(unsigned Mode) {
964 // Set addressing mode by modifying bits U(23) and P(24)
965 // IA - Increment after - bit U = 1 and bit P = 0
966 // IB - Increment before - bit U = 1 and bit P = 1
967 // DA - Decrement after - bit U = 0 and bit P = 0
968 // DB - Decrement before - bit U = 0 and bit P = 1
970 default: llvm_unreachable("Unknown addressing sub-mode!");
971 case ARM_AM::da: break;
972 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
973 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
974 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
980 template<class CodeEmitter>
981 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
982 const MachineInstr &MI) {
983 // Part of binary is determined by TableGn.
984 unsigned Binary = getBinaryCodeForInstr(MI);
986 // Set the conditional execution predicate
987 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
989 // Set base address operand
990 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
992 // Set addressing mode by modifying bits U(23) and P(24)
993 const MachineOperand &MO = MI.getOperand(1);
994 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
997 if (ARM_AM::getAM4WBFlag(MO.getImm()))
998 Binary |= 0x1 << ARMII::W_BitShift;
1001 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1002 const MachineOperand &MO = MI.getOperand(i);
1003 if (!MO.isReg() || MO.isImplicit())
1005 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1006 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1008 Binary |= 0x1 << RegNum;
1014 template<class CodeEmitter>
1015 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1016 const TargetInstrDesc &TID = MI.getDesc();
1018 // Part of binary is determined by TableGn.
1019 unsigned Binary = getBinaryCodeForInstr(MI);
1021 // Set the conditional execution predicate
1022 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1024 // Encode S bit if MI modifies CPSR.
1025 Binary |= getAddrModeSBit(MI, TID);
1027 // 32x32->64bit operations have two destination registers. The number
1028 // of register definitions will tell us if that's what we're dealing with.
1030 if (TID.getNumDefs() == 2)
1031 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1034 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1037 Binary |= getMachineOpValue(MI, OpIdx++);
1040 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1042 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1043 // it as Rn (for multiply, that's in the same offset as RdLo.
1044 if (TID.getNumOperands() > OpIdx &&
1045 !TID.OpInfo[OpIdx].isPredicate() &&
1046 !TID.OpInfo[OpIdx].isOptionalDef())
1047 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1052 template<class CodeEmitter>
1053 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1054 const TargetInstrDesc &TID = MI.getDesc();
1056 // Part of binary is determined by TableGn.
1057 unsigned Binary = getBinaryCodeForInstr(MI);
1059 // Set the conditional execution predicate
1060 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1065 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1067 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1068 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1070 // Two register operand form.
1072 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1075 Binary |= getMachineOpValue(MI, MO2);
1078 Binary |= getMachineOpValue(MI, MO1);
1081 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1082 if (MI.getOperand(OpIdx).isImm() &&
1083 !TID.OpInfo[OpIdx].isPredicate() &&
1084 !TID.OpInfo[OpIdx].isOptionalDef())
1085 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1090 template<class CodeEmitter>
1091 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1092 const TargetInstrDesc &TID = MI.getDesc();
1094 // Part of binary is determined by TableGn.
1095 unsigned Binary = getBinaryCodeForInstr(MI);
1097 // Set the conditional execution predicate
1098 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1103 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1105 const MachineOperand &MO = MI.getOperand(OpIdx++);
1106 if (OpIdx == TID.getNumOperands() ||
1107 TID.OpInfo[OpIdx].isPredicate() ||
1108 TID.OpInfo[OpIdx].isOptionalDef()) {
1109 // Encode Rm and it's done.
1110 Binary |= getMachineOpValue(MI, MO);
1116 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1119 Binary |= getMachineOpValue(MI, OpIdx++);
1121 // Encode shift_imm.
1122 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1123 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1124 Binary |= ShiftAmt << ARMII::ShiftShift;
1129 template<class CodeEmitter>
1130 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1131 const TargetInstrDesc &TID = MI.getDesc();
1133 if (TID.Opcode == ARM::TPsoft) {
1134 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1137 // Part of binary is determined by TableGn.
1138 unsigned Binary = getBinaryCodeForInstr(MI);
1140 // Set the conditional execution predicate
1141 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1143 // Set signed_immed_24 field
1144 Binary |= getMachineOpValue(MI, 0);
1149 template<class CodeEmitter>
1150 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1151 // Remember the base address of the inline jump table.
1152 uintptr_t JTBase = MCE.getCurrentPCValue();
1153 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1154 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1157 // Now emit the jump table entries.
1158 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1159 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1161 // DestBB address - JT base.
1162 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1164 // Absolute DestBB address.
1165 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1170 template<class CodeEmitter>
1171 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1172 const TargetInstrDesc &TID = MI.getDesc();
1174 // Handle jump tables.
1175 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1176 // First emit a ldr pc, [] instruction.
1177 emitDataProcessingInstruction(MI, ARM::PC);
1179 // Then emit the inline jump table.
1181 (TID.Opcode == ARM::BR_JTr)
1182 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1183 emitInlineJumpTable(JTIndex);
1185 } else if (TID.Opcode == ARM::BR_JTm) {
1186 // First emit a ldr pc, [] instruction.
1187 emitLoadStoreInstruction(MI, ARM::PC);
1189 // Then emit the inline jump table.
1190 emitInlineJumpTable(MI.getOperand(3).getIndex());
1194 // Part of binary is determined by TableGn.
1195 unsigned Binary = getBinaryCodeForInstr(MI);
1197 // Set the conditional execution predicate
1198 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1200 if (TID.Opcode == ARM::BX_RET)
1201 // The return register is LR.
1202 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1204 // otherwise, set the return register
1205 Binary |= getMachineOpValue(MI, 0);
1210 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1211 unsigned RegD = MI.getOperand(OpIdx).getReg();
1212 unsigned Binary = 0;
1213 bool isSPVFP = false;
1214 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1216 Binary |= RegD << ARMII::RegRdShift;
1218 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1219 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1224 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1225 unsigned RegN = MI.getOperand(OpIdx).getReg();
1226 unsigned Binary = 0;
1227 bool isSPVFP = false;
1228 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1230 Binary |= RegN << ARMII::RegRnShift;
1232 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1233 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1238 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1239 unsigned RegM = MI.getOperand(OpIdx).getReg();
1240 unsigned Binary = 0;
1241 bool isSPVFP = false;
1242 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1246 Binary |= ((RegM & 0x1E) >> 1);
1247 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1252 template<class CodeEmitter>
1253 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1254 const TargetInstrDesc &TID = MI.getDesc();
1256 // Part of binary is determined by TableGn.
1257 unsigned Binary = getBinaryCodeForInstr(MI);
1259 // Set the conditional execution predicate
1260 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1263 assert((Binary & ARMII::D_BitShift) == 0 &&
1264 (Binary & ARMII::N_BitShift) == 0 &&
1265 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1268 Binary |= encodeVFPRd(MI, OpIdx++);
1270 // If this is a two-address operand, skip it, e.g. FMACD.
1271 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1275 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1276 Binary |= encodeVFPRn(MI, OpIdx++);
1278 if (OpIdx == TID.getNumOperands() ||
1279 TID.OpInfo[OpIdx].isPredicate() ||
1280 TID.OpInfo[OpIdx].isOptionalDef()) {
1281 // FCMPEZD etc. has only one operand.
1287 Binary |= encodeVFPRm(MI, OpIdx);
1292 template<class CodeEmitter>
1293 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1294 const MachineInstr &MI) {
1295 const TargetInstrDesc &TID = MI.getDesc();
1296 unsigned Form = TID.TSFlags & ARMII::FormMask;
1298 // Part of binary is determined by TableGn.
1299 unsigned Binary = getBinaryCodeForInstr(MI);
1301 // Set the conditional execution predicate
1302 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1306 case ARMII::VFPConv1Frm:
1307 case ARMII::VFPConv2Frm:
1308 case ARMII::VFPConv3Frm:
1310 Binary |= encodeVFPRd(MI, 0);
1312 case ARMII::VFPConv4Frm:
1314 Binary |= encodeVFPRn(MI, 0);
1316 case ARMII::VFPConv5Frm:
1318 Binary |= encodeVFPRm(MI, 0);
1324 case ARMII::VFPConv1Frm:
1326 Binary |= encodeVFPRm(MI, 1);
1328 case ARMII::VFPConv2Frm:
1329 case ARMII::VFPConv3Frm:
1331 Binary |= encodeVFPRn(MI, 1);
1333 case ARMII::VFPConv4Frm:
1334 case ARMII::VFPConv5Frm:
1336 Binary |= encodeVFPRd(MI, 1);
1340 if (Form == ARMII::VFPConv5Frm)
1342 Binary |= encodeVFPRn(MI, 2);
1343 else if (Form == ARMII::VFPConv3Frm)
1345 Binary |= encodeVFPRm(MI, 2);
1350 template<class CodeEmitter>
1351 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1352 // Part of binary is determined by TableGn.
1353 unsigned Binary = getBinaryCodeForInstr(MI);
1355 // Set the conditional execution predicate
1356 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1361 Binary |= encodeVFPRd(MI, OpIdx++);
1363 // Encode address base.
1364 const MachineOperand &Base = MI.getOperand(OpIdx++);
1365 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1367 // If there is a non-zero immediate offset, encode it.
1369 const MachineOperand &Offset = MI.getOperand(OpIdx);
1370 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1371 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1372 Binary |= 1 << ARMII::U_BitShift;
1379 // If immediate offset is omitted, default to +0.
1380 Binary |= 1 << ARMII::U_BitShift;
1385 template<class CodeEmitter>
1386 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1387 const MachineInstr &MI) {
1388 // Part of binary is determined by TableGn.
1389 unsigned Binary = getBinaryCodeForInstr(MI);
1391 // Set the conditional execution predicate
1392 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1394 // Set base address operand
1395 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1397 // Set addressing mode by modifying bits U(23) and P(24)
1398 const MachineOperand &MO = MI.getOperand(1);
1399 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1402 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1403 Binary |= 0x1 << ARMII::W_BitShift;
1405 // First register is encoded in Dd.
1406 Binary |= encodeVFPRd(MI, 5);
1408 // Number of registers are encoded in offset field.
1409 unsigned NumRegs = 1;
1410 for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
1411 const MachineOperand &MO = MI.getOperand(i);
1412 if (!MO.isReg() || MO.isImplicit())
1416 Binary |= NumRegs * 2;
1421 template<class CodeEmitter>
1422 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1423 // Part of binary is determined by TableGn.
1424 unsigned Binary = getBinaryCodeForInstr(MI);
1426 // Set the conditional execution predicate
1427 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1432 #include "ARMGenCodeEmitter.inc"