1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const MCInstrDesc &MCID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const MCInstrDesc &MCID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
212 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
216 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
220 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
226 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
228 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
231 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
233 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
235 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
236 unsigned Op) const { return 0; }
237 unsigned getSsatBitPosValue(const MachineInstr &MI,
238 unsigned Op) const { return 0; }
239 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
241 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
244 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
247 // {12} = (U)nsigned (add == '1', sub == '0')
249 const MachineOperand &MO = MI.getOperand(Op);
250 const MachineOperand &MO1 = MI.getOperand(Op + 1);
252 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
255 unsigned Reg = getARMRegisterNumbering(MO.getReg());
256 int32_t Imm12 = MO1.getImm();
258 Binary = Imm12 & 0xfff;
261 Binary |= (Reg << 13);
265 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
269 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
273 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
275 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
277 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
279 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
281 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
283 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
285 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
287 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
289 // {12} = (U)nsigned (add == '1', sub == '0')
291 const MachineOperand &MO = MI.getOperand(Op);
292 const MachineOperand &MO1 = MI.getOperand(Op + 1);
294 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
297 unsigned Reg = getARMRegisterNumbering(MO.getReg());
298 int32_t Imm12 = MO1.getImm();
300 // Special value for #-0
301 if (Imm12 == INT32_MIN)
304 // Immediate is always encoded as positive. The 'U' bit controls add vs
312 uint32_t Binary = Imm12 & 0xfff;
315 Binary |= (Reg << 13);
318 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
321 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
324 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
326 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
328 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
330 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
333 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
334 /// machine operand requires relocation, record the relocation and return
336 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
339 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
341 unsigned getShiftOp(unsigned Imm) const ;
343 /// Routines that handle operands which add machine relocations which are
344 /// fixed up by the relocation stage.
345 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
346 bool MayNeedFarStub, bool Indirect,
347 intptr_t ACPV = 0) const;
348 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
349 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
350 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
351 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
352 intptr_t JTBase = 0) const;
356 char ARMCodeEmitter::ID = 0;
358 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
359 /// code to the specified MCE object.
360 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
361 JITCodeEmitter &JCE) {
362 return new ARMCodeEmitter(TM, JCE);
365 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
366 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
367 MF.getTarget().getRelocationModel() != Reloc::Static) &&
368 "JIT relocation model must be set to static or default!");
369 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
370 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
371 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
372 Subtarget = &TM.getSubtarget<ARMSubtarget>();
373 MCPEs = &MF.getConstantPool()->getConstants();
375 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
376 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
377 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
378 JTI->Initialize(MF, IsPIC);
379 MMI = &getAnalysis<MachineModuleInfo>();
380 MCE.setModuleInfo(MMI);
383 DEBUG(errs() << "JITTing function '"
384 << MF.getFunction()->getName() << "'\n");
385 MCE.startFunction(MF);
386 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
388 MCE.StartMachineBasicBlock(MBB);
389 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
393 } while (MCE.finishFunction(MF));
398 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
400 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
401 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
402 default: llvm_unreachable("Unknown shift opc!");
403 case ARM_AM::asr: return 2;
404 case ARM_AM::lsl: return 0;
405 case ARM_AM::lsr: return 1;
407 case ARM_AM::rrx: return 3;
411 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
412 /// machine operand requires relocation, record the relocation and return zero.
413 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
414 const MachineOperand &MO,
416 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
417 && "Relocation to this function should be for movt or movw");
420 return static_cast<unsigned>(MO.getImm());
421 else if (MO.isGlobal())
422 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
423 else if (MO.isSymbol())
424 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
426 emitMachineBasicBlock(MO.getMBB(), Reloc);
431 llvm_unreachable("Unsupported operand type for movw/movt");
436 /// getMachineOpValue - Return binary encoding of operand. If the machine
437 /// operand requires relocation, record the relocation and return zero.
438 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
439 const MachineOperand &MO) const {
441 return getARMRegisterNumbering(MO.getReg());
443 return static_cast<unsigned>(MO.getImm());
444 else if (MO.isGlobal())
445 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
446 else if (MO.isSymbol())
447 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
448 else if (MO.isCPI()) {
449 const MCInstrDesc &MCID = MI.getDesc();
450 // For VFP load, the immediate offset is multiplied by 4.
451 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
452 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
453 emitConstPoolAddress(MO.getIndex(), Reloc);
454 } else if (MO.isJTI())
455 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
457 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
459 llvm_unreachable("Unable to encode MachineOperand!");
463 /// emitGlobalAddress - Emit the specified address to the code stream.
465 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
466 bool MayNeedFarStub, bool Indirect,
467 intptr_t ACPV) const {
468 MachineRelocation MR = Indirect
469 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
470 const_cast<GlobalValue *>(GV),
471 ACPV, MayNeedFarStub)
472 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
473 const_cast<GlobalValue *>(GV), ACPV,
475 MCE.addRelocation(MR);
478 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
479 /// be emitted to the current location in the function, and allow it to be PC
481 void ARMCodeEmitter::
482 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
483 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
487 /// emitConstPoolAddress - Arrange for the address of an constant pool
488 /// to be emitted to the current location in the function, and allow it to be PC
490 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
491 // Tell JIT emitter we'll resolve the address.
492 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
493 Reloc, CPI, 0, true));
496 /// emitJumpTableAddress - Arrange for the address of a jump table to
497 /// be emitted to the current location in the function, and allow it to be PC
499 void ARMCodeEmitter::
500 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
501 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
502 Reloc, JTIndex, 0, true));
505 /// emitMachineBasicBlock - Emit the specified address basic block.
506 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
508 intptr_t JTBase) const {
509 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
513 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
514 DEBUG(errs() << " 0x";
515 errs().write_hex(Binary) << "\n");
516 MCE.emitWordLE(Binary);
519 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
520 DEBUG(errs() << " 0x";
521 errs().write_hex(Binary) << "\n");
522 MCE.emitDWordLE(Binary);
525 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
526 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
528 MCE.processDebugLoc(MI.getDebugLoc(), true);
530 ++NumEmitted; // Keep track of the # of mi's emitted
531 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
533 llvm_unreachable("Unhandled instruction encoding format!");
536 if (MI.getOpcode() == ARM::LEApcrelJT) {
537 // Materialize jumptable address.
538 emitLEApcrelJTInstruction(MI);
541 llvm_unreachable("Unhandled instruction encoding!");
543 emitPseudoInstruction(MI);
546 case ARMII::DPSoRegFrm:
547 emitDataProcessingInstruction(MI);
551 emitLoadStoreInstruction(MI);
553 case ARMII::LdMiscFrm:
554 case ARMII::StMiscFrm:
555 emitMiscLoadStoreInstruction(MI);
557 case ARMII::LdStMulFrm:
558 emitLoadStoreMultipleInstruction(MI);
561 emitMulFrmInstruction(MI);
564 emitExtendInstruction(MI);
566 case ARMII::ArithMiscFrm:
567 emitMiscArithInstruction(MI);
570 emitSaturateInstruction(MI);
573 emitBranchInstruction(MI);
575 case ARMII::BrMiscFrm:
576 emitMiscBranchInstruction(MI);
579 case ARMII::VFPUnaryFrm:
580 case ARMII::VFPBinaryFrm:
581 emitVFPArithInstruction(MI);
583 case ARMII::VFPConv1Frm:
584 case ARMII::VFPConv2Frm:
585 case ARMII::VFPConv3Frm:
586 case ARMII::VFPConv4Frm:
587 case ARMII::VFPConv5Frm:
588 emitVFPConversionInstruction(MI);
590 case ARMII::VFPLdStFrm:
591 emitVFPLoadStoreInstruction(MI);
593 case ARMII::VFPLdStMulFrm:
594 emitVFPLoadStoreMultipleInstruction(MI);
597 // NEON instructions.
598 case ARMII::NGetLnFrm:
599 case ARMII::NSetLnFrm:
600 emitNEONLaneInstruction(MI);
603 emitNEONDupInstruction(MI);
605 case ARMII::N1RegModImmFrm:
606 emitNEON1RegModImmInstruction(MI);
608 case ARMII::N2RegFrm:
609 emitNEON2RegInstruction(MI);
611 case ARMII::N3RegFrm:
612 emitNEON3RegInstruction(MI);
615 MCE.processDebugLoc(MI.getDebugLoc(), false);
618 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
619 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
620 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
621 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
623 // Remember the CONSTPOOL_ENTRY address for later relocation.
624 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
626 // Emit constpool island entry. In most cases, the actual values will be
627 // resolved and relocated after code emission.
628 if (MCPE.isMachineConstantPoolEntry()) {
629 ARMConstantPoolValue *ACPV =
630 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
632 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
633 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
635 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
636 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
638 Reloc::Model RelocM = TM.getRelocationModel();
639 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
641 Subtarget->GVIsIndirectSymbol(GV, RelocM),
644 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
645 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
649 const Constant *CV = MCPE.Val.ConstVal;
652 errs() << " ** Constant pool #" << CPI << " @ "
653 << (void*)MCE.getCurrentPCValue() << " ";
654 if (const Function *F = dyn_cast<Function>(CV))
655 errs() << F->getName();
661 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
662 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
664 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
665 uint32_t Val = uint32_t(*CI->getValue().getRawData());
667 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
668 if (CFP->getType()->isFloatTy())
669 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
670 else if (CFP->getType()->isDoubleTy())
671 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
673 llvm_unreachable("Unable to handle this constantpool entry!");
676 llvm_unreachable("Unable to handle this constantpool entry!");
681 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
682 const MachineOperand &MO0 = MI.getOperand(0);
683 const MachineOperand &MO1 = MI.getOperand(1);
685 // Emit the 'movw' instruction.
686 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
688 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
690 // Set the conditional execution predicate.
691 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
694 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
696 // Encode imm16 as imm4:imm12
697 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
698 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
701 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
702 // Emit the 'movt' instruction.
703 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
705 // Set the conditional execution predicate.
706 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
709 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
711 // Encode imm16 as imm4:imm1, same as movw above.
712 Binary |= Hi16 & 0xFFF;
713 Binary |= ((Hi16 >> 12) & 0xF) << 16;
717 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
718 const MachineOperand &MO0 = MI.getOperand(0);
719 const MachineOperand &MO1 = MI.getOperand(1);
720 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
721 "Not a valid so_imm value!");
722 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
723 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
725 // Emit the 'mov' instruction.
726 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
728 // Set the conditional execution predicate.
729 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
732 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
735 // Set bit I(25) to identify this is the immediate form of <shifter_op>
736 Binary |= 1 << ARMII::I_BitShift;
737 Binary |= getMachineSoImmOpValue(V1);
740 // Now the 'orr' instruction.
741 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
743 // Set the conditional execution predicate.
744 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
747 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
753 // Set bit I(25) to identify this is the immediate form of <shifter_op>
754 Binary |= 1 << ARMII::I_BitShift;
755 Binary |= getMachineSoImmOpValue(V2);
759 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
760 // It's basically add r, pc, (LJTI - $+8)
762 const MCInstrDesc &MCID = MI.getDesc();
764 // Emit the 'add' instruction.
765 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
767 // Set the conditional execution predicate
768 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
770 // Encode S bit if MI modifies CPSR.
771 Binary |= getAddrModeSBit(MI, MCID);
774 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
776 // Encode Rn which is PC.
777 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
779 // Encode the displacement.
780 Binary |= 1 << ARMII::I_BitShift;
781 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
786 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
787 unsigned Opcode = MI.getDesc().Opcode;
789 // Part of binary is determined by TableGn.
790 unsigned Binary = getBinaryCodeForInstr(MI);
792 // Set the conditional execution predicate
793 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
795 // Encode S bit if MI modifies CPSR.
796 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
797 Binary |= 1 << ARMII::S_BitShift;
799 // Encode register def if there is one.
800 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
802 // Encode the shift operation.
809 case ARM::MOVsrl_flag:
811 Binary |= (0x2 << 4) | (1 << 7);
813 case ARM::MOVsra_flag:
815 Binary |= (0x4 << 4) | (1 << 7);
819 // Encode register Rm.
820 Binary |= getMachineOpValue(MI, 1);
825 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
826 DEBUG(errs() << " ** LPC" << LabelID << " @ "
827 << (void*)MCE.getCurrentPCValue() << '\n');
828 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
831 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
832 unsigned Opcode = MI.getDesc().Opcode;
835 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
837 case ARM::BMOVPCRX_CALL:
839 case ARM::BMOVPCRXr9_CALL: {
840 // First emit mov lr, pc
841 unsigned Binary = 0x01a0e00f;
842 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
845 // and then emit the branch.
846 emitMiscBranchInstruction(MI);
849 case TargetOpcode::INLINEASM: {
850 // We allow inline assembler nodes with empty bodies - they can
851 // implicitly define registers, which is ok for JIT.
852 if (MI.getOperand(0).getSymbolName()[0]) {
853 report_fatal_error("JIT does not support inline asm!");
857 case TargetOpcode::PROLOG_LABEL:
858 case TargetOpcode::EH_LABEL:
859 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
861 case TargetOpcode::IMPLICIT_DEF:
862 case TargetOpcode::KILL:
865 case ARM::CONSTPOOL_ENTRY:
866 emitConstPoolInstruction(MI);
869 // Remember of the address of the PC label for relocation later.
870 addPCLabel(MI.getOperand(2).getImm());
871 // PICADD is just an add instruction that implicitly read pc.
872 emitDataProcessingInstruction(MI, 0, ARM::PC);
879 // Remember of the address of the PC label for relocation later.
880 addPCLabel(MI.getOperand(2).getImm());
881 // These are just load / store instructions that implicitly read pc.
882 emitLoadStoreInstruction(MI, 0, ARM::PC);
889 // Remember of the address of the PC label for relocation later.
890 addPCLabel(MI.getOperand(2).getImm());
891 // These are just load / store instructions that implicitly read pc.
892 emitMiscLoadStoreInstruction(MI, ARM::PC);
897 // Two instructions to materialize a constant.
898 if (Subtarget->hasV6T2Ops())
899 emitMOVi32immInstruction(MI);
901 emitMOVi2piecesInstruction(MI);
904 case ARM::LEApcrelJT:
905 // Materialize jumptable address.
906 emitLEApcrelJTInstruction(MI);
909 case ARM::MOVsrl_flag:
910 case ARM::MOVsra_flag:
911 emitPseudoMoveInstruction(MI);
916 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
917 const MCInstrDesc &MCID,
918 const MachineOperand &MO,
920 unsigned Binary = getMachineOpValue(MI, MO);
922 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
923 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
924 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
926 // Encode the shift opcode.
928 unsigned Rs = MO1.getReg();
930 // Set shift operand (bit[7:4]).
935 // RRX - 0110 and bit[11:8] clear.
937 default: llvm_unreachable("Unknown shift opc!");
938 case ARM_AM::lsl: SBits = 0x1; break;
939 case ARM_AM::lsr: SBits = 0x3; break;
940 case ARM_AM::asr: SBits = 0x5; break;
941 case ARM_AM::ror: SBits = 0x7; break;
942 case ARM_AM::rrx: SBits = 0x6; break;
945 // Set shift operand (bit[6:4]).
951 default: llvm_unreachable("Unknown shift opc!");
952 case ARM_AM::lsl: SBits = 0x0; break;
953 case ARM_AM::lsr: SBits = 0x2; break;
954 case ARM_AM::asr: SBits = 0x4; break;
955 case ARM_AM::ror: SBits = 0x6; break;
958 Binary |= SBits << 4;
959 if (SOpc == ARM_AM::rrx)
962 // Encode the shift operation Rs or shift_imm (except rrx).
964 // Encode Rs bit[11:8].
965 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
966 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
969 // Encode shift_imm bit[11:7].
970 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
973 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
974 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
975 assert(SoImmVal != -1 && "Not a valid so_imm value!");
977 // Encode rotate_imm.
978 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
979 << ARMII::SoRotImmShift;
982 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
986 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
987 const MCInstrDesc &MCID) const {
988 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
989 const MachineOperand &MO = MI.getOperand(i-1);
990 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
991 return 1 << ARMII::S_BitShift;
996 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
998 unsigned ImplicitRn) {
999 const MCInstrDesc &MCID = MI.getDesc();
1001 // Part of binary is determined by TableGn.
1002 unsigned Binary = getBinaryCodeForInstr(MI);
1004 // Set the conditional execution predicate
1005 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1007 // Encode S bit if MI modifies CPSR.
1008 Binary |= getAddrModeSBit(MI, MCID);
1010 // Encode register def if there is one.
1011 unsigned NumDefs = MCID.getNumDefs();
1014 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1015 else if (ImplicitRd)
1016 // Special handling for implicit use (e.g. PC).
1017 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1019 if (MCID.Opcode == ARM::MOVi16) {
1020 // Get immediate from MI.
1021 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1022 ARM::reloc_arm_movw);
1023 // Encode imm which is the same as in emitMOVi32immInstruction().
1024 Binary |= Lo16 & 0xFFF;
1025 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1028 } else if(MCID.Opcode == ARM::MOVTi16) {
1029 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1030 ARM::reloc_arm_movt) >> 16);
1031 Binary |= Hi16 & 0xFFF;
1032 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1035 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1036 uint32_t v = ~MI.getOperand(2).getImm();
1037 int32_t lsb = CountTrailingZeros_32(v);
1038 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1039 // Instr{20-16} = msb, Instr{11-7} = lsb
1040 Binary |= (msb & 0x1F) << 16;
1041 Binary |= (lsb & 0x1F) << 7;
1044 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1045 // Encode Rn in Instr{0-3}
1046 Binary |= getMachineOpValue(MI, OpIdx++);
1048 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1049 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1051 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1052 Binary |= (widthm1 & 0x1F) << 16;
1053 Binary |= (lsb & 0x1F) << 7;
1058 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1059 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1062 // Encode first non-shifter register operand if there is one.
1063 bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1066 // Special handling for implicit use (e.g. PC).
1067 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1069 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1074 // Encode shifter operand.
1075 const MachineOperand &MO = MI.getOperand(OpIdx);
1076 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1078 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1083 // Encode register Rm.
1084 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1089 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1094 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1095 unsigned ImplicitRd,
1096 unsigned ImplicitRn) {
1097 const MCInstrDesc &MCID = MI.getDesc();
1098 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1099 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1101 // Part of binary is determined by TableGn.
1102 unsigned Binary = getBinaryCodeForInstr(MI);
1104 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1105 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1106 MI.getOpcode() == ARM::STRi12) {
1111 // Set the conditional execution predicate
1112 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1116 // Operand 0 of a pre- and post-indexed store is the address base
1117 // writeback. Skip it.
1118 bool Skipped = false;
1119 if (IsPrePost && Form == ARMII::StFrm) {
1124 // Set first operand
1126 // Special handling for implicit use (e.g. PC).
1127 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1129 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1131 // Set second operand
1133 // Special handling for implicit use (e.g. PC).
1134 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1136 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1138 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1139 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1142 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1143 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1144 ? 0 : MI.getOperand(OpIdx+1).getImm();
1146 // Set bit U(23) according to sign of immed value (positive or negative).
1147 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1149 if (!MO2.getReg()) { // is immediate
1150 if (ARM_AM::getAM2Offset(AM2Opc))
1151 // Set the value of offset_12 field
1152 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1157 // Set bit I(25), because this is not in immediate encoding.
1158 Binary |= 1 << ARMII::I_BitShift;
1159 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1160 // Set bit[3:0] to the corresponding Rm register
1161 Binary |= getARMRegisterNumbering(MO2.getReg());
1163 // If this instr is in scaled register offset/index instruction, set
1164 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1165 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1166 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1167 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1173 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1174 unsigned ImplicitRn) {
1175 const MCInstrDesc &MCID = MI.getDesc();
1176 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1177 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1179 // Part of binary is determined by TableGn.
1180 unsigned Binary = getBinaryCodeForInstr(MI);
1182 // Set the conditional execution predicate
1183 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1187 // Operand 0 of a pre- and post-indexed store is the address base
1188 // writeback. Skip it.
1189 bool Skipped = false;
1190 if (IsPrePost && Form == ARMII::StMiscFrm) {
1195 // Set first operand
1196 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1198 // Skip LDRD and STRD's second operand.
1199 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1202 // Set second operand
1204 // Special handling for implicit use (e.g. PC).
1205 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1207 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1209 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1210 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1213 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1214 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1215 ? 0 : MI.getOperand(OpIdx+1).getImm();
1217 // Set bit U(23) according to sign of immed value (positive or negative)
1218 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1221 // If this instr is in register offset/index encoding, set bit[3:0]
1222 // to the corresponding Rm register.
1224 Binary |= getARMRegisterNumbering(MO2.getReg());
1229 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1230 Binary |= 1 << ARMII::AM3_I_BitShift;
1231 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1233 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1234 Binary |= (ImmOffs & 0xF); // immedL
1240 static unsigned getAddrModeUPBits(unsigned Mode) {
1241 unsigned Binary = 0;
1243 // Set addressing mode by modifying bits U(23) and P(24)
1244 // IA - Increment after - bit U = 1 and bit P = 0
1245 // IB - Increment before - bit U = 1 and bit P = 1
1246 // DA - Decrement after - bit U = 0 and bit P = 0
1247 // DB - Decrement before - bit U = 0 and bit P = 1
1249 default: llvm_unreachable("Unknown addressing sub-mode!");
1250 case ARM_AM::da: break;
1251 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1252 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1253 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1259 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1260 const MCInstrDesc &MCID = MI.getDesc();
1261 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1263 // Part of binary is determined by TableGn.
1264 unsigned Binary = getBinaryCodeForInstr(MI);
1266 // Set the conditional execution predicate
1267 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1269 // Skip operand 0 of an instruction with base register update.
1274 // Set base address operand
1275 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1277 // Set addressing mode by modifying bits U(23) and P(24)
1278 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1279 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1283 Binary |= 0x1 << ARMII::W_BitShift;
1286 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1287 const MachineOperand &MO = MI.getOperand(i);
1288 if (!MO.isReg() || MO.isImplicit())
1290 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1291 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1293 Binary |= 0x1 << RegNum;
1299 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1300 const MCInstrDesc &MCID = MI.getDesc();
1302 // Part of binary is determined by TableGn.
1303 unsigned Binary = getBinaryCodeForInstr(MI);
1305 // Set the conditional execution predicate
1306 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1308 // Encode S bit if MI modifies CPSR.
1309 Binary |= getAddrModeSBit(MI, MCID);
1311 // 32x32->64bit operations have two destination registers. The number
1312 // of register definitions will tell us if that's what we're dealing with.
1314 if (MCID.getNumDefs() == 2)
1315 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1318 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1321 Binary |= getMachineOpValue(MI, OpIdx++);
1324 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1326 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1327 // it as Rn (for multiply, that's in the same offset as RdLo.
1328 if (MCID.getNumOperands() > OpIdx &&
1329 !MCID.OpInfo[OpIdx].isPredicate() &&
1330 !MCID.OpInfo[OpIdx].isOptionalDef())
1331 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1336 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1337 const MCInstrDesc &MCID = MI.getDesc();
1339 // Part of binary is determined by TableGn.
1340 unsigned Binary = getBinaryCodeForInstr(MI);
1342 // Set the conditional execution predicate
1343 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1348 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1350 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1351 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1353 // Two register operand form.
1355 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1358 Binary |= getMachineOpValue(MI, MO2);
1361 Binary |= getMachineOpValue(MI, MO1);
1364 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1365 if (MI.getOperand(OpIdx).isImm() &&
1366 !MCID.OpInfo[OpIdx].isPredicate() &&
1367 !MCID.OpInfo[OpIdx].isOptionalDef())
1368 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1373 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1374 const MCInstrDesc &MCID = MI.getDesc();
1376 // Part of binary is determined by TableGn.
1377 unsigned Binary = getBinaryCodeForInstr(MI);
1379 // Set the conditional execution predicate
1380 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1382 // PKH instructions are finished at this point
1383 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1391 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1393 const MachineOperand &MO = MI.getOperand(OpIdx++);
1394 if (OpIdx == MCID.getNumOperands() ||
1395 MCID.OpInfo[OpIdx].isPredicate() ||
1396 MCID.OpInfo[OpIdx].isOptionalDef()) {
1397 // Encode Rm and it's done.
1398 Binary |= getMachineOpValue(MI, MO);
1404 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1407 Binary |= getMachineOpValue(MI, OpIdx++);
1409 // Encode shift_imm.
1410 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1411 if (MCID.Opcode == ARM::PKHTB) {
1412 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1416 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1417 Binary |= ShiftAmt << ARMII::ShiftShift;
1422 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1423 const MCInstrDesc &MCID = MI.getDesc();
1425 // Part of binary is determined by TableGen.
1426 unsigned Binary = getBinaryCodeForInstr(MI);
1428 // Set the conditional execution predicate
1429 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1432 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1434 // Encode saturate bit position.
1435 unsigned Pos = MI.getOperand(1).getImm();
1436 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1438 assert((Pos < 16 || (Pos < 32 &&
1439 MCID.Opcode != ARM::SSAT16 &&
1440 MCID.Opcode != ARM::USAT16)) &&
1441 "saturate bit position out of range");
1442 Binary |= Pos << 16;
1445 Binary |= getMachineOpValue(MI, 2);
1447 // Encode shift_imm.
1448 if (MCID.getNumOperands() == 4) {
1449 unsigned ShiftOp = MI.getOperand(3).getImm();
1450 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1451 if (Opc == ARM_AM::asr)
1453 unsigned ShiftAmt = MI.getOperand(3).getImm();
1454 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1456 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1457 Binary |= ShiftAmt << ARMII::ShiftShift;
1463 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1464 const MCInstrDesc &MCID = MI.getDesc();
1466 if (MCID.Opcode == ARM::TPsoft) {
1467 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1470 // Part of binary is determined by TableGn.
1471 unsigned Binary = getBinaryCodeForInstr(MI);
1473 // Set the conditional execution predicate
1474 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1476 // Set signed_immed_24 field
1477 Binary |= getMachineOpValue(MI, 0);
1482 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1483 // Remember the base address of the inline jump table.
1484 uintptr_t JTBase = MCE.getCurrentPCValue();
1485 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1486 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1489 // Now emit the jump table entries.
1490 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1491 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1493 // DestBB address - JT base.
1494 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1496 // Absolute DestBB address.
1497 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1502 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1503 const MCInstrDesc &MCID = MI.getDesc();
1505 // Handle jump tables.
1506 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1507 // First emit a ldr pc, [] instruction.
1508 emitDataProcessingInstruction(MI, ARM::PC);
1510 // Then emit the inline jump table.
1512 (MCID.Opcode == ARM::BR_JTr)
1513 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1514 emitInlineJumpTable(JTIndex);
1516 } else if (MCID.Opcode == ARM::BR_JTm) {
1517 // First emit a ldr pc, [] instruction.
1518 emitLoadStoreInstruction(MI, ARM::PC);
1520 // Then emit the inline jump table.
1521 emitInlineJumpTable(MI.getOperand(3).getIndex());
1525 // Part of binary is determined by TableGn.
1526 unsigned Binary = getBinaryCodeForInstr(MI);
1528 // Set the conditional execution predicate
1529 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1531 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1532 // The return register is LR.
1533 Binary |= getARMRegisterNumbering(ARM::LR);
1535 // otherwise, set the return register
1536 Binary |= getMachineOpValue(MI, 0);
1541 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1542 unsigned RegD = MI.getOperand(OpIdx).getReg();
1543 unsigned Binary = 0;
1544 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1545 RegD = getARMRegisterNumbering(RegD);
1547 Binary |= RegD << ARMII::RegRdShift;
1549 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1550 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1555 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1556 unsigned RegN = MI.getOperand(OpIdx).getReg();
1557 unsigned Binary = 0;
1558 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1559 RegN = getARMRegisterNumbering(RegN);
1561 Binary |= RegN << ARMII::RegRnShift;
1563 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1564 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1569 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1570 unsigned RegM = MI.getOperand(OpIdx).getReg();
1571 unsigned Binary = 0;
1572 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1573 RegM = getARMRegisterNumbering(RegM);
1577 Binary |= ((RegM & 0x1E) >> 1);
1578 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1583 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1584 const MCInstrDesc &MCID = MI.getDesc();
1586 // Part of binary is determined by TableGn.
1587 unsigned Binary = getBinaryCodeForInstr(MI);
1589 // Set the conditional execution predicate
1590 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1593 assert((Binary & ARMII::D_BitShift) == 0 &&
1594 (Binary & ARMII::N_BitShift) == 0 &&
1595 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1598 Binary |= encodeVFPRd(MI, OpIdx++);
1600 // If this is a two-address operand, skip it, e.g. FMACD.
1601 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1605 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1606 Binary |= encodeVFPRn(MI, OpIdx++);
1608 if (OpIdx == MCID.getNumOperands() ||
1609 MCID.OpInfo[OpIdx].isPredicate() ||
1610 MCID.OpInfo[OpIdx].isOptionalDef()) {
1611 // FCMPEZD etc. has only one operand.
1617 Binary |= encodeVFPRm(MI, OpIdx);
1622 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1623 const MCInstrDesc &MCID = MI.getDesc();
1624 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1626 // Part of binary is determined by TableGn.
1627 unsigned Binary = getBinaryCodeForInstr(MI);
1629 // Set the conditional execution predicate
1630 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1634 case ARMII::VFPConv1Frm:
1635 case ARMII::VFPConv2Frm:
1636 case ARMII::VFPConv3Frm:
1638 Binary |= encodeVFPRd(MI, 0);
1640 case ARMII::VFPConv4Frm:
1642 Binary |= encodeVFPRn(MI, 0);
1644 case ARMII::VFPConv5Frm:
1646 Binary |= encodeVFPRm(MI, 0);
1652 case ARMII::VFPConv1Frm:
1654 Binary |= encodeVFPRm(MI, 1);
1656 case ARMII::VFPConv2Frm:
1657 case ARMII::VFPConv3Frm:
1659 Binary |= encodeVFPRn(MI, 1);
1661 case ARMII::VFPConv4Frm:
1662 case ARMII::VFPConv5Frm:
1664 Binary |= encodeVFPRd(MI, 1);
1668 if (Form == ARMII::VFPConv5Frm)
1670 Binary |= encodeVFPRn(MI, 2);
1671 else if (Form == ARMII::VFPConv3Frm)
1673 Binary |= encodeVFPRm(MI, 2);
1678 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1679 // Part of binary is determined by TableGn.
1680 unsigned Binary = getBinaryCodeForInstr(MI);
1682 // Set the conditional execution predicate
1683 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1688 Binary |= encodeVFPRd(MI, OpIdx++);
1690 // Encode address base.
1691 const MachineOperand &Base = MI.getOperand(OpIdx++);
1692 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1694 // If there is a non-zero immediate offset, encode it.
1696 const MachineOperand &Offset = MI.getOperand(OpIdx);
1697 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1698 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1699 Binary |= 1 << ARMII::U_BitShift;
1706 // If immediate offset is omitted, default to +0.
1707 Binary |= 1 << ARMII::U_BitShift;
1713 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1714 const MCInstrDesc &MCID = MI.getDesc();
1715 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1717 // Part of binary is determined by TableGn.
1718 unsigned Binary = getBinaryCodeForInstr(MI);
1720 // Set the conditional execution predicate
1721 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1723 // Skip operand 0 of an instruction with base register update.
1728 // Set base address operand
1729 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1731 // Set addressing mode by modifying bits U(23) and P(24)
1732 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1733 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1737 Binary |= 0x1 << ARMII::W_BitShift;
1739 // First register is encoded in Dd.
1740 Binary |= encodeVFPRd(MI, OpIdx+2);
1742 // Count the number of registers.
1743 unsigned NumRegs = 1;
1744 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1745 const MachineOperand &MO = MI.getOperand(i);
1746 if (!MO.isReg() || MO.isImplicit())
1750 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1751 // Otherwise, it will be 0, in the case of 32-bit registers.
1753 Binary |= NumRegs * 2;
1760 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1761 unsigned RegD = MI.getOperand(OpIdx).getReg();
1762 unsigned Binary = 0;
1763 RegD = getARMRegisterNumbering(RegD);
1764 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1765 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1769 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1770 unsigned RegN = MI.getOperand(OpIdx).getReg();
1771 unsigned Binary = 0;
1772 RegN = getARMRegisterNumbering(RegN);
1773 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1774 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1778 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1779 unsigned RegM = MI.getOperand(OpIdx).getReg();
1780 unsigned Binary = 0;
1781 RegM = getARMRegisterNumbering(RegM);
1782 Binary |= (RegM & 0xf);
1783 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1787 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1788 /// data-processing instruction to the corresponding Thumb encoding.
1789 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1790 assert((Binary & 0xfe000000) == 0xf2000000 &&
1791 "not an ARM NEON data-processing instruction");
1792 unsigned UBit = (Binary >> 24) & 1;
1793 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1796 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1797 unsigned Binary = getBinaryCodeForInstr(MI);
1799 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1800 const MCInstrDesc &MCID = MI.getDesc();
1801 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1805 } else { // ARMII::NSetLnFrm
1811 // Set the conditional execution predicate
1812 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1814 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1815 RegT = getARMRegisterNumbering(RegT);
1816 Binary |= (RegT << ARMII::RegRdShift);
1817 Binary |= encodeNEONRn(MI, RegNOpIdx);
1820 if ((Binary & (1 << 22)) != 0)
1821 LaneShift = 0; // 8-bit elements
1822 else if ((Binary & (1 << 5)) != 0)
1823 LaneShift = 1; // 16-bit elements
1825 LaneShift = 2; // 32-bit elements
1827 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1828 unsigned Opc1 = Lane >> 2;
1829 unsigned Opc2 = Lane & 3;
1830 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1831 Binary |= (Opc1 << 21);
1832 Binary |= (Opc2 << 5);
1837 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1838 unsigned Binary = getBinaryCodeForInstr(MI);
1840 // Set the conditional execution predicate
1841 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1843 unsigned RegT = MI.getOperand(1).getReg();
1844 RegT = getARMRegisterNumbering(RegT);
1845 Binary |= (RegT << ARMII::RegRdShift);
1846 Binary |= encodeNEONRn(MI, 0);
1850 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1851 unsigned Binary = getBinaryCodeForInstr(MI);
1852 // Destination register is encoded in Dd.
1853 Binary |= encodeNEONRd(MI, 0);
1854 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1855 unsigned Imm = MI.getOperand(1).getImm();
1856 unsigned Op = (Imm >> 12) & 1;
1857 unsigned Cmode = (Imm >> 8) & 0xf;
1858 unsigned I = (Imm >> 7) & 1;
1859 unsigned Imm3 = (Imm >> 4) & 0x7;
1860 unsigned Imm4 = Imm & 0xf;
1861 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1863 Binary = convertNEONDataProcToThumb(Binary);
1867 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1868 const MCInstrDesc &MCID = MI.getDesc();
1869 unsigned Binary = getBinaryCodeForInstr(MI);
1870 // Destination register is encoded in Dd; source register in Dm.
1872 Binary |= encodeNEONRd(MI, OpIdx++);
1873 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1875 Binary |= encodeNEONRm(MI, OpIdx);
1877 Binary = convertNEONDataProcToThumb(Binary);
1878 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1882 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1883 const MCInstrDesc &MCID = MI.getDesc();
1884 unsigned Binary = getBinaryCodeForInstr(MI);
1885 // Destination register is encoded in Dd; source registers in Dn and Dm.
1887 Binary |= encodeNEONRd(MI, OpIdx++);
1888 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1890 Binary |= encodeNEONRn(MI, OpIdx++);
1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1893 Binary |= encodeNEONRm(MI, OpIdx);
1895 Binary = convertNEONDataProcToThumb(Binary);
1896 // FIXME: This does not handle VMOVDneon or VMOVQ.
1900 #include "ARMGenCodeEmitter.inc"