1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
200 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
212 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
215 unsigned Op) const { return 0; }
216 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
218 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
221 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
224 // {12} = (U)nsigned (add == '1', sub == '0')
226 const MachineOperand &MO = MI.getOperand(Op);
227 const MachineOperand &MO1 = MI.getOperand(Op + 1);
229 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
232 unsigned Reg = getARMRegisterNumbering(MO.getReg());
233 int32_t Imm12 = MO1.getImm();
235 Binary = Imm12 & 0xfff;
238 Binary |= (Reg << 13);
242 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
246 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
248 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
250 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
252 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
254 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
256 uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op)
258 uint32_t getAddrModeS2OpValue(const MachineInstr &MI, unsigned Op)
260 uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op)
262 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
264 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
266 // {12} = (U)nsigned (add == '1', sub == '0')
268 const MachineOperand &MO = MI.getOperand(Op);
269 const MachineOperand &MO1 = MI.getOperand(Op + 1);
271 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
274 unsigned Reg = getARMRegisterNumbering(MO.getReg());
275 int32_t Imm12 = MO1.getImm();
277 // Special value for #-0
278 if (Imm12 == INT32_MIN)
281 // Immediate is always encoded as positive. The 'U' bit controls add vs
289 uint32_t Binary = Imm12 & 0xfff;
292 Binary |= (Reg << 13);
295 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
298 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
301 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
302 /// machine operand requires relocation, record the relocation and return
304 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
307 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
309 unsigned getShiftOp(unsigned Imm) const ;
311 /// Routines that handle operands which add machine relocations which are
312 /// fixed up by the relocation stage.
313 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
314 bool MayNeedFarStub, bool Indirect,
315 intptr_t ACPV = 0) const;
316 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
317 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
318 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
319 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
320 intptr_t JTBase = 0) const;
324 char ARMCodeEmitter::ID = 0;
326 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
327 /// code to the specified MCE object.
328 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
329 JITCodeEmitter &JCE) {
330 return new ARMCodeEmitter(TM, JCE);
333 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
334 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
335 MF.getTarget().getRelocationModel() != Reloc::Static) &&
336 "JIT relocation model must be set to static or default!");
337 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
338 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
339 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
340 Subtarget = &TM.getSubtarget<ARMSubtarget>();
341 MCPEs = &MF.getConstantPool()->getConstants();
343 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
344 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
345 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
346 JTI->Initialize(MF, IsPIC);
347 MMI = &getAnalysis<MachineModuleInfo>();
348 MCE.setModuleInfo(MMI);
351 DEBUG(errs() << "JITTing function '"
352 << MF.getFunction()->getName() << "'\n");
353 MCE.startFunction(MF);
354 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
356 MCE.StartMachineBasicBlock(MBB);
357 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
361 } while (MCE.finishFunction(MF));
366 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
368 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
369 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
370 default: llvm_unreachable("Unknown shift opc!");
371 case ARM_AM::asr: return 2;
372 case ARM_AM::lsl: return 0;
373 case ARM_AM::lsr: return 1;
375 case ARM_AM::rrx: return 3;
380 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
381 /// machine operand requires relocation, record the relocation and return zero.
382 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
383 const MachineOperand &MO,
385 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
386 && "Relocation to this function should be for movt or movw");
389 return static_cast<unsigned>(MO.getImm());
390 else if (MO.isGlobal())
391 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
392 else if (MO.isSymbol())
393 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
395 emitMachineBasicBlock(MO.getMBB(), Reloc);
400 llvm_unreachable("Unsupported operand type for movw/movt");
405 /// getMachineOpValue - Return binary encoding of operand. If the machine
406 /// operand requires relocation, record the relocation and return zero.
407 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
408 const MachineOperand &MO) const {
410 return getARMRegisterNumbering(MO.getReg());
412 return static_cast<unsigned>(MO.getImm());
413 else if (MO.isGlobal())
414 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
415 else if (MO.isSymbol())
416 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
417 else if (MO.isCPI()) {
418 const TargetInstrDesc &TID = MI.getDesc();
419 // For VFP load, the immediate offset is multiplied by 4.
420 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
421 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
422 emitConstPoolAddress(MO.getIndex(), Reloc);
423 } else if (MO.isJTI())
424 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
426 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
428 llvm_unreachable("Unable to encode MachineOperand!");
432 /// emitGlobalAddress - Emit the specified address to the code stream.
434 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
435 bool MayNeedFarStub, bool Indirect,
436 intptr_t ACPV) const {
437 MachineRelocation MR = Indirect
438 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
439 const_cast<GlobalValue *>(GV),
440 ACPV, MayNeedFarStub)
441 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
442 const_cast<GlobalValue *>(GV), ACPV,
444 MCE.addRelocation(MR);
447 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
448 /// be emitted to the current location in the function, and allow it to be PC
450 void ARMCodeEmitter::
451 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
452 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
456 /// emitConstPoolAddress - Arrange for the address of an constant pool
457 /// to be emitted to the current location in the function, and allow it to be PC
459 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
460 // Tell JIT emitter we'll resolve the address.
461 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
462 Reloc, CPI, 0, true));
465 /// emitJumpTableAddress - Arrange for the address of a jump table to
466 /// be emitted to the current location in the function, and allow it to be PC
468 void ARMCodeEmitter::
469 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
470 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
471 Reloc, JTIndex, 0, true));
474 /// emitMachineBasicBlock - Emit the specified address basic block.
475 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
477 intptr_t JTBase) const {
478 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
482 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
483 DEBUG(errs() << " 0x";
484 errs().write_hex(Binary) << "\n");
485 MCE.emitWordLE(Binary);
488 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
489 DEBUG(errs() << " 0x";
490 errs().write_hex(Binary) << "\n");
491 MCE.emitDWordLE(Binary);
494 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
495 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
497 MCE.processDebugLoc(MI.getDebugLoc(), true);
499 ++NumEmitted; // Keep track of the # of mi's emitted
500 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
502 llvm_unreachable("Unhandled instruction encoding format!");
506 if (MI.getOpcode() == ARM::LEApcrelJT) {
507 // Materialize jumptable address.
508 emitLEApcrelJTInstruction(MI);
511 llvm_unreachable("Unhandled instruction encoding!");
514 emitPseudoInstruction(MI);
517 case ARMII::DPSoRegFrm:
518 emitDataProcessingInstruction(MI);
522 emitLoadStoreInstruction(MI);
524 case ARMII::LdMiscFrm:
525 case ARMII::StMiscFrm:
526 emitMiscLoadStoreInstruction(MI);
528 case ARMII::LdStMulFrm:
529 emitLoadStoreMultipleInstruction(MI);
532 emitMulFrmInstruction(MI);
535 emitExtendInstruction(MI);
537 case ARMII::ArithMiscFrm:
538 emitMiscArithInstruction(MI);
541 emitSaturateInstruction(MI);
544 emitBranchInstruction(MI);
546 case ARMII::BrMiscFrm:
547 emitMiscBranchInstruction(MI);
550 case ARMII::VFPUnaryFrm:
551 case ARMII::VFPBinaryFrm:
552 emitVFPArithInstruction(MI);
554 case ARMII::VFPConv1Frm:
555 case ARMII::VFPConv2Frm:
556 case ARMII::VFPConv3Frm:
557 case ARMII::VFPConv4Frm:
558 case ARMII::VFPConv5Frm:
559 emitVFPConversionInstruction(MI);
561 case ARMII::VFPLdStFrm:
562 emitVFPLoadStoreInstruction(MI);
564 case ARMII::VFPLdStMulFrm:
565 emitVFPLoadStoreMultipleInstruction(MI);
568 // NEON instructions.
569 case ARMII::NGetLnFrm:
570 case ARMII::NSetLnFrm:
571 emitNEONLaneInstruction(MI);
574 emitNEONDupInstruction(MI);
576 case ARMII::N1RegModImmFrm:
577 emitNEON1RegModImmInstruction(MI);
579 case ARMII::N2RegFrm:
580 emitNEON2RegInstruction(MI);
582 case ARMII::N3RegFrm:
583 emitNEON3RegInstruction(MI);
586 MCE.processDebugLoc(MI.getDebugLoc(), false);
589 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
590 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
591 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
592 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
594 // Remember the CONSTPOOL_ENTRY address for later relocation.
595 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
597 // Emit constpool island entry. In most cases, the actual values will be
598 // resolved and relocated after code emission.
599 if (MCPE.isMachineConstantPoolEntry()) {
600 ARMConstantPoolValue *ACPV =
601 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
603 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
604 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
606 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
607 const GlobalValue *GV = ACPV->getGV();
609 Reloc::Model RelocM = TM.getRelocationModel();
610 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
612 Subtarget->GVIsIndirectSymbol(GV, RelocM),
615 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
619 const Constant *CV = MCPE.Val.ConstVal;
622 errs() << " ** Constant pool #" << CPI << " @ "
623 << (void*)MCE.getCurrentPCValue() << " ";
624 if (const Function *F = dyn_cast<Function>(CV))
625 errs() << F->getName();
631 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
632 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
634 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
635 uint32_t Val = uint32_t(*CI->getValue().getRawData());
637 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
638 if (CFP->getType()->isFloatTy())
639 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
640 else if (CFP->getType()->isDoubleTy())
641 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
643 llvm_unreachable("Unable to handle this constantpool entry!");
646 llvm_unreachable("Unable to handle this constantpool entry!");
651 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
652 const MachineOperand &MO0 = MI.getOperand(0);
653 const MachineOperand &MO1 = MI.getOperand(1);
655 // Emit the 'movw' instruction.
656 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
658 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
660 // Set the conditional execution predicate.
661 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
664 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
666 // Encode imm16 as imm4:imm12
667 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
668 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
671 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
672 // Emit the 'movt' instruction.
673 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
675 // Set the conditional execution predicate.
676 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
679 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
681 // Encode imm16 as imm4:imm1, same as movw above.
682 Binary |= Hi16 & 0xFFF;
683 Binary |= ((Hi16 >> 12) & 0xF) << 16;
687 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
688 const MachineOperand &MO0 = MI.getOperand(0);
689 const MachineOperand &MO1 = MI.getOperand(1);
690 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
691 "Not a valid so_imm value!");
692 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
693 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
695 // Emit the 'mov' instruction.
696 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
698 // Set the conditional execution predicate.
699 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
702 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
705 // Set bit I(25) to identify this is the immediate form of <shifter_op>
706 Binary |= 1 << ARMII::I_BitShift;
707 Binary |= getMachineSoImmOpValue(V1);
710 // Now the 'orr' instruction.
711 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
713 // Set the conditional execution predicate.
714 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
717 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
720 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
723 // Set bit I(25) to identify this is the immediate form of <shifter_op>
724 Binary |= 1 << ARMII::I_BitShift;
725 Binary |= getMachineSoImmOpValue(V2);
729 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
730 // It's basically add r, pc, (LJTI - $+8)
732 const TargetInstrDesc &TID = MI.getDesc();
734 // Emit the 'add' instruction.
735 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
737 // Set the conditional execution predicate
738 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
740 // Encode S bit if MI modifies CPSR.
741 Binary |= getAddrModeSBit(MI, TID);
744 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
746 // Encode Rn which is PC.
747 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
749 // Encode the displacement.
750 Binary |= 1 << ARMII::I_BitShift;
751 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
756 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
757 unsigned Opcode = MI.getDesc().Opcode;
759 // Part of binary is determined by TableGn.
760 unsigned Binary = getBinaryCodeForInstr(MI);
762 // Set the conditional execution predicate
763 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
765 // Encode S bit if MI modifies CPSR.
766 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
767 Binary |= 1 << ARMII::S_BitShift;
769 // Encode register def if there is one.
770 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
772 // Encode the shift operation.
779 case ARM::MOVsrl_flag:
781 Binary |= (0x2 << 4) | (1 << 7);
783 case ARM::MOVsra_flag:
785 Binary |= (0x4 << 4) | (1 << 7);
789 // Encode register Rm.
790 Binary |= getMachineOpValue(MI, 1);
795 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
796 DEBUG(errs() << " ** LPC" << LabelID << " @ "
797 << (void*)MCE.getCurrentPCValue() << '\n');
798 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
801 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
802 unsigned Opcode = MI.getDesc().Opcode;
805 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
807 case ARM::BMOVPCRX_CALL:
809 case ARM::BMOVPCRXr9_CALL: {
810 // First emit mov lr, pc
811 unsigned Binary = 0x01a0e00f;
812 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
815 // and then emit the branch.
816 emitMiscBranchInstruction(MI);
819 case TargetOpcode::INLINEASM: {
820 // We allow inline assembler nodes with empty bodies - they can
821 // implicitly define registers, which is ok for JIT.
822 if (MI.getOperand(0).getSymbolName()[0]) {
823 report_fatal_error("JIT does not support inline asm!");
827 case TargetOpcode::PROLOG_LABEL:
828 case TargetOpcode::EH_LABEL:
829 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
831 case TargetOpcode::IMPLICIT_DEF:
832 case TargetOpcode::KILL:
835 case ARM::CONSTPOOL_ENTRY:
836 emitConstPoolInstruction(MI);
839 // Remember of the address of the PC label for relocation later.
840 addPCLabel(MI.getOperand(2).getImm());
841 // PICADD is just an add instruction that implicitly read pc.
842 emitDataProcessingInstruction(MI, 0, ARM::PC);
849 // Remember of the address of the PC label for relocation later.
850 addPCLabel(MI.getOperand(2).getImm());
851 // These are just load / store instructions that implicitly read pc.
852 emitLoadStoreInstruction(MI, 0, ARM::PC);
859 // Remember of the address of the PC label for relocation later.
860 addPCLabel(MI.getOperand(2).getImm());
861 // These are just load / store instructions that implicitly read pc.
862 emitMiscLoadStoreInstruction(MI, ARM::PC);
867 // Two instructions to materialize a constant.
868 if (Subtarget->hasV6T2Ops())
869 emitMOVi32immInstruction(MI);
871 emitMOVi2piecesInstruction(MI);
874 case ARM::LEApcrelJT:
875 // Materialize jumptable address.
876 emitLEApcrelJTInstruction(MI);
879 case ARM::MOVsrl_flag:
880 case ARM::MOVsra_flag:
881 emitPseudoMoveInstruction(MI);
886 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
887 const TargetInstrDesc &TID,
888 const MachineOperand &MO,
890 unsigned Binary = getMachineOpValue(MI, MO);
892 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
893 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
894 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
896 // Encode the shift opcode.
898 unsigned Rs = MO1.getReg();
900 // Set shift operand (bit[7:4]).
905 // RRX - 0110 and bit[11:8] clear.
907 default: llvm_unreachable("Unknown shift opc!");
908 case ARM_AM::lsl: SBits = 0x1; break;
909 case ARM_AM::lsr: SBits = 0x3; break;
910 case ARM_AM::asr: SBits = 0x5; break;
911 case ARM_AM::ror: SBits = 0x7; break;
912 case ARM_AM::rrx: SBits = 0x6; break;
915 // Set shift operand (bit[6:4]).
921 default: llvm_unreachable("Unknown shift opc!");
922 case ARM_AM::lsl: SBits = 0x0; break;
923 case ARM_AM::lsr: SBits = 0x2; break;
924 case ARM_AM::asr: SBits = 0x4; break;
925 case ARM_AM::ror: SBits = 0x6; break;
928 Binary |= SBits << 4;
929 if (SOpc == ARM_AM::rrx)
932 // Encode the shift operation Rs or shift_imm (except rrx).
934 // Encode Rs bit[11:8].
935 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
936 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
939 // Encode shift_imm bit[11:7].
940 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
943 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
944 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
945 assert(SoImmVal != -1 && "Not a valid so_imm value!");
947 // Encode rotate_imm.
948 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
949 << ARMII::SoRotImmShift;
952 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
956 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
957 const TargetInstrDesc &TID) const {
958 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
959 const MachineOperand &MO = MI.getOperand(i-1);
960 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
961 return 1 << ARMII::S_BitShift;
966 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
968 unsigned ImplicitRn) {
969 const TargetInstrDesc &TID = MI.getDesc();
971 // Part of binary is determined by TableGn.
972 unsigned Binary = getBinaryCodeForInstr(MI);
974 // Set the conditional execution predicate
975 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
977 // Encode S bit if MI modifies CPSR.
978 Binary |= getAddrModeSBit(MI, TID);
980 // Encode register def if there is one.
981 unsigned NumDefs = TID.getNumDefs();
984 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
986 // Special handling for implicit use (e.g. PC).
987 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
989 if (TID.Opcode == ARM::MOVi16) {
990 // Get immediate from MI.
991 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
992 ARM::reloc_arm_movw);
993 // Encode imm which is the same as in emitMOVi32immInstruction().
994 Binary |= Lo16 & 0xFFF;
995 Binary |= ((Lo16 >> 12) & 0xF) << 16;
998 } else if(TID.Opcode == ARM::MOVTi16) {
999 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1000 ARM::reloc_arm_movt) >> 16);
1001 Binary |= Hi16 & 0xFFF;
1002 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1005 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1006 uint32_t v = ~MI.getOperand(2).getImm();
1007 int32_t lsb = CountTrailingZeros_32(v);
1008 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1009 // Instr{20-16} = msb, Instr{11-7} = lsb
1010 Binary |= (msb & 0x1F) << 16;
1011 Binary |= (lsb & 0x1F) << 7;
1014 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1015 // Encode Rn in Instr{0-3}
1016 Binary |= getMachineOpValue(MI, OpIdx++);
1018 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1019 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1021 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1022 Binary |= (widthm1 & 0x1F) << 16;
1023 Binary |= (lsb & 0x1F) << 7;
1028 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1029 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1032 // Encode first non-shifter register operand if there is one.
1033 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1036 // Special handling for implicit use (e.g. PC).
1037 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1039 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1044 // Encode shifter operand.
1045 const MachineOperand &MO = MI.getOperand(OpIdx);
1046 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1048 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1053 // Encode register Rm.
1054 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1059 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1064 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1065 unsigned ImplicitRd,
1066 unsigned ImplicitRn) {
1067 const TargetInstrDesc &TID = MI.getDesc();
1068 unsigned Form = TID.TSFlags & ARMII::FormMask;
1069 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1071 // Part of binary is determined by TableGn.
1072 unsigned Binary = getBinaryCodeForInstr(MI);
1074 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1075 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1076 MI.getOpcode() == ARM::STRi12) {
1081 // Set the conditional execution predicate
1082 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1086 // Operand 0 of a pre- and post-indexed store is the address base
1087 // writeback. Skip it.
1088 bool Skipped = false;
1089 if (IsPrePost && Form == ARMII::StFrm) {
1094 // Set first operand
1096 // Special handling for implicit use (e.g. PC).
1097 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1099 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1101 // Set second operand
1103 // Special handling for implicit use (e.g. PC).
1104 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1106 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1108 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1109 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1112 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1113 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1114 ? 0 : MI.getOperand(OpIdx+1).getImm();
1116 // Set bit U(23) according to sign of immed value (positive or negative).
1117 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1119 if (!MO2.getReg()) { // is immediate
1120 if (ARM_AM::getAM2Offset(AM2Opc))
1121 // Set the value of offset_12 field
1122 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1127 // Set bit I(25), because this is not in immediate encoding.
1128 Binary |= 1 << ARMII::I_BitShift;
1129 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1130 // Set bit[3:0] to the corresponding Rm register
1131 Binary |= getARMRegisterNumbering(MO2.getReg());
1133 // If this instr is in scaled register offset/index instruction, set
1134 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1135 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1136 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1137 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1143 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1144 unsigned ImplicitRn) {
1145 const TargetInstrDesc &TID = MI.getDesc();
1146 unsigned Form = TID.TSFlags & ARMII::FormMask;
1147 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1149 // Part of binary is determined by TableGn.
1150 unsigned Binary = getBinaryCodeForInstr(MI);
1152 // Set the conditional execution predicate
1153 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1157 // Operand 0 of a pre- and post-indexed store is the address base
1158 // writeback. Skip it.
1159 bool Skipped = false;
1160 if (IsPrePost && Form == ARMII::StMiscFrm) {
1165 // Set first operand
1166 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1168 // Skip LDRD and STRD's second operand.
1169 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1172 // Set second operand
1174 // Special handling for implicit use (e.g. PC).
1175 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1177 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1179 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1180 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1183 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1184 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1185 ? 0 : MI.getOperand(OpIdx+1).getImm();
1187 // Set bit U(23) according to sign of immed value (positive or negative)
1188 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1191 // If this instr is in register offset/index encoding, set bit[3:0]
1192 // to the corresponding Rm register.
1194 Binary |= getARMRegisterNumbering(MO2.getReg());
1199 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1200 Binary |= 1 << ARMII::AM3_I_BitShift;
1201 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1203 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1204 Binary |= (ImmOffs & 0xF); // immedL
1210 static unsigned getAddrModeUPBits(unsigned Mode) {
1211 unsigned Binary = 0;
1213 // Set addressing mode by modifying bits U(23) and P(24)
1214 // IA - Increment after - bit U = 1 and bit P = 0
1215 // IB - Increment before - bit U = 1 and bit P = 1
1216 // DA - Decrement after - bit U = 0 and bit P = 0
1217 // DB - Decrement before - bit U = 0 and bit P = 1
1219 default: llvm_unreachable("Unknown addressing sub-mode!");
1220 case ARM_AM::da: break;
1221 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1222 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1223 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1229 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1230 const TargetInstrDesc &TID = MI.getDesc();
1231 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1233 // Part of binary is determined by TableGn.
1234 unsigned Binary = getBinaryCodeForInstr(MI);
1236 // Set the conditional execution predicate
1237 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1239 // Skip operand 0 of an instruction with base register update.
1244 // Set base address operand
1245 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1247 // Set addressing mode by modifying bits U(23) and P(24)
1248 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1249 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1253 Binary |= 0x1 << ARMII::W_BitShift;
1256 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1257 const MachineOperand &MO = MI.getOperand(i);
1258 if (!MO.isReg() || MO.isImplicit())
1260 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1261 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1263 Binary |= 0x1 << RegNum;
1269 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1270 const TargetInstrDesc &TID = MI.getDesc();
1272 // Part of binary is determined by TableGn.
1273 unsigned Binary = getBinaryCodeForInstr(MI);
1275 // Set the conditional execution predicate
1276 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1278 // Encode S bit if MI modifies CPSR.
1279 Binary |= getAddrModeSBit(MI, TID);
1281 // 32x32->64bit operations have two destination registers. The number
1282 // of register definitions will tell us if that's what we're dealing with.
1284 if (TID.getNumDefs() == 2)
1285 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1288 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1291 Binary |= getMachineOpValue(MI, OpIdx++);
1294 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1296 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1297 // it as Rn (for multiply, that's in the same offset as RdLo.
1298 if (TID.getNumOperands() > OpIdx &&
1299 !TID.OpInfo[OpIdx].isPredicate() &&
1300 !TID.OpInfo[OpIdx].isOptionalDef())
1301 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1306 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1307 const TargetInstrDesc &TID = MI.getDesc();
1309 // Part of binary is determined by TableGn.
1310 unsigned Binary = getBinaryCodeForInstr(MI);
1312 // Set the conditional execution predicate
1313 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1318 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1320 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1321 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1323 // Two register operand form.
1325 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1328 Binary |= getMachineOpValue(MI, MO2);
1331 Binary |= getMachineOpValue(MI, MO1);
1334 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1335 if (MI.getOperand(OpIdx).isImm() &&
1336 !TID.OpInfo[OpIdx].isPredicate() &&
1337 !TID.OpInfo[OpIdx].isOptionalDef())
1338 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1343 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1344 const TargetInstrDesc &TID = MI.getDesc();
1346 // Part of binary is determined by TableGn.
1347 unsigned Binary = getBinaryCodeForInstr(MI);
1349 // Set the conditional execution predicate
1350 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1355 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1357 const MachineOperand &MO = MI.getOperand(OpIdx++);
1358 if (OpIdx == TID.getNumOperands() ||
1359 TID.OpInfo[OpIdx].isPredicate() ||
1360 TID.OpInfo[OpIdx].isOptionalDef()) {
1361 // Encode Rm and it's done.
1362 Binary |= getMachineOpValue(MI, MO);
1368 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1371 Binary |= getMachineOpValue(MI, OpIdx++);
1373 // Encode shift_imm.
1374 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1375 if (TID.Opcode == ARM::PKHTB) {
1376 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1380 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1381 Binary |= ShiftAmt << ARMII::ShiftShift;
1386 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1387 const TargetInstrDesc &TID = MI.getDesc();
1389 // Part of binary is determined by TableGen.
1390 unsigned Binary = getBinaryCodeForInstr(MI);
1392 // Set the conditional execution predicate
1393 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1396 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1398 // Encode saturate bit position.
1399 unsigned Pos = MI.getOperand(1).getImm();
1400 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1402 assert((Pos < 16 || (Pos < 32 &&
1403 TID.Opcode != ARM::SSAT16 &&
1404 TID.Opcode != ARM::USAT16)) &&
1405 "saturate bit position out of range");
1406 Binary |= Pos << 16;
1409 Binary |= getMachineOpValue(MI, 2);
1411 // Encode shift_imm.
1412 if (TID.getNumOperands() == 4) {
1413 unsigned ShiftOp = MI.getOperand(3).getImm();
1414 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1415 if (Opc == ARM_AM::asr)
1417 unsigned ShiftAmt = MI.getOperand(3).getImm();
1418 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1420 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1421 Binary |= ShiftAmt << ARMII::ShiftShift;
1427 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1428 const TargetInstrDesc &TID = MI.getDesc();
1430 if (TID.Opcode == ARM::TPsoft) {
1431 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1434 // Part of binary is determined by TableGn.
1435 unsigned Binary = getBinaryCodeForInstr(MI);
1437 // Set the conditional execution predicate
1438 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1440 // Set signed_immed_24 field
1441 Binary |= getMachineOpValue(MI, 0);
1446 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1447 // Remember the base address of the inline jump table.
1448 uintptr_t JTBase = MCE.getCurrentPCValue();
1449 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1450 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1453 // Now emit the jump table entries.
1454 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1455 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1457 // DestBB address - JT base.
1458 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1460 // Absolute DestBB address.
1461 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1466 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1467 const TargetInstrDesc &TID = MI.getDesc();
1469 // Handle jump tables.
1470 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1471 // First emit a ldr pc, [] instruction.
1472 emitDataProcessingInstruction(MI, ARM::PC);
1474 // Then emit the inline jump table.
1476 (TID.Opcode == ARM::BR_JTr)
1477 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1478 emitInlineJumpTable(JTIndex);
1480 } else if (TID.Opcode == ARM::BR_JTm) {
1481 // First emit a ldr pc, [] instruction.
1482 emitLoadStoreInstruction(MI, ARM::PC);
1484 // Then emit the inline jump table.
1485 emitInlineJumpTable(MI.getOperand(3).getIndex());
1489 // Part of binary is determined by TableGn.
1490 unsigned Binary = getBinaryCodeForInstr(MI);
1492 // Set the conditional execution predicate
1493 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1495 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1496 // The return register is LR.
1497 Binary |= getARMRegisterNumbering(ARM::LR);
1499 // otherwise, set the return register
1500 Binary |= getMachineOpValue(MI, 0);
1505 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1506 unsigned RegD = MI.getOperand(OpIdx).getReg();
1507 unsigned Binary = 0;
1508 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1509 RegD = getARMRegisterNumbering(RegD);
1511 Binary |= RegD << ARMII::RegRdShift;
1513 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1514 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1519 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1520 unsigned RegN = MI.getOperand(OpIdx).getReg();
1521 unsigned Binary = 0;
1522 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1523 RegN = getARMRegisterNumbering(RegN);
1525 Binary |= RegN << ARMII::RegRnShift;
1527 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1528 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1533 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1534 unsigned RegM = MI.getOperand(OpIdx).getReg();
1535 unsigned Binary = 0;
1536 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1537 RegM = getARMRegisterNumbering(RegM);
1541 Binary |= ((RegM & 0x1E) >> 1);
1542 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1547 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1548 const TargetInstrDesc &TID = MI.getDesc();
1550 // Part of binary is determined by TableGn.
1551 unsigned Binary = getBinaryCodeForInstr(MI);
1553 // Set the conditional execution predicate
1554 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1557 assert((Binary & ARMII::D_BitShift) == 0 &&
1558 (Binary & ARMII::N_BitShift) == 0 &&
1559 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1562 Binary |= encodeVFPRd(MI, OpIdx++);
1564 // If this is a two-address operand, skip it, e.g. FMACD.
1565 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1569 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1570 Binary |= encodeVFPRn(MI, OpIdx++);
1572 if (OpIdx == TID.getNumOperands() ||
1573 TID.OpInfo[OpIdx].isPredicate() ||
1574 TID.OpInfo[OpIdx].isOptionalDef()) {
1575 // FCMPEZD etc. has only one operand.
1581 Binary |= encodeVFPRm(MI, OpIdx);
1586 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1587 const TargetInstrDesc &TID = MI.getDesc();
1588 unsigned Form = TID.TSFlags & ARMII::FormMask;
1590 // Part of binary is determined by TableGn.
1591 unsigned Binary = getBinaryCodeForInstr(MI);
1593 // Set the conditional execution predicate
1594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1598 case ARMII::VFPConv1Frm:
1599 case ARMII::VFPConv2Frm:
1600 case ARMII::VFPConv3Frm:
1602 Binary |= encodeVFPRd(MI, 0);
1604 case ARMII::VFPConv4Frm:
1606 Binary |= encodeVFPRn(MI, 0);
1608 case ARMII::VFPConv5Frm:
1610 Binary |= encodeVFPRm(MI, 0);
1616 case ARMII::VFPConv1Frm:
1618 Binary |= encodeVFPRm(MI, 1);
1620 case ARMII::VFPConv2Frm:
1621 case ARMII::VFPConv3Frm:
1623 Binary |= encodeVFPRn(MI, 1);
1625 case ARMII::VFPConv4Frm:
1626 case ARMII::VFPConv5Frm:
1628 Binary |= encodeVFPRd(MI, 1);
1632 if (Form == ARMII::VFPConv5Frm)
1634 Binary |= encodeVFPRn(MI, 2);
1635 else if (Form == ARMII::VFPConv3Frm)
1637 Binary |= encodeVFPRm(MI, 2);
1642 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1643 // Part of binary is determined by TableGn.
1644 unsigned Binary = getBinaryCodeForInstr(MI);
1646 // Set the conditional execution predicate
1647 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1652 Binary |= encodeVFPRd(MI, OpIdx++);
1654 // Encode address base.
1655 const MachineOperand &Base = MI.getOperand(OpIdx++);
1656 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1658 // If there is a non-zero immediate offset, encode it.
1660 const MachineOperand &Offset = MI.getOperand(OpIdx);
1661 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1662 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1663 Binary |= 1 << ARMII::U_BitShift;
1670 // If immediate offset is omitted, default to +0.
1671 Binary |= 1 << ARMII::U_BitShift;
1677 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1678 const TargetInstrDesc &TID = MI.getDesc();
1679 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1681 // Part of binary is determined by TableGn.
1682 unsigned Binary = getBinaryCodeForInstr(MI);
1684 // Set the conditional execution predicate
1685 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1687 // Skip operand 0 of an instruction with base register update.
1692 // Set base address operand
1693 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1695 // Set addressing mode by modifying bits U(23) and P(24)
1696 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1697 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1701 Binary |= 0x1 << ARMII::W_BitShift;
1703 // First register is encoded in Dd.
1704 Binary |= encodeVFPRd(MI, OpIdx+2);
1706 // Count the number of registers.
1707 unsigned NumRegs = 1;
1708 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1709 const MachineOperand &MO = MI.getOperand(i);
1710 if (!MO.isReg() || MO.isImplicit())
1714 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1715 // Otherwise, it will be 0, in the case of 32-bit registers.
1717 Binary |= NumRegs * 2;
1724 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1725 unsigned RegD = MI.getOperand(OpIdx).getReg();
1726 unsigned Binary = 0;
1727 RegD = getARMRegisterNumbering(RegD);
1728 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1729 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1733 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1734 unsigned RegN = MI.getOperand(OpIdx).getReg();
1735 unsigned Binary = 0;
1736 RegN = getARMRegisterNumbering(RegN);
1737 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1738 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1742 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1743 unsigned RegM = MI.getOperand(OpIdx).getReg();
1744 unsigned Binary = 0;
1745 RegM = getARMRegisterNumbering(RegM);
1746 Binary |= (RegM & 0xf);
1747 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1751 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1752 /// data-processing instruction to the corresponding Thumb encoding.
1753 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1754 assert((Binary & 0xfe000000) == 0xf2000000 &&
1755 "not an ARM NEON data-processing instruction");
1756 unsigned UBit = (Binary >> 24) & 1;
1757 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1760 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1761 unsigned Binary = getBinaryCodeForInstr(MI);
1763 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1764 const TargetInstrDesc &TID = MI.getDesc();
1765 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1769 } else { // ARMII::NSetLnFrm
1775 // Set the conditional execution predicate
1776 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1778 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1779 RegT = getARMRegisterNumbering(RegT);
1780 Binary |= (RegT << ARMII::RegRdShift);
1781 Binary |= encodeNEONRn(MI, RegNOpIdx);
1784 if ((Binary & (1 << 22)) != 0)
1785 LaneShift = 0; // 8-bit elements
1786 else if ((Binary & (1 << 5)) != 0)
1787 LaneShift = 1; // 16-bit elements
1789 LaneShift = 2; // 32-bit elements
1791 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1792 unsigned Opc1 = Lane >> 2;
1793 unsigned Opc2 = Lane & 3;
1794 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1795 Binary |= (Opc1 << 21);
1796 Binary |= (Opc2 << 5);
1801 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1802 unsigned Binary = getBinaryCodeForInstr(MI);
1804 // Set the conditional execution predicate
1805 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1807 unsigned RegT = MI.getOperand(1).getReg();
1808 RegT = getARMRegisterNumbering(RegT);
1809 Binary |= (RegT << ARMII::RegRdShift);
1810 Binary |= encodeNEONRn(MI, 0);
1814 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1815 unsigned Binary = getBinaryCodeForInstr(MI);
1816 // Destination register is encoded in Dd.
1817 Binary |= encodeNEONRd(MI, 0);
1818 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1819 unsigned Imm = MI.getOperand(1).getImm();
1820 unsigned Op = (Imm >> 12) & 1;
1821 unsigned Cmode = (Imm >> 8) & 0xf;
1822 unsigned I = (Imm >> 7) & 1;
1823 unsigned Imm3 = (Imm >> 4) & 0x7;
1824 unsigned Imm4 = Imm & 0xf;
1825 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1827 Binary = convertNEONDataProcToThumb(Binary);
1831 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1832 const TargetInstrDesc &TID = MI.getDesc();
1833 unsigned Binary = getBinaryCodeForInstr(MI);
1834 // Destination register is encoded in Dd; source register in Dm.
1836 Binary |= encodeNEONRd(MI, OpIdx++);
1837 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1839 Binary |= encodeNEONRm(MI, OpIdx);
1841 Binary = convertNEONDataProcToThumb(Binary);
1842 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1846 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1847 const TargetInstrDesc &TID = MI.getDesc();
1848 unsigned Binary = getBinaryCodeForInstr(MI);
1849 // Destination register is encoded in Dd; source registers in Dn and Dm.
1851 Binary |= encodeNEONRd(MI, OpIdx++);
1852 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1854 Binary |= encodeNEONRn(MI, OpIdx++);
1855 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1857 Binary |= encodeNEONRm(MI, OpIdx);
1859 Binary = convertNEONDataProcToThumb(Binary);
1860 // FIXME: This does not handle VMOVDneon or VMOVQ.
1864 #include "ARMGenCodeEmitter.inc"