1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
168 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
170 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
183 unsigned Op) const { return 0; }
184 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
186 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
189 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
192 // {12} = (U)nsigned (add == '1', sub == '0')
194 const MachineOperand &MO = MI.getOperand(Op);
195 const MachineOperand &MO1 = MI.getOperand(Op + 1);
197 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
200 unsigned Reg = getARMRegisterNumbering(MO.getReg());
201 int32_t Imm12 = MO1.getImm();
203 Binary = Imm12 & 0xfff;
206 Binary |= (Reg << 13);
209 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
211 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
213 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
215 // {8} = (U)nsigned (add == '1', sub == '0')
217 const MachineOperand &MO = MI.getOperand(Op);
218 const MachineOperand &MO1 = MI.getOperand(Op + 1);
220 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
223 unsigned Reg = getARMRegisterNumbering(MO.getReg());
224 int32_t Imm8 = MO1.getImm();
226 Binary = Imm8 & 0xff;
229 Binary |= (Reg << 9);
232 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
235 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
238 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
239 /// machine operand requires relocation, record the relocation and return
241 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
244 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
246 unsigned getShiftOp(unsigned Imm) const ;
248 /// Routines that handle operands which add machine relocations which are
249 /// fixed up by the relocation stage.
250 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
251 bool MayNeedFarStub, bool Indirect,
252 intptr_t ACPV = 0) const;
253 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
254 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
255 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
256 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
257 intptr_t JTBase = 0) const;
261 char ARMCodeEmitter::ID = 0;
263 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
264 /// code to the specified MCE object.
265 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
266 JITCodeEmitter &JCE) {
267 return new ARMCodeEmitter(TM, JCE);
270 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
271 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
272 MF.getTarget().getRelocationModel() != Reloc::Static) &&
273 "JIT relocation model must be set to static or default!");
274 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
275 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
276 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
277 Subtarget = &TM.getSubtarget<ARMSubtarget>();
278 MCPEs = &MF.getConstantPool()->getConstants();
280 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
281 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
282 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
283 JTI->Initialize(MF, IsPIC);
284 MMI = &getAnalysis<MachineModuleInfo>();
285 MCE.setModuleInfo(MMI);
288 DEBUG(errs() << "JITTing function '"
289 << MF.getFunction()->getName() << "'\n");
290 MCE.startFunction(MF);
291 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
293 MCE.StartMachineBasicBlock(MBB);
294 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
298 } while (MCE.finishFunction(MF));
303 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
305 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
306 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
307 default: llvm_unreachable("Unknown shift opc!");
308 case ARM_AM::asr: return 2;
309 case ARM_AM::lsl: return 0;
310 case ARM_AM::lsr: return 1;
312 case ARM_AM::rrx: return 3;
317 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
318 /// machine operand requires relocation, record the relocation and return zero.
319 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
320 const MachineOperand &MO,
322 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
323 && "Relocation to this function should be for movt or movw");
326 return static_cast<unsigned>(MO.getImm());
327 else if (MO.isGlobal())
328 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
329 else if (MO.isSymbol())
330 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
332 emitMachineBasicBlock(MO.getMBB(), Reloc);
337 llvm_unreachable("Unsupported operand type for movw/movt");
342 /// getMachineOpValue - Return binary encoding of operand. If the machine
343 /// operand requires relocation, record the relocation and return zero.
344 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
345 const MachineOperand &MO) const {
347 return getARMRegisterNumbering(MO.getReg());
349 return static_cast<unsigned>(MO.getImm());
350 else if (MO.isGlobal())
351 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
352 else if (MO.isSymbol())
353 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
354 else if (MO.isCPI()) {
355 const TargetInstrDesc &TID = MI.getDesc();
356 // For VFP load, the immediate offset is multiplied by 4.
357 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
358 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
359 emitConstPoolAddress(MO.getIndex(), Reloc);
360 } else if (MO.isJTI())
361 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
363 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
373 /// emitGlobalAddress - Emit the specified address to the code stream.
375 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
376 bool MayNeedFarStub, bool Indirect,
377 intptr_t ACPV) const {
378 MachineRelocation MR = Indirect
379 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
380 const_cast<GlobalValue *>(GV),
381 ACPV, MayNeedFarStub)
382 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
383 const_cast<GlobalValue *>(GV), ACPV,
385 MCE.addRelocation(MR);
388 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
389 /// be emitted to the current location in the function, and allow it to be PC
391 void ARMCodeEmitter::
392 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
393 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
397 /// emitConstPoolAddress - Arrange for the address of an constant pool
398 /// to be emitted to the current location in the function, and allow it to be PC
400 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
401 // Tell JIT emitter we'll resolve the address.
402 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
403 Reloc, CPI, 0, true));
406 /// emitJumpTableAddress - Arrange for the address of a jump table to
407 /// be emitted to the current location in the function, and allow it to be PC
409 void ARMCodeEmitter::
410 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
411 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
412 Reloc, JTIndex, 0, true));
415 /// emitMachineBasicBlock - Emit the specified address basic block.
416 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
418 intptr_t JTBase) const {
419 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
423 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
424 DEBUG(errs() << " 0x";
425 errs().write_hex(Binary) << "\n");
426 MCE.emitWordLE(Binary);
429 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
430 DEBUG(errs() << " 0x";
431 errs().write_hex(Binary) << "\n");
432 MCE.emitDWordLE(Binary);
435 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
436 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
438 MCE.processDebugLoc(MI.getDebugLoc(), true);
440 ++NumEmitted; // Keep track of the # of mi's emitted
441 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
443 llvm_unreachable("Unhandled instruction encoding format!");
447 emitPseudoInstruction(MI);
450 case ARMII::DPSoRegFrm:
451 emitDataProcessingInstruction(MI);
455 emitLoadStoreInstruction(MI);
457 case ARMII::LdMiscFrm:
458 case ARMII::StMiscFrm:
459 emitMiscLoadStoreInstruction(MI);
461 case ARMII::LdStMulFrm:
462 emitLoadStoreMultipleInstruction(MI);
465 emitMulFrmInstruction(MI);
468 emitExtendInstruction(MI);
470 case ARMII::ArithMiscFrm:
471 emitMiscArithInstruction(MI);
474 emitSaturateInstruction(MI);
477 emitBranchInstruction(MI);
479 case ARMII::BrMiscFrm:
480 emitMiscBranchInstruction(MI);
483 case ARMII::VFPUnaryFrm:
484 case ARMII::VFPBinaryFrm:
485 emitVFPArithInstruction(MI);
487 case ARMII::VFPConv1Frm:
488 case ARMII::VFPConv2Frm:
489 case ARMII::VFPConv3Frm:
490 case ARMII::VFPConv4Frm:
491 case ARMII::VFPConv5Frm:
492 emitVFPConversionInstruction(MI);
494 case ARMII::VFPLdStFrm:
495 emitVFPLoadStoreInstruction(MI);
497 case ARMII::VFPLdStMulFrm:
498 emitVFPLoadStoreMultipleInstruction(MI);
501 // NEON instructions.
502 case ARMII::NGetLnFrm:
503 case ARMII::NSetLnFrm:
504 emitNEONLaneInstruction(MI);
507 emitNEONDupInstruction(MI);
509 case ARMII::N1RegModImmFrm:
510 emitNEON1RegModImmInstruction(MI);
512 case ARMII::N2RegFrm:
513 emitNEON2RegInstruction(MI);
515 case ARMII::N3RegFrm:
516 emitNEON3RegInstruction(MI);
519 MCE.processDebugLoc(MI.getDebugLoc(), false);
522 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
523 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
524 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
525 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
527 // Remember the CONSTPOOL_ENTRY address for later relocation.
528 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
530 // Emit constpool island entry. In most cases, the actual values will be
531 // resolved and relocated after code emission.
532 if (MCPE.isMachineConstantPoolEntry()) {
533 ARMConstantPoolValue *ACPV =
534 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
536 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
537 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
539 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
540 const GlobalValue *GV = ACPV->getGV();
542 Reloc::Model RelocM = TM.getRelocationModel();
543 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
545 Subtarget->GVIsIndirectSymbol(GV, RelocM),
548 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
552 const Constant *CV = MCPE.Val.ConstVal;
555 errs() << " ** Constant pool #" << CPI << " @ "
556 << (void*)MCE.getCurrentPCValue() << " ";
557 if (const Function *F = dyn_cast<Function>(CV))
558 errs() << F->getName();
564 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
565 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
567 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
568 uint32_t Val = uint32_t(*CI->getValue().getRawData());
570 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
571 if (CFP->getType()->isFloatTy())
572 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
573 else if (CFP->getType()->isDoubleTy())
574 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
576 llvm_unreachable("Unable to handle this constantpool entry!");
579 llvm_unreachable("Unable to handle this constantpool entry!");
584 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
585 const MachineOperand &MO0 = MI.getOperand(0);
586 const MachineOperand &MO1 = MI.getOperand(1);
588 // Emit the 'movw' instruction.
589 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
591 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
593 // Set the conditional execution predicate.
594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
597 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
599 // Encode imm16 as imm4:imm12
600 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
601 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
604 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
605 // Emit the 'movt' instruction.
606 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
608 // Set the conditional execution predicate.
609 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
612 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
614 // Encode imm16 as imm4:imm1, same as movw above.
615 Binary |= Hi16 & 0xFFF;
616 Binary |= ((Hi16 >> 12) & 0xF) << 16;
620 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
621 const MachineOperand &MO0 = MI.getOperand(0);
622 const MachineOperand &MO1 = MI.getOperand(1);
623 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
624 "Not a valid so_imm value!");
625 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
626 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
628 // Emit the 'mov' instruction.
629 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
631 // Set the conditional execution predicate.
632 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
635 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
638 // Set bit I(25) to identify this is the immediate form of <shifter_op>
639 Binary |= 1 << ARMII::I_BitShift;
640 Binary |= getMachineSoImmOpValue(V1);
643 // Now the 'orr' instruction.
644 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
646 // Set the conditional execution predicate.
647 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
650 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
653 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
656 // Set bit I(25) to identify this is the immediate form of <shifter_op>
657 Binary |= 1 << ARMII::I_BitShift;
658 Binary |= getMachineSoImmOpValue(V2);
662 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
663 // It's basically add r, pc, (LJTI - $+8)
665 const TargetInstrDesc &TID = MI.getDesc();
667 // Emit the 'add' instruction.
668 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
670 // Set the conditional execution predicate
671 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
673 // Encode S bit if MI modifies CPSR.
674 Binary |= getAddrModeSBit(MI, TID);
677 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
679 // Encode Rn which is PC.
680 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
682 // Encode the displacement.
683 Binary |= 1 << ARMII::I_BitShift;
684 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
689 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
690 unsigned Opcode = MI.getDesc().Opcode;
692 // Part of binary is determined by TableGn.
693 unsigned Binary = getBinaryCodeForInstr(MI);
695 // Set the conditional execution predicate
696 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
698 // Encode S bit if MI modifies CPSR.
699 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
700 Binary |= 1 << ARMII::S_BitShift;
702 // Encode register def if there is one.
703 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
705 // Encode the shift operation.
712 case ARM::MOVsrl_flag:
714 Binary |= (0x2 << 4) | (1 << 7);
716 case ARM::MOVsra_flag:
718 Binary |= (0x4 << 4) | (1 << 7);
722 // Encode register Rm.
723 Binary |= getMachineOpValue(MI, 1);
728 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
729 DEBUG(errs() << " ** LPC" << LabelID << " @ "
730 << (void*)MCE.getCurrentPCValue() << '\n');
731 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
734 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
735 unsigned Opcode = MI.getDesc().Opcode;
738 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
742 case ARM::BMOVPCRXr9: {
743 // First emit mov lr, pc
744 unsigned Binary = 0x01a0e00f;
745 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
748 // and then emit the branch.
749 emitMiscBranchInstruction(MI);
752 case TargetOpcode::INLINEASM: {
753 // We allow inline assembler nodes with empty bodies - they can
754 // implicitly define registers, which is ok for JIT.
755 if (MI.getOperand(0).getSymbolName()[0]) {
756 report_fatal_error("JIT does not support inline asm!");
760 case TargetOpcode::PROLOG_LABEL:
761 case TargetOpcode::EH_LABEL:
762 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
764 case TargetOpcode::IMPLICIT_DEF:
765 case TargetOpcode::KILL:
768 case ARM::CONSTPOOL_ENTRY:
769 emitConstPoolInstruction(MI);
772 // Remember of the address of the PC label for relocation later.
773 addPCLabel(MI.getOperand(2).getImm());
774 // PICADD is just an add instruction that implicitly read pc.
775 emitDataProcessingInstruction(MI, 0, ARM::PC);
782 // Remember of the address of the PC label for relocation later.
783 addPCLabel(MI.getOperand(2).getImm());
784 // These are just load / store instructions that implicitly read pc.
785 emitLoadStoreInstruction(MI, 0, ARM::PC);
792 // Remember of the address of the PC label for relocation later.
793 addPCLabel(MI.getOperand(2).getImm());
794 // These are just load / store instructions that implicitly read pc.
795 emitMiscLoadStoreInstruction(MI, ARM::PC);
800 emitMOVi32immInstruction(MI);
803 case ARM::MOVi2pieces:
804 // Two instructions to materialize a constant.
805 emitMOVi2piecesInstruction(MI);
807 case ARM::LEApcrelJT:
808 // Materialize jumptable address.
809 emitLEApcrelJTInstruction(MI);
812 case ARM::MOVsrl_flag:
813 case ARM::MOVsra_flag:
814 emitPseudoMoveInstruction(MI);
819 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
820 const TargetInstrDesc &TID,
821 const MachineOperand &MO,
823 unsigned Binary = getMachineOpValue(MI, MO);
825 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
826 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
827 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
829 // Encode the shift opcode.
831 unsigned Rs = MO1.getReg();
833 // Set shift operand (bit[7:4]).
838 // RRX - 0110 and bit[11:8] clear.
840 default: llvm_unreachable("Unknown shift opc!");
841 case ARM_AM::lsl: SBits = 0x1; break;
842 case ARM_AM::lsr: SBits = 0x3; break;
843 case ARM_AM::asr: SBits = 0x5; break;
844 case ARM_AM::ror: SBits = 0x7; break;
845 case ARM_AM::rrx: SBits = 0x6; break;
848 // Set shift operand (bit[6:4]).
854 default: llvm_unreachable("Unknown shift opc!");
855 case ARM_AM::lsl: SBits = 0x0; break;
856 case ARM_AM::lsr: SBits = 0x2; break;
857 case ARM_AM::asr: SBits = 0x4; break;
858 case ARM_AM::ror: SBits = 0x6; break;
861 Binary |= SBits << 4;
862 if (SOpc == ARM_AM::rrx)
865 // Encode the shift operation Rs or shift_imm (except rrx).
867 // Encode Rs bit[11:8].
868 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
869 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
872 // Encode shift_imm bit[11:7].
873 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
876 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
877 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
878 assert(SoImmVal != -1 && "Not a valid so_imm value!");
880 // Encode rotate_imm.
881 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
882 << ARMII::SoRotImmShift;
885 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
889 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
890 const TargetInstrDesc &TID) const {
891 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
892 const MachineOperand &MO = MI.getOperand(i-1);
893 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
894 return 1 << ARMII::S_BitShift;
899 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
901 unsigned ImplicitRn) {
902 const TargetInstrDesc &TID = MI.getDesc();
904 // Part of binary is determined by TableGn.
905 unsigned Binary = getBinaryCodeForInstr(MI);
907 // Set the conditional execution predicate
908 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
910 // Encode S bit if MI modifies CPSR.
911 Binary |= getAddrModeSBit(MI, TID);
913 // Encode register def if there is one.
914 unsigned NumDefs = TID.getNumDefs();
917 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
919 // Special handling for implicit use (e.g. PC).
920 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
922 if (TID.Opcode == ARM::MOVi16) {
923 // Get immediate from MI.
924 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
925 ARM::reloc_arm_movw);
926 // Encode imm which is the same as in emitMOVi32immInstruction().
927 Binary |= Lo16 & 0xFFF;
928 Binary |= ((Lo16 >> 12) & 0xF) << 16;
931 } else if(TID.Opcode == ARM::MOVTi16) {
932 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
933 ARM::reloc_arm_movt) >> 16);
934 Binary |= Hi16 & 0xFFF;
935 Binary |= ((Hi16 >> 12) & 0xF) << 16;
938 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
939 uint32_t v = ~MI.getOperand(2).getImm();
940 int32_t lsb = CountTrailingZeros_32(v);
941 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
942 // Instr{20-16} = msb, Instr{11-7} = lsb
943 Binary |= (msb & 0x1F) << 16;
944 Binary |= (lsb & 0x1F) << 7;
947 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
948 // Encode Rn in Instr{0-3}
949 Binary |= getMachineOpValue(MI, OpIdx++);
951 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
952 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
954 // Instr{20-16} = widthm1, Instr{11-7} = lsb
955 Binary |= (widthm1 & 0x1F) << 16;
956 Binary |= (lsb & 0x1F) << 7;
961 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
962 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
965 // Encode first non-shifter register operand if there is one.
966 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
969 // Special handling for implicit use (e.g. PC).
970 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
972 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
977 // Encode shifter operand.
978 const MachineOperand &MO = MI.getOperand(OpIdx);
979 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
981 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
986 // Encode register Rm.
987 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
992 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
997 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
999 unsigned ImplicitRn) {
1000 const TargetInstrDesc &TID = MI.getDesc();
1001 unsigned Form = TID.TSFlags & ARMII::FormMask;
1002 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1004 // Part of binary is determined by TableGn.
1005 unsigned Binary = getBinaryCodeForInstr(MI);
1007 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1008 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1009 MI.getOpcode() == ARM::STRi12) {
1014 // Set the conditional execution predicate
1015 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1019 // Operand 0 of a pre- and post-indexed store is the address base
1020 // writeback. Skip it.
1021 bool Skipped = false;
1022 if (IsPrePost && Form == ARMII::StFrm) {
1027 // Set first operand
1029 // Special handling for implicit use (e.g. PC).
1030 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1032 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1034 // Set second operand
1036 // Special handling for implicit use (e.g. PC).
1037 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1039 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1041 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1042 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1045 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1046 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1047 ? 0 : MI.getOperand(OpIdx+1).getImm();
1049 // Set bit U(23) according to sign of immed value (positive or negative).
1050 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1052 if (!MO2.getReg()) { // is immediate
1053 if (ARM_AM::getAM2Offset(AM2Opc))
1054 // Set the value of offset_12 field
1055 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1060 // Set bit I(25), because this is not in immediate encoding.
1061 Binary |= 1 << ARMII::I_BitShift;
1062 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1063 // Set bit[3:0] to the corresponding Rm register
1064 Binary |= getARMRegisterNumbering(MO2.getReg());
1066 // If this instr is in scaled register offset/index instruction, set
1067 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1068 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1069 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1070 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1076 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1077 unsigned ImplicitRn) {
1078 const TargetInstrDesc &TID = MI.getDesc();
1079 unsigned Form = TID.TSFlags & ARMII::FormMask;
1080 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1082 // Part of binary is determined by TableGn.
1083 unsigned Binary = getBinaryCodeForInstr(MI);
1085 // Set the conditional execution predicate
1086 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1090 // Operand 0 of a pre- and post-indexed store is the address base
1091 // writeback. Skip it.
1092 bool Skipped = false;
1093 if (IsPrePost && Form == ARMII::StMiscFrm) {
1098 // Set first operand
1099 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1101 // Skip LDRD and STRD's second operand.
1102 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1105 // Set second operand
1107 // Special handling for implicit use (e.g. PC).
1108 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1110 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1112 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1113 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1116 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1117 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1118 ? 0 : MI.getOperand(OpIdx+1).getImm();
1120 // Set bit U(23) according to sign of immed value (positive or negative)
1121 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1124 // If this instr is in register offset/index encoding, set bit[3:0]
1125 // to the corresponding Rm register.
1127 Binary |= getARMRegisterNumbering(MO2.getReg());
1132 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1133 Binary |= 1 << ARMII::AM3_I_BitShift;
1134 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1136 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1137 Binary |= (ImmOffs & 0xF); // immedL
1143 static unsigned getAddrModeUPBits(unsigned Mode) {
1144 unsigned Binary = 0;
1146 // Set addressing mode by modifying bits U(23) and P(24)
1147 // IA - Increment after - bit U = 1 and bit P = 0
1148 // IB - Increment before - bit U = 1 and bit P = 1
1149 // DA - Decrement after - bit U = 0 and bit P = 0
1150 // DB - Decrement before - bit U = 0 and bit P = 1
1152 default: llvm_unreachable("Unknown addressing sub-mode!");
1153 case ARM_AM::da: break;
1154 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1155 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1156 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1162 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1163 const TargetInstrDesc &TID = MI.getDesc();
1164 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1166 // Part of binary is determined by TableGn.
1167 unsigned Binary = getBinaryCodeForInstr(MI);
1169 // Set the conditional execution predicate
1170 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1172 // Skip operand 0 of an instruction with base register update.
1177 // Set base address operand
1178 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1180 // Set addressing mode by modifying bits U(23) and P(24)
1181 const MachineOperand &MO = MI.getOperand(OpIdx++);
1182 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1186 Binary |= 0x1 << ARMII::W_BitShift;
1189 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1190 const MachineOperand &MO = MI.getOperand(i);
1191 if (!MO.isReg() || MO.isImplicit())
1193 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1194 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1196 Binary |= 0x1 << RegNum;
1202 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1203 const TargetInstrDesc &TID = MI.getDesc();
1205 // Part of binary is determined by TableGn.
1206 unsigned Binary = getBinaryCodeForInstr(MI);
1208 // Set the conditional execution predicate
1209 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1211 // Encode S bit if MI modifies CPSR.
1212 Binary |= getAddrModeSBit(MI, TID);
1214 // 32x32->64bit operations have two destination registers. The number
1215 // of register definitions will tell us if that's what we're dealing with.
1217 if (TID.getNumDefs() == 2)
1218 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1221 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1224 Binary |= getMachineOpValue(MI, OpIdx++);
1227 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1229 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1230 // it as Rn (for multiply, that's in the same offset as RdLo.
1231 if (TID.getNumOperands() > OpIdx &&
1232 !TID.OpInfo[OpIdx].isPredicate() &&
1233 !TID.OpInfo[OpIdx].isOptionalDef())
1234 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1239 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1240 const TargetInstrDesc &TID = MI.getDesc();
1242 // Part of binary is determined by TableGn.
1243 unsigned Binary = getBinaryCodeForInstr(MI);
1245 // Set the conditional execution predicate
1246 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1251 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1253 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1254 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1256 // Two register operand form.
1258 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1261 Binary |= getMachineOpValue(MI, MO2);
1264 Binary |= getMachineOpValue(MI, MO1);
1267 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1268 if (MI.getOperand(OpIdx).isImm() &&
1269 !TID.OpInfo[OpIdx].isPredicate() &&
1270 !TID.OpInfo[OpIdx].isOptionalDef())
1271 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1276 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1277 const TargetInstrDesc &TID = MI.getDesc();
1279 // Part of binary is determined by TableGn.
1280 unsigned Binary = getBinaryCodeForInstr(MI);
1282 // Set the conditional execution predicate
1283 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1288 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1290 const MachineOperand &MO = MI.getOperand(OpIdx++);
1291 if (OpIdx == TID.getNumOperands() ||
1292 TID.OpInfo[OpIdx].isPredicate() ||
1293 TID.OpInfo[OpIdx].isOptionalDef()) {
1294 // Encode Rm and it's done.
1295 Binary |= getMachineOpValue(MI, MO);
1301 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1304 Binary |= getMachineOpValue(MI, OpIdx++);
1306 // Encode shift_imm.
1307 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1308 if (TID.Opcode == ARM::PKHTB) {
1309 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1313 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1314 Binary |= ShiftAmt << ARMII::ShiftShift;
1319 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1320 const TargetInstrDesc &TID = MI.getDesc();
1322 // Part of binary is determined by TableGen.
1323 unsigned Binary = getBinaryCodeForInstr(MI);
1325 // Set the conditional execution predicate
1326 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1329 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1331 // Encode saturate bit position.
1332 unsigned Pos = MI.getOperand(1).getImm();
1333 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1335 assert((Pos < 16 || (Pos < 32 &&
1336 TID.Opcode != ARM::SSAT16 &&
1337 TID.Opcode != ARM::USAT16)) &&
1338 "saturate bit position out of range");
1339 Binary |= Pos << 16;
1342 Binary |= getMachineOpValue(MI, 2);
1344 // Encode shift_imm.
1345 if (TID.getNumOperands() == 4) {
1346 unsigned ShiftOp = MI.getOperand(3).getImm();
1347 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1348 if (Opc == ARM_AM::asr)
1350 unsigned ShiftAmt = MI.getOperand(3).getImm();
1351 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1353 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1354 Binary |= ShiftAmt << ARMII::ShiftShift;
1360 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1361 const TargetInstrDesc &TID = MI.getDesc();
1363 if (TID.Opcode == ARM::TPsoft) {
1364 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1367 // Part of binary is determined by TableGn.
1368 unsigned Binary = getBinaryCodeForInstr(MI);
1370 // Set the conditional execution predicate
1371 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1373 // Set signed_immed_24 field
1374 Binary |= getMachineOpValue(MI, 0);
1379 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1380 // Remember the base address of the inline jump table.
1381 uintptr_t JTBase = MCE.getCurrentPCValue();
1382 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1383 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1386 // Now emit the jump table entries.
1387 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1388 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1390 // DestBB address - JT base.
1391 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1393 // Absolute DestBB address.
1394 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1399 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1400 const TargetInstrDesc &TID = MI.getDesc();
1402 // Handle jump tables.
1403 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1404 // First emit a ldr pc, [] instruction.
1405 emitDataProcessingInstruction(MI, ARM::PC);
1407 // Then emit the inline jump table.
1409 (TID.Opcode == ARM::BR_JTr)
1410 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1411 emitInlineJumpTable(JTIndex);
1413 } else if (TID.Opcode == ARM::BR_JTm) {
1414 // First emit a ldr pc, [] instruction.
1415 emitLoadStoreInstruction(MI, ARM::PC);
1417 // Then emit the inline jump table.
1418 emitInlineJumpTable(MI.getOperand(3).getIndex());
1422 // Part of binary is determined by TableGn.
1423 unsigned Binary = getBinaryCodeForInstr(MI);
1425 // Set the conditional execution predicate
1426 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1428 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1429 // The return register is LR.
1430 Binary |= getARMRegisterNumbering(ARM::LR);
1432 // otherwise, set the return register
1433 Binary |= getMachineOpValue(MI, 0);
1438 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1439 unsigned RegD = MI.getOperand(OpIdx).getReg();
1440 unsigned Binary = 0;
1441 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1442 RegD = getARMRegisterNumbering(RegD);
1444 Binary |= RegD << ARMII::RegRdShift;
1446 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1447 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1452 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1453 unsigned RegN = MI.getOperand(OpIdx).getReg();
1454 unsigned Binary = 0;
1455 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1456 RegN = getARMRegisterNumbering(RegN);
1458 Binary |= RegN << ARMII::RegRnShift;
1460 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1461 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1466 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1467 unsigned RegM = MI.getOperand(OpIdx).getReg();
1468 unsigned Binary = 0;
1469 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1470 RegM = getARMRegisterNumbering(RegM);
1474 Binary |= ((RegM & 0x1E) >> 1);
1475 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1480 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1481 const TargetInstrDesc &TID = MI.getDesc();
1483 // Part of binary is determined by TableGn.
1484 unsigned Binary = getBinaryCodeForInstr(MI);
1486 // Set the conditional execution predicate
1487 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1490 assert((Binary & ARMII::D_BitShift) == 0 &&
1491 (Binary & ARMII::N_BitShift) == 0 &&
1492 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1495 Binary |= encodeVFPRd(MI, OpIdx++);
1497 // If this is a two-address operand, skip it, e.g. FMACD.
1498 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1502 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1503 Binary |= encodeVFPRn(MI, OpIdx++);
1505 if (OpIdx == TID.getNumOperands() ||
1506 TID.OpInfo[OpIdx].isPredicate() ||
1507 TID.OpInfo[OpIdx].isOptionalDef()) {
1508 // FCMPEZD etc. has only one operand.
1514 Binary |= encodeVFPRm(MI, OpIdx);
1519 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1520 const TargetInstrDesc &TID = MI.getDesc();
1521 unsigned Form = TID.TSFlags & ARMII::FormMask;
1523 // Part of binary is determined by TableGn.
1524 unsigned Binary = getBinaryCodeForInstr(MI);
1526 // Set the conditional execution predicate
1527 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1531 case ARMII::VFPConv1Frm:
1532 case ARMII::VFPConv2Frm:
1533 case ARMII::VFPConv3Frm:
1535 Binary |= encodeVFPRd(MI, 0);
1537 case ARMII::VFPConv4Frm:
1539 Binary |= encodeVFPRn(MI, 0);
1541 case ARMII::VFPConv5Frm:
1543 Binary |= encodeVFPRm(MI, 0);
1549 case ARMII::VFPConv1Frm:
1551 Binary |= encodeVFPRm(MI, 1);
1553 case ARMII::VFPConv2Frm:
1554 case ARMII::VFPConv3Frm:
1556 Binary |= encodeVFPRn(MI, 1);
1558 case ARMII::VFPConv4Frm:
1559 case ARMII::VFPConv5Frm:
1561 Binary |= encodeVFPRd(MI, 1);
1565 if (Form == ARMII::VFPConv5Frm)
1567 Binary |= encodeVFPRn(MI, 2);
1568 else if (Form == ARMII::VFPConv3Frm)
1570 Binary |= encodeVFPRm(MI, 2);
1575 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1576 // Part of binary is determined by TableGn.
1577 unsigned Binary = getBinaryCodeForInstr(MI);
1579 // Set the conditional execution predicate
1580 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1585 Binary |= encodeVFPRd(MI, OpIdx++);
1587 // Encode address base.
1588 const MachineOperand &Base = MI.getOperand(OpIdx++);
1589 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1591 // If there is a non-zero immediate offset, encode it.
1593 const MachineOperand &Offset = MI.getOperand(OpIdx);
1594 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1595 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1596 Binary |= 1 << ARMII::U_BitShift;
1603 // If immediate offset is omitted, default to +0.
1604 Binary |= 1 << ARMII::U_BitShift;
1610 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1611 const TargetInstrDesc &TID = MI.getDesc();
1612 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1614 // Part of binary is determined by TableGn.
1615 unsigned Binary = getBinaryCodeForInstr(MI);
1617 // Set the conditional execution predicate
1618 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1620 // Skip operand 0 of an instruction with base register update.
1625 // Set base address operand
1626 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1628 // Set addressing mode by modifying bits U(23) and P(24)
1629 const MachineOperand &MO = MI.getOperand(OpIdx++);
1630 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1634 Binary |= 0x1 << ARMII::W_BitShift;
1636 // First register is encoded in Dd.
1637 Binary |= encodeVFPRd(MI, OpIdx+2);
1639 // Count the number of registers.
1640 unsigned NumRegs = 1;
1641 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1642 const MachineOperand &MO = MI.getOperand(i);
1643 if (!MO.isReg() || MO.isImplicit())
1647 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1648 // Otherwise, it will be 0, in the case of 32-bit registers.
1650 Binary |= NumRegs * 2;
1657 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1658 unsigned RegD = MI.getOperand(OpIdx).getReg();
1659 unsigned Binary = 0;
1660 RegD = getARMRegisterNumbering(RegD);
1661 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1662 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1666 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1667 unsigned RegN = MI.getOperand(OpIdx).getReg();
1668 unsigned Binary = 0;
1669 RegN = getARMRegisterNumbering(RegN);
1670 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1671 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1675 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1676 unsigned RegM = MI.getOperand(OpIdx).getReg();
1677 unsigned Binary = 0;
1678 RegM = getARMRegisterNumbering(RegM);
1679 Binary |= (RegM & 0xf);
1680 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1684 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1685 /// data-processing instruction to the corresponding Thumb encoding.
1686 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1687 assert((Binary & 0xfe000000) == 0xf2000000 &&
1688 "not an ARM NEON data-processing instruction");
1689 unsigned UBit = (Binary >> 24) & 1;
1690 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1693 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1694 unsigned Binary = getBinaryCodeForInstr(MI);
1696 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1697 const TargetInstrDesc &TID = MI.getDesc();
1698 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1702 } else { // ARMII::NSetLnFrm
1708 // Set the conditional execution predicate
1709 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1711 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1712 RegT = getARMRegisterNumbering(RegT);
1713 Binary |= (RegT << ARMII::RegRdShift);
1714 Binary |= encodeNEONRn(MI, RegNOpIdx);
1717 if ((Binary & (1 << 22)) != 0)
1718 LaneShift = 0; // 8-bit elements
1719 else if ((Binary & (1 << 5)) != 0)
1720 LaneShift = 1; // 16-bit elements
1722 LaneShift = 2; // 32-bit elements
1724 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1725 unsigned Opc1 = Lane >> 2;
1726 unsigned Opc2 = Lane & 3;
1727 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1728 Binary |= (Opc1 << 21);
1729 Binary |= (Opc2 << 5);
1734 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1735 unsigned Binary = getBinaryCodeForInstr(MI);
1737 // Set the conditional execution predicate
1738 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1740 unsigned RegT = MI.getOperand(1).getReg();
1741 RegT = getARMRegisterNumbering(RegT);
1742 Binary |= (RegT << ARMII::RegRdShift);
1743 Binary |= encodeNEONRn(MI, 0);
1747 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1748 unsigned Binary = getBinaryCodeForInstr(MI);
1749 // Destination register is encoded in Dd.
1750 Binary |= encodeNEONRd(MI, 0);
1751 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1752 unsigned Imm = MI.getOperand(1).getImm();
1753 unsigned Op = (Imm >> 12) & 1;
1754 unsigned Cmode = (Imm >> 8) & 0xf;
1755 unsigned I = (Imm >> 7) & 1;
1756 unsigned Imm3 = (Imm >> 4) & 0x7;
1757 unsigned Imm4 = Imm & 0xf;
1758 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1760 Binary = convertNEONDataProcToThumb(Binary);
1764 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1765 const TargetInstrDesc &TID = MI.getDesc();
1766 unsigned Binary = getBinaryCodeForInstr(MI);
1767 // Destination register is encoded in Dd; source register in Dm.
1769 Binary |= encodeNEONRd(MI, OpIdx++);
1770 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1772 Binary |= encodeNEONRm(MI, OpIdx);
1774 Binary = convertNEONDataProcToThumb(Binary);
1775 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1779 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1780 const TargetInstrDesc &TID = MI.getDesc();
1781 unsigned Binary = getBinaryCodeForInstr(MI);
1782 // Destination register is encoded in Dd; source registers in Dn and Dm.
1784 Binary |= encodeNEONRd(MI, OpIdx++);
1785 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1787 Binary |= encodeNEONRn(MI, OpIdx++);
1788 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1790 Binary |= encodeNEONRm(MI, OpIdx);
1792 Binary = convertNEONDataProcToThumb(Binary);
1793 // FIXME: This does not handle VMOVDneon or VMOVQ.
1797 #include "ARMGenCodeEmitter.inc"