1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrMode6RegisterOperand(const MachineInstr &MI);
105 unsigned getAddrMode6OffsetOperand(const MachineInstr &MI);
107 unsigned getAddrModeSBit(const MachineInstr &MI,
108 const TargetInstrDesc &TID) const;
110 void emitDataProcessingInstruction(const MachineInstr &MI,
111 unsigned ImplicitRd = 0,
112 unsigned ImplicitRn = 0);
114 void emitLoadStoreInstruction(const MachineInstr &MI,
115 unsigned ImplicitRd = 0,
116 unsigned ImplicitRn = 0);
118 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
119 unsigned ImplicitRn = 0);
121 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
123 void emitMulFrmInstruction(const MachineInstr &MI);
125 void emitExtendInstruction(const MachineInstr &MI);
127 void emitMiscArithInstruction(const MachineInstr &MI);
129 void emitSaturateInstruction(const MachineInstr &MI);
131 void emitBranchInstruction(const MachineInstr &MI);
133 void emitInlineJumpTable(unsigned JTIndex);
135 void emitMiscBranchInstruction(const MachineInstr &MI);
137 void emitVFPArithInstruction(const MachineInstr &MI);
139 void emitVFPConversionInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
143 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,
154 const MachineOperand &MO) const;
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
160 // TableGen'erated getBinaryCodeForInstr() function to encode any
161 // operand values, instead querying getMachineOpValue() directly for
162 // each operand it needs to encode. Thus, any of the new encoder
163 // helper functions can simply return 0 as the values the return
164 // are already handled elsewhere. They are placeholders to allow this
165 // encoder to continue to function until the MC encoder is sufficiently
166 // far along that this one can be eliminated entirely.
167 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
169 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
171 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
173 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
175 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
177 unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op)
179 unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op)
181 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
182 unsigned Op) const { return 0; }
183 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
186 // {12} = (U)nsigned (add == '1', sub == '0')
188 const MachineOperand &MO = MI.getOperand(Op);
189 const MachineOperand &MO1 = MI.getOperand(Op + 1);
191 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
194 unsigned Reg = getARMRegisterNumbering(MO.getReg());
195 int32_t Imm12 = MO1.getImm();
197 Binary = Imm12 & 0xfff;
200 Binary |= (Reg << 13);
203 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
209 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
210 /// machine operand requires relocation, record the relocation and return
212 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
215 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
217 unsigned getShiftOp(unsigned Imm) const ;
219 /// Routines that handle operands which add machine relocations which are
220 /// fixed up by the relocation stage.
221 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
222 bool MayNeedFarStub, bool Indirect,
223 intptr_t ACPV = 0) const;
224 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
225 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
226 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
227 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
228 intptr_t JTBase = 0) const;
232 char ARMCodeEmitter::ID = 0;
234 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
235 /// code to the specified MCE object.
236 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
237 JITCodeEmitter &JCE) {
238 return new ARMCodeEmitter(TM, JCE);
241 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
242 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
243 MF.getTarget().getRelocationModel() != Reloc::Static) &&
244 "JIT relocation model must be set to static or default!");
245 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
246 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
247 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
248 Subtarget = &TM.getSubtarget<ARMSubtarget>();
249 MCPEs = &MF.getConstantPool()->getConstants();
251 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
252 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
253 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
254 JTI->Initialize(MF, IsPIC);
255 MMI = &getAnalysis<MachineModuleInfo>();
256 MCE.setModuleInfo(MMI);
259 DEBUG(errs() << "JITTing function '"
260 << MF.getFunction()->getName() << "'\n");
261 MCE.startFunction(MF);
262 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
264 MCE.StartMachineBasicBlock(MBB);
265 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
269 } while (MCE.finishFunction(MF));
274 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
276 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
277 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
278 default: llvm_unreachable("Unknown shift opc!");
279 case ARM_AM::asr: return 2;
280 case ARM_AM::lsl: return 0;
281 case ARM_AM::lsr: return 1;
283 case ARM_AM::rrx: return 3;
288 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
289 /// machine operand requires relocation, record the relocation and return zero.
290 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
291 const MachineOperand &MO,
293 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
294 && "Relocation to this function should be for movt or movw");
297 return static_cast<unsigned>(MO.getImm());
298 else if (MO.isGlobal())
299 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
300 else if (MO.isSymbol())
301 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
303 emitMachineBasicBlock(MO.getMBB(), Reloc);
308 llvm_unreachable("Unsupported operand type for movw/movt");
313 /// getMachineOpValue - Return binary encoding of operand. If the machine
314 /// operand requires relocation, record the relocation and return zero.
315 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
316 const MachineOperand &MO) const {
318 return getARMRegisterNumbering(MO.getReg());
320 return static_cast<unsigned>(MO.getImm());
321 else if (MO.isGlobal())
322 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
323 else if (MO.isSymbol())
324 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
325 else if (MO.isCPI()) {
326 const TargetInstrDesc &TID = MI.getDesc();
327 // For VFP load, the immediate offset is multiplied by 4.
328 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
329 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
330 emitConstPoolAddress(MO.getIndex(), Reloc);
331 } else if (MO.isJTI())
332 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
334 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
344 /// emitGlobalAddress - Emit the specified address to the code stream.
346 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
347 bool MayNeedFarStub, bool Indirect,
348 intptr_t ACPV) const {
349 MachineRelocation MR = Indirect
350 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
351 const_cast<GlobalValue *>(GV),
352 ACPV, MayNeedFarStub)
353 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
354 const_cast<GlobalValue *>(GV), ACPV,
356 MCE.addRelocation(MR);
359 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
360 /// be emitted to the current location in the function, and allow it to be PC
362 void ARMCodeEmitter::
363 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
364 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
368 /// emitConstPoolAddress - Arrange for the address of an constant pool
369 /// to be emitted to the current location in the function, and allow it to be PC
371 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
372 // Tell JIT emitter we'll resolve the address.
373 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
374 Reloc, CPI, 0, true));
377 /// emitJumpTableAddress - Arrange for the address of a jump table to
378 /// be emitted to the current location in the function, and allow it to be PC
380 void ARMCodeEmitter::
381 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
382 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
383 Reloc, JTIndex, 0, true));
386 /// emitMachineBasicBlock - Emit the specified address basic block.
387 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
389 intptr_t JTBase) const {
390 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
394 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
395 DEBUG(errs() << " 0x";
396 errs().write_hex(Binary) << "\n");
397 MCE.emitWordLE(Binary);
400 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
401 DEBUG(errs() << " 0x";
402 errs().write_hex(Binary) << "\n");
403 MCE.emitDWordLE(Binary);
406 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
407 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
409 MCE.processDebugLoc(MI.getDebugLoc(), true);
411 ++NumEmitted; // Keep track of the # of mi's emitted
412 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
414 llvm_unreachable("Unhandled instruction encoding format!");
418 emitPseudoInstruction(MI);
421 case ARMII::DPSoRegFrm:
422 emitDataProcessingInstruction(MI);
426 emitLoadStoreInstruction(MI);
428 case ARMII::LdMiscFrm:
429 case ARMII::StMiscFrm:
430 emitMiscLoadStoreInstruction(MI);
432 case ARMII::LdStMulFrm:
433 emitLoadStoreMultipleInstruction(MI);
436 emitMulFrmInstruction(MI);
439 emitExtendInstruction(MI);
441 case ARMII::ArithMiscFrm:
442 emitMiscArithInstruction(MI);
445 emitSaturateInstruction(MI);
448 emitBranchInstruction(MI);
450 case ARMII::BrMiscFrm:
451 emitMiscBranchInstruction(MI);
454 case ARMII::VFPUnaryFrm:
455 case ARMII::VFPBinaryFrm:
456 emitVFPArithInstruction(MI);
458 case ARMII::VFPConv1Frm:
459 case ARMII::VFPConv2Frm:
460 case ARMII::VFPConv3Frm:
461 case ARMII::VFPConv4Frm:
462 case ARMII::VFPConv5Frm:
463 emitVFPConversionInstruction(MI);
465 case ARMII::VFPLdStFrm:
466 emitVFPLoadStoreInstruction(MI);
468 case ARMII::VFPLdStMulFrm:
469 emitVFPLoadStoreMultipleInstruction(MI);
472 // NEON instructions.
473 case ARMII::NGetLnFrm:
474 case ARMII::NSetLnFrm:
475 emitNEONLaneInstruction(MI);
478 emitNEONDupInstruction(MI);
480 case ARMII::N1RegModImmFrm:
481 emitNEON1RegModImmInstruction(MI);
483 case ARMII::N2RegFrm:
484 emitNEON2RegInstruction(MI);
486 case ARMII::N3RegFrm:
487 emitNEON3RegInstruction(MI);
490 MCE.processDebugLoc(MI.getDebugLoc(), false);
493 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
494 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
495 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
496 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
498 // Remember the CONSTPOOL_ENTRY address for later relocation.
499 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
501 // Emit constpool island entry. In most cases, the actual values will be
502 // resolved and relocated after code emission.
503 if (MCPE.isMachineConstantPoolEntry()) {
504 ARMConstantPoolValue *ACPV =
505 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
507 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
508 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
510 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
511 const GlobalValue *GV = ACPV->getGV();
513 Reloc::Model RelocM = TM.getRelocationModel();
514 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
516 Subtarget->GVIsIndirectSymbol(GV, RelocM),
519 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
523 const Constant *CV = MCPE.Val.ConstVal;
526 errs() << " ** Constant pool #" << CPI << " @ "
527 << (void*)MCE.getCurrentPCValue() << " ";
528 if (const Function *F = dyn_cast<Function>(CV))
529 errs() << F->getName();
535 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
536 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
538 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
539 uint32_t Val = uint32_t(*CI->getValue().getRawData());
541 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
542 if (CFP->getType()->isFloatTy())
543 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
544 else if (CFP->getType()->isDoubleTy())
545 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
547 llvm_unreachable("Unable to handle this constantpool entry!");
550 llvm_unreachable("Unable to handle this constantpool entry!");
555 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
556 const MachineOperand &MO0 = MI.getOperand(0);
557 const MachineOperand &MO1 = MI.getOperand(1);
559 // Emit the 'movw' instruction.
560 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
562 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
564 // Set the conditional execution predicate.
565 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
568 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
570 // Encode imm16 as imm4:imm12
571 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
572 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
575 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
576 // Emit the 'movt' instruction.
577 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
579 // Set the conditional execution predicate.
580 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
583 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
585 // Encode imm16 as imm4:imm1, same as movw above.
586 Binary |= Hi16 & 0xFFF;
587 Binary |= ((Hi16 >> 12) & 0xF) << 16;
591 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
592 const MachineOperand &MO0 = MI.getOperand(0);
593 const MachineOperand &MO1 = MI.getOperand(1);
594 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
595 "Not a valid so_imm value!");
596 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
597 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
599 // Emit the 'mov' instruction.
600 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
602 // Set the conditional execution predicate.
603 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
606 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
609 // Set bit I(25) to identify this is the immediate form of <shifter_op>
610 Binary |= 1 << ARMII::I_BitShift;
611 Binary |= getMachineSoImmOpValue(V1);
614 // Now the 'orr' instruction.
615 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
617 // Set the conditional execution predicate.
618 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
621 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
624 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
627 // Set bit I(25) to identify this is the immediate form of <shifter_op>
628 Binary |= 1 << ARMII::I_BitShift;
629 Binary |= getMachineSoImmOpValue(V2);
633 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
634 // It's basically add r, pc, (LJTI - $+8)
636 const TargetInstrDesc &TID = MI.getDesc();
638 // Emit the 'add' instruction.
639 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
641 // Set the conditional execution predicate
642 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
644 // Encode S bit if MI modifies CPSR.
645 Binary |= getAddrModeSBit(MI, TID);
648 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
650 // Encode Rn which is PC.
651 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
653 // Encode the displacement.
654 Binary |= 1 << ARMII::I_BitShift;
655 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
660 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
661 unsigned Opcode = MI.getDesc().Opcode;
663 // Part of binary is determined by TableGn.
664 unsigned Binary = getBinaryCodeForInstr(MI);
666 // Set the conditional execution predicate
667 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
669 // Encode S bit if MI modifies CPSR.
670 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
671 Binary |= 1 << ARMII::S_BitShift;
673 // Encode register def if there is one.
674 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
676 // Encode the shift operation.
683 case ARM::MOVsrl_flag:
685 Binary |= (0x2 << 4) | (1 << 7);
687 case ARM::MOVsra_flag:
689 Binary |= (0x4 << 4) | (1 << 7);
693 // Encode register Rm.
694 Binary |= getMachineOpValue(MI, 1);
699 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
700 DEBUG(errs() << " ** LPC" << LabelID << " @ "
701 << (void*)MCE.getCurrentPCValue() << '\n');
702 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
705 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
706 unsigned Opcode = MI.getDesc().Opcode;
709 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
713 case ARM::BMOVPCRXr9: {
714 // First emit mov lr, pc
715 unsigned Binary = 0x01a0e00f;
716 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
719 // and then emit the branch.
720 emitMiscBranchInstruction(MI);
723 case TargetOpcode::INLINEASM: {
724 // We allow inline assembler nodes with empty bodies - they can
725 // implicitly define registers, which is ok for JIT.
726 if (MI.getOperand(0).getSymbolName()[0]) {
727 report_fatal_error("JIT does not support inline asm!");
731 case TargetOpcode::PROLOG_LABEL:
732 case TargetOpcode::EH_LABEL:
733 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
735 case TargetOpcode::IMPLICIT_DEF:
736 case TargetOpcode::KILL:
739 case ARM::CONSTPOOL_ENTRY:
740 emitConstPoolInstruction(MI);
743 // Remember of the address of the PC label for relocation later.
744 addPCLabel(MI.getOperand(2).getImm());
745 // PICADD is just an add instruction that implicitly read pc.
746 emitDataProcessingInstruction(MI, 0, ARM::PC);
753 // Remember of the address of the PC label for relocation later.
754 addPCLabel(MI.getOperand(2).getImm());
755 // These are just load / store instructions that implicitly read pc.
756 emitLoadStoreInstruction(MI, 0, ARM::PC);
763 // Remember of the address of the PC label for relocation later.
764 addPCLabel(MI.getOperand(2).getImm());
765 // These are just load / store instructions that implicitly read pc.
766 emitMiscLoadStoreInstruction(MI, ARM::PC);
771 emitMOVi32immInstruction(MI);
774 case ARM::MOVi2pieces:
775 // Two instructions to materialize a constant.
776 emitMOVi2piecesInstruction(MI);
778 case ARM::LEApcrelJT:
779 // Materialize jumptable address.
780 emitLEApcrelJTInstruction(MI);
783 case ARM::MOVsrl_flag:
784 case ARM::MOVsra_flag:
785 emitPseudoMoveInstruction(MI);
790 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
791 const TargetInstrDesc &TID,
792 const MachineOperand &MO,
794 unsigned Binary = getMachineOpValue(MI, MO);
796 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
797 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
798 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
800 // Encode the shift opcode.
802 unsigned Rs = MO1.getReg();
804 // Set shift operand (bit[7:4]).
809 // RRX - 0110 and bit[11:8] clear.
811 default: llvm_unreachable("Unknown shift opc!");
812 case ARM_AM::lsl: SBits = 0x1; break;
813 case ARM_AM::lsr: SBits = 0x3; break;
814 case ARM_AM::asr: SBits = 0x5; break;
815 case ARM_AM::ror: SBits = 0x7; break;
816 case ARM_AM::rrx: SBits = 0x6; break;
819 // Set shift operand (bit[6:4]).
825 default: llvm_unreachable("Unknown shift opc!");
826 case ARM_AM::lsl: SBits = 0x0; break;
827 case ARM_AM::lsr: SBits = 0x2; break;
828 case ARM_AM::asr: SBits = 0x4; break;
829 case ARM_AM::ror: SBits = 0x6; break;
832 Binary |= SBits << 4;
833 if (SOpc == ARM_AM::rrx)
836 // Encode the shift operation Rs or shift_imm (except rrx).
838 // Encode Rs bit[11:8].
839 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
840 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
843 // Encode shift_imm bit[11:7].
844 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
847 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
848 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
849 assert(SoImmVal != -1 && "Not a valid so_imm value!");
851 // Encode rotate_imm.
852 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
853 << ARMII::SoRotImmShift;
856 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
860 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
861 const TargetInstrDesc &TID) const {
862 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
863 const MachineOperand &MO = MI.getOperand(i-1);
864 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
865 return 1 << ARMII::S_BitShift;
870 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
872 unsigned ImplicitRn) {
873 const TargetInstrDesc &TID = MI.getDesc();
875 // Part of binary is determined by TableGn.
876 unsigned Binary = getBinaryCodeForInstr(MI);
878 // Set the conditional execution predicate
879 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
881 // Encode S bit if MI modifies CPSR.
882 Binary |= getAddrModeSBit(MI, TID);
884 // Encode register def if there is one.
885 unsigned NumDefs = TID.getNumDefs();
888 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
890 // Special handling for implicit use (e.g. PC).
891 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
893 if (TID.Opcode == ARM::MOVi16) {
894 // Get immediate from MI.
895 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
896 ARM::reloc_arm_movw);
897 // Encode imm which is the same as in emitMOVi32immInstruction().
898 Binary |= Lo16 & 0xFFF;
899 Binary |= ((Lo16 >> 12) & 0xF) << 16;
902 } else if(TID.Opcode == ARM::MOVTi16) {
903 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
904 ARM::reloc_arm_movt) >> 16);
905 Binary |= Hi16 & 0xFFF;
906 Binary |= ((Hi16 >> 12) & 0xF) << 16;
909 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
910 uint32_t v = ~MI.getOperand(2).getImm();
911 int32_t lsb = CountTrailingZeros_32(v);
912 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
913 // Instr{20-16} = msb, Instr{11-7} = lsb
914 Binary |= (msb & 0x1F) << 16;
915 Binary |= (lsb & 0x1F) << 7;
918 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
919 // Encode Rn in Instr{0-3}
920 Binary |= getMachineOpValue(MI, OpIdx++);
922 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
923 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
925 // Instr{20-16} = widthm1, Instr{11-7} = lsb
926 Binary |= (widthm1 & 0x1F) << 16;
927 Binary |= (lsb & 0x1F) << 7;
932 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
933 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
936 // Encode first non-shifter register operand if there is one.
937 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
940 // Special handling for implicit use (e.g. PC).
941 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
943 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
948 // Encode shifter operand.
949 const MachineOperand &MO = MI.getOperand(OpIdx);
950 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
952 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
957 // Encode register Rm.
958 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
963 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
968 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
970 unsigned ImplicitRn) {
971 const TargetInstrDesc &TID = MI.getDesc();
972 unsigned Form = TID.TSFlags & ARMII::FormMask;
973 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
975 // Part of binary is determined by TableGn.
976 unsigned Binary = getBinaryCodeForInstr(MI);
978 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
979 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
980 MI.getOpcode() == ARM::STRi12) {
985 // Set the conditional execution predicate
986 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
990 // Operand 0 of a pre- and post-indexed store is the address base
991 // writeback. Skip it.
992 bool Skipped = false;
993 if (IsPrePost && Form == ARMII::StFrm) {
1000 // Special handling for implicit use (e.g. PC).
1001 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1003 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1005 // Set second operand
1007 // Special handling for implicit use (e.g. PC).
1008 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1010 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1012 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1013 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1016 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1017 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1018 ? 0 : MI.getOperand(OpIdx+1).getImm();
1020 // Set bit U(23) according to sign of immed value (positive or negative).
1021 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1023 if (!MO2.getReg()) { // is immediate
1024 if (ARM_AM::getAM2Offset(AM2Opc))
1025 // Set the value of offset_12 field
1026 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1031 // Set bit I(25), because this is not in immediate encoding.
1032 Binary |= 1 << ARMII::I_BitShift;
1033 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1034 // Set bit[3:0] to the corresponding Rm register
1035 Binary |= getARMRegisterNumbering(MO2.getReg());
1037 // If this instr is in scaled register offset/index instruction, set
1038 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1039 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1040 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1041 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1047 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1048 unsigned ImplicitRn) {
1049 const TargetInstrDesc &TID = MI.getDesc();
1050 unsigned Form = TID.TSFlags & ARMII::FormMask;
1051 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1053 // Part of binary is determined by TableGn.
1054 unsigned Binary = getBinaryCodeForInstr(MI);
1056 // Set the conditional execution predicate
1057 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1061 // Operand 0 of a pre- and post-indexed store is the address base
1062 // writeback. Skip it.
1063 bool Skipped = false;
1064 if (IsPrePost && Form == ARMII::StMiscFrm) {
1069 // Set first operand
1070 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1072 // Skip LDRD and STRD's second operand.
1073 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1076 // Set second operand
1078 // Special handling for implicit use (e.g. PC).
1079 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1081 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1083 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1084 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1087 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1088 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1089 ? 0 : MI.getOperand(OpIdx+1).getImm();
1091 // Set bit U(23) according to sign of immed value (positive or negative)
1092 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1095 // If this instr is in register offset/index encoding, set bit[3:0]
1096 // to the corresponding Rm register.
1098 Binary |= getARMRegisterNumbering(MO2.getReg());
1103 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1104 Binary |= 1 << ARMII::AM3_I_BitShift;
1105 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1107 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1108 Binary |= (ImmOffs & 0xF); // immedL
1114 static unsigned getAddrModeUPBits(unsigned Mode) {
1115 unsigned Binary = 0;
1117 // Set addressing mode by modifying bits U(23) and P(24)
1118 // IA - Increment after - bit U = 1 and bit P = 0
1119 // IB - Increment before - bit U = 1 and bit P = 1
1120 // DA - Decrement after - bit U = 0 and bit P = 0
1121 // DB - Decrement before - bit U = 0 and bit P = 1
1123 default: llvm_unreachable("Unknown addressing sub-mode!");
1124 case ARM_AM::da: break;
1125 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1126 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1127 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1133 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1134 const TargetInstrDesc &TID = MI.getDesc();
1135 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1137 // Part of binary is determined by TableGn.
1138 unsigned Binary = getBinaryCodeForInstr(MI);
1140 // Set the conditional execution predicate
1141 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1143 // Skip operand 0 of an instruction with base register update.
1148 // Set base address operand
1149 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1151 // Set addressing mode by modifying bits U(23) and P(24)
1152 const MachineOperand &MO = MI.getOperand(OpIdx++);
1153 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1157 Binary |= 0x1 << ARMII::W_BitShift;
1160 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1161 const MachineOperand &MO = MI.getOperand(i);
1162 if (!MO.isReg() || MO.isImplicit())
1164 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1165 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1167 Binary |= 0x1 << RegNum;
1173 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1174 const TargetInstrDesc &TID = MI.getDesc();
1176 // Part of binary is determined by TableGn.
1177 unsigned Binary = getBinaryCodeForInstr(MI);
1179 // Set the conditional execution predicate
1180 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1182 // Encode S bit if MI modifies CPSR.
1183 Binary |= getAddrModeSBit(MI, TID);
1185 // 32x32->64bit operations have two destination registers. The number
1186 // of register definitions will tell us if that's what we're dealing with.
1188 if (TID.getNumDefs() == 2)
1189 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1192 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1195 Binary |= getMachineOpValue(MI, OpIdx++);
1198 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1200 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1201 // it as Rn (for multiply, that's in the same offset as RdLo.
1202 if (TID.getNumOperands() > OpIdx &&
1203 !TID.OpInfo[OpIdx].isPredicate() &&
1204 !TID.OpInfo[OpIdx].isOptionalDef())
1205 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1210 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1211 const TargetInstrDesc &TID = MI.getDesc();
1213 // Part of binary is determined by TableGn.
1214 unsigned Binary = getBinaryCodeForInstr(MI);
1216 // Set the conditional execution predicate
1217 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1222 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1224 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1225 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1227 // Two register operand form.
1229 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1232 Binary |= getMachineOpValue(MI, MO2);
1235 Binary |= getMachineOpValue(MI, MO1);
1238 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1239 if (MI.getOperand(OpIdx).isImm() &&
1240 !TID.OpInfo[OpIdx].isPredicate() &&
1241 !TID.OpInfo[OpIdx].isOptionalDef())
1242 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1247 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1248 const TargetInstrDesc &TID = MI.getDesc();
1250 // Part of binary is determined by TableGn.
1251 unsigned Binary = getBinaryCodeForInstr(MI);
1253 // Set the conditional execution predicate
1254 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1259 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1261 const MachineOperand &MO = MI.getOperand(OpIdx++);
1262 if (OpIdx == TID.getNumOperands() ||
1263 TID.OpInfo[OpIdx].isPredicate() ||
1264 TID.OpInfo[OpIdx].isOptionalDef()) {
1265 // Encode Rm and it's done.
1266 Binary |= getMachineOpValue(MI, MO);
1272 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1275 Binary |= getMachineOpValue(MI, OpIdx++);
1277 // Encode shift_imm.
1278 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1279 if (TID.Opcode == ARM::PKHTB) {
1280 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1284 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1285 Binary |= ShiftAmt << ARMII::ShiftShift;
1290 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1291 const TargetInstrDesc &TID = MI.getDesc();
1293 // Part of binary is determined by TableGen.
1294 unsigned Binary = getBinaryCodeForInstr(MI);
1296 // Set the conditional execution predicate
1297 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1300 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1302 // Encode saturate bit position.
1303 unsigned Pos = MI.getOperand(1).getImm();
1304 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1306 assert((Pos < 16 || (Pos < 32 &&
1307 TID.Opcode != ARM::SSAT16 &&
1308 TID.Opcode != ARM::USAT16)) &&
1309 "saturate bit position out of range");
1310 Binary |= Pos << 16;
1313 Binary |= getMachineOpValue(MI, 2);
1315 // Encode shift_imm.
1316 if (TID.getNumOperands() == 4) {
1317 unsigned ShiftOp = MI.getOperand(3).getImm();
1318 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1319 if (Opc == ARM_AM::asr)
1321 unsigned ShiftAmt = MI.getOperand(3).getImm();
1322 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1324 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1325 Binary |= ShiftAmt << ARMII::ShiftShift;
1331 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1332 const TargetInstrDesc &TID = MI.getDesc();
1334 if (TID.Opcode == ARM::TPsoft) {
1335 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1338 // Part of binary is determined by TableGn.
1339 unsigned Binary = getBinaryCodeForInstr(MI);
1341 // Set the conditional execution predicate
1342 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344 // Set signed_immed_24 field
1345 Binary |= getMachineOpValue(MI, 0);
1350 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1351 // Remember the base address of the inline jump table.
1352 uintptr_t JTBase = MCE.getCurrentPCValue();
1353 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1354 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1357 // Now emit the jump table entries.
1358 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1359 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1361 // DestBB address - JT base.
1362 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1364 // Absolute DestBB address.
1365 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1370 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1371 const TargetInstrDesc &TID = MI.getDesc();
1373 // Handle jump tables.
1374 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1375 // First emit a ldr pc, [] instruction.
1376 emitDataProcessingInstruction(MI, ARM::PC);
1378 // Then emit the inline jump table.
1380 (TID.Opcode == ARM::BR_JTr)
1381 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1382 emitInlineJumpTable(JTIndex);
1384 } else if (TID.Opcode == ARM::BR_JTm) {
1385 // First emit a ldr pc, [] instruction.
1386 emitLoadStoreInstruction(MI, ARM::PC);
1388 // Then emit the inline jump table.
1389 emitInlineJumpTable(MI.getOperand(3).getIndex());
1393 // Part of binary is determined by TableGn.
1394 unsigned Binary = getBinaryCodeForInstr(MI);
1396 // Set the conditional execution predicate
1397 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1399 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1400 // The return register is LR.
1401 Binary |= getARMRegisterNumbering(ARM::LR);
1403 // otherwise, set the return register
1404 Binary |= getMachineOpValue(MI, 0);
1409 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1410 unsigned RegD = MI.getOperand(OpIdx).getReg();
1411 unsigned Binary = 0;
1412 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1413 RegD = getARMRegisterNumbering(RegD);
1415 Binary |= RegD << ARMII::RegRdShift;
1417 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1418 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1423 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1424 unsigned RegN = MI.getOperand(OpIdx).getReg();
1425 unsigned Binary = 0;
1426 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1427 RegN = getARMRegisterNumbering(RegN);
1429 Binary |= RegN << ARMII::RegRnShift;
1431 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1432 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1437 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1438 unsigned RegM = MI.getOperand(OpIdx).getReg();
1439 unsigned Binary = 0;
1440 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1441 RegM = getARMRegisterNumbering(RegM);
1445 Binary |= ((RegM & 0x1E) >> 1);
1446 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1451 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1452 const TargetInstrDesc &TID = MI.getDesc();
1454 // Part of binary is determined by TableGn.
1455 unsigned Binary = getBinaryCodeForInstr(MI);
1457 // Set the conditional execution predicate
1458 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1461 assert((Binary & ARMII::D_BitShift) == 0 &&
1462 (Binary & ARMII::N_BitShift) == 0 &&
1463 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1466 Binary |= encodeVFPRd(MI, OpIdx++);
1468 // If this is a two-address operand, skip it, e.g. FMACD.
1469 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1473 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1474 Binary |= encodeVFPRn(MI, OpIdx++);
1476 if (OpIdx == TID.getNumOperands() ||
1477 TID.OpInfo[OpIdx].isPredicate() ||
1478 TID.OpInfo[OpIdx].isOptionalDef()) {
1479 // FCMPEZD etc. has only one operand.
1485 Binary |= encodeVFPRm(MI, OpIdx);
1490 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1491 const TargetInstrDesc &TID = MI.getDesc();
1492 unsigned Form = TID.TSFlags & ARMII::FormMask;
1494 // Part of binary is determined by TableGn.
1495 unsigned Binary = getBinaryCodeForInstr(MI);
1497 // Set the conditional execution predicate
1498 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1502 case ARMII::VFPConv1Frm:
1503 case ARMII::VFPConv2Frm:
1504 case ARMII::VFPConv3Frm:
1506 Binary |= encodeVFPRd(MI, 0);
1508 case ARMII::VFPConv4Frm:
1510 Binary |= encodeVFPRn(MI, 0);
1512 case ARMII::VFPConv5Frm:
1514 Binary |= encodeVFPRm(MI, 0);
1520 case ARMII::VFPConv1Frm:
1522 Binary |= encodeVFPRm(MI, 1);
1524 case ARMII::VFPConv2Frm:
1525 case ARMII::VFPConv3Frm:
1527 Binary |= encodeVFPRn(MI, 1);
1529 case ARMII::VFPConv4Frm:
1530 case ARMII::VFPConv5Frm:
1532 Binary |= encodeVFPRd(MI, 1);
1536 if (Form == ARMII::VFPConv5Frm)
1538 Binary |= encodeVFPRn(MI, 2);
1539 else if (Form == ARMII::VFPConv3Frm)
1541 Binary |= encodeVFPRm(MI, 2);
1546 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1547 // Part of binary is determined by TableGn.
1548 unsigned Binary = getBinaryCodeForInstr(MI);
1550 // Set the conditional execution predicate
1551 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1556 Binary |= encodeVFPRd(MI, OpIdx++);
1558 // Encode address base.
1559 const MachineOperand &Base = MI.getOperand(OpIdx++);
1560 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1562 // If there is a non-zero immediate offset, encode it.
1564 const MachineOperand &Offset = MI.getOperand(OpIdx);
1565 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1566 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1567 Binary |= 1 << ARMII::U_BitShift;
1574 // If immediate offset is omitted, default to +0.
1575 Binary |= 1 << ARMII::U_BitShift;
1581 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1582 const TargetInstrDesc &TID = MI.getDesc();
1583 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1585 // Part of binary is determined by TableGn.
1586 unsigned Binary = getBinaryCodeForInstr(MI);
1588 // Set the conditional execution predicate
1589 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1591 // Skip operand 0 of an instruction with base register update.
1596 // Set base address operand
1597 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1599 // Set addressing mode by modifying bits U(23) and P(24)
1600 const MachineOperand &MO = MI.getOperand(OpIdx++);
1601 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1605 Binary |= 0x1 << ARMII::W_BitShift;
1607 // First register is encoded in Dd.
1608 Binary |= encodeVFPRd(MI, OpIdx+2);
1610 // Count the number of registers.
1611 unsigned NumRegs = 1;
1612 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1613 const MachineOperand &MO = MI.getOperand(i);
1614 if (!MO.isReg() || MO.isImplicit())
1618 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1619 // Otherwise, it will be 0, in the case of 32-bit registers.
1621 Binary |= NumRegs * 2;
1628 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1629 unsigned RegD = MI.getOperand(OpIdx).getReg();
1630 unsigned Binary = 0;
1631 RegD = getARMRegisterNumbering(RegD);
1632 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1633 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1637 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1638 unsigned RegN = MI.getOperand(OpIdx).getReg();
1639 unsigned Binary = 0;
1640 RegN = getARMRegisterNumbering(RegN);
1641 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1642 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1646 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1647 unsigned RegM = MI.getOperand(OpIdx).getReg();
1648 unsigned Binary = 0;
1649 RegM = getARMRegisterNumbering(RegM);
1650 Binary |= (RegM & 0xf);
1651 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1655 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1656 /// data-processing instruction to the corresponding Thumb encoding.
1657 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1658 assert((Binary & 0xfe000000) == 0xf2000000 &&
1659 "not an ARM NEON data-processing instruction");
1660 unsigned UBit = (Binary >> 24) & 1;
1661 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1664 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1665 unsigned Binary = getBinaryCodeForInstr(MI);
1667 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1668 const TargetInstrDesc &TID = MI.getDesc();
1669 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1673 } else { // ARMII::NSetLnFrm
1679 // Set the conditional execution predicate
1680 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1682 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1683 RegT = getARMRegisterNumbering(RegT);
1684 Binary |= (RegT << ARMII::RegRdShift);
1685 Binary |= encodeNEONRn(MI, RegNOpIdx);
1688 if ((Binary & (1 << 22)) != 0)
1689 LaneShift = 0; // 8-bit elements
1690 else if ((Binary & (1 << 5)) != 0)
1691 LaneShift = 1; // 16-bit elements
1693 LaneShift = 2; // 32-bit elements
1695 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1696 unsigned Opc1 = Lane >> 2;
1697 unsigned Opc2 = Lane & 3;
1698 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1699 Binary |= (Opc1 << 21);
1700 Binary |= (Opc2 << 5);
1705 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1706 unsigned Binary = getBinaryCodeForInstr(MI);
1708 // Set the conditional execution predicate
1709 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1711 unsigned RegT = MI.getOperand(1).getReg();
1712 RegT = getARMRegisterNumbering(RegT);
1713 Binary |= (RegT << ARMII::RegRdShift);
1714 Binary |= encodeNEONRn(MI, 0);
1718 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1719 unsigned Binary = getBinaryCodeForInstr(MI);
1720 // Destination register is encoded in Dd.
1721 Binary |= encodeNEONRd(MI, 0);
1722 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1723 unsigned Imm = MI.getOperand(1).getImm();
1724 unsigned Op = (Imm >> 12) & 1;
1725 unsigned Cmode = (Imm >> 8) & 0xf;
1726 unsigned I = (Imm >> 7) & 1;
1727 unsigned Imm3 = (Imm >> 4) & 0x7;
1728 unsigned Imm4 = Imm & 0xf;
1729 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1731 Binary = convertNEONDataProcToThumb(Binary);
1735 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1736 const TargetInstrDesc &TID = MI.getDesc();
1737 unsigned Binary = getBinaryCodeForInstr(MI);
1738 // Destination register is encoded in Dd; source register in Dm.
1740 Binary |= encodeNEONRd(MI, OpIdx++);
1741 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1743 Binary |= encodeNEONRm(MI, OpIdx);
1745 Binary = convertNEONDataProcToThumb(Binary);
1746 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1750 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1751 const TargetInstrDesc &TID = MI.getDesc();
1752 unsigned Binary = getBinaryCodeForInstr(MI);
1753 // Destination register is encoded in Dd; source registers in Dn and Dm.
1755 Binary |= encodeNEONRd(MI, OpIdx++);
1756 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1758 Binary |= encodeNEONRn(MI, OpIdx++);
1759 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1761 Binary |= encodeNEONRm(MI, OpIdx);
1763 Binary = convertNEONDataProcToThumb(Binary);
1764 // FIXME: This does not handle VMOVDneon or VMOVQ.
1768 #include "ARMGenCodeEmitter.inc"