1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/PassManager.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMBaseInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getDataLayout()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const MCInstrDesc &MCID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const MCInstrDesc &MCID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val)
172 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
174 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
191 unsigned Op) const { return 0; }
192 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
212 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
216 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
220 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
224 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
226 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
228 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
230 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
232 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
235 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
237 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
239 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
240 unsigned Op) const { return 0; }
241 unsigned getSsatBitPosValue(const MachineInstr &MI,
242 unsigned Op) const { return 0; }
243 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
245 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
248 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
251 // {12} = (U)nsigned (add == '1', sub == '0')
253 const MachineOperand &MO = MI.getOperand(Op);
254 const MachineOperand &MO1 = MI.getOperand(Op + 1);
256 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
259 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
260 int32_t Imm12 = MO1.getImm();
262 Binary = Imm12 & 0xfff;
265 Binary |= (Reg << 13);
269 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
273 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
275 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
277 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
279 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
281 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
283 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
285 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
287 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
289 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
291 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
293 // {12} = (U)nsigned (add == '1', sub == '0')
295 const MachineOperand &MO = MI.getOperand(Op);
296 const MachineOperand &MO1 = MI.getOperand(Op + 1);
298 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
301 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
302 int32_t Imm12 = MO1.getImm();
304 // Special value for #-0
305 if (Imm12 == INT32_MIN)
308 // Immediate is always encoded as positive. The 'U' bit controls add vs
316 uint32_t Binary = Imm12 & 0xfff;
319 Binary |= (Reg << 13);
322 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
325 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
328 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
330 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
332 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
334 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
337 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
338 /// machine operand requires relocation, record the relocation and return
340 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
343 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
345 unsigned getShiftOp(unsigned Imm) const ;
347 /// Routines that handle operands which add machine relocations which are
348 /// fixed up by the relocation stage.
349 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
350 bool MayNeedFarStub, bool Indirect,
351 intptr_t ACPV = 0) const;
352 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
353 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
354 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
355 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
356 intptr_t JTBase = 0) const;
357 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
358 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
359 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
360 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
361 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
362 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
366 char ARMCodeEmitter::ID = 0;
368 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
369 /// code to the specified MCE object.
370 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
371 JITCodeEmitter &JCE) {
372 return new ARMCodeEmitter(TM, JCE);
375 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
376 TargetMachine &Target = const_cast<TargetMachine&>(MF.getTarget());
378 assert((Target.getRelocationModel() != Reloc::Default ||
379 Target.getRelocationModel() != Reloc::Static) &&
380 "JIT relocation model must be set to static or default!");
382 JTI = static_cast<ARMJITInfo*>(Target.getJITInfo());
383 II = static_cast<const ARMBaseInstrInfo*>(Target.getInstrInfo());
384 TD = Target.getDataLayout();
386 Subtarget = &TM.getSubtarget<ARMSubtarget>();
387 MCPEs = &MF.getConstantPool()->getConstants();
389 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
390 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
391 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
392 JTI->Initialize(MF, IsPIC);
393 MMI = &getAnalysis<MachineModuleInfo>();
394 MCE.setModuleInfo(MMI);
397 DEBUG(errs() << "JITTing function '"
398 << MF.getName() << "'\n");
399 MCE.startFunction(MF);
400 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
402 MCE.StartMachineBasicBlock(MBB);
403 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
407 } while (MCE.finishFunction(MF));
412 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
414 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
415 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
416 default: llvm_unreachable("Unknown shift opc!");
417 case ARM_AM::asr: return 2;
418 case ARM_AM::lsl: return 0;
419 case ARM_AM::lsr: return 1;
421 case ARM_AM::rrx: return 3;
425 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
426 /// machine operand requires relocation, record the relocation and return zero.
427 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
428 const MachineOperand &MO,
430 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
431 && "Relocation to this function should be for movt or movw");
434 return static_cast<unsigned>(MO.getImm());
435 else if (MO.isGlobal())
436 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
437 else if (MO.isSymbol())
438 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
440 emitMachineBasicBlock(MO.getMBB(), Reloc);
445 llvm_unreachable("Unsupported operand type for movw/movt");
450 /// getMachineOpValue - Return binary encoding of operand. If the machine
451 /// operand requires relocation, record the relocation and return zero.
452 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
453 const MachineOperand &MO) const {
455 return II->getRegisterInfo().getEncodingValue(MO.getReg());
457 return static_cast<unsigned>(MO.getImm());
458 else if (MO.isGlobal())
459 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
460 else if (MO.isSymbol())
461 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
462 else if (MO.isCPI()) {
463 const MCInstrDesc &MCID = MI.getDesc();
464 // For VFP load, the immediate offset is multiplied by 4.
465 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
466 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
467 emitConstPoolAddress(MO.getIndex(), Reloc);
468 } else if (MO.isJTI())
469 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
471 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
473 llvm_unreachable("Unable to encode MachineOperand!");
477 /// emitGlobalAddress - Emit the specified address to the code stream.
479 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
480 bool MayNeedFarStub, bool Indirect,
481 intptr_t ACPV) const {
482 MachineRelocation MR = Indirect
483 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
484 const_cast<GlobalValue *>(GV),
485 ACPV, MayNeedFarStub)
486 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
487 const_cast<GlobalValue *>(GV), ACPV,
489 MCE.addRelocation(MR);
492 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
493 /// be emitted to the current location in the function, and allow it to be PC
495 void ARMCodeEmitter::
496 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
497 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
501 /// emitConstPoolAddress - Arrange for the address of an constant pool
502 /// to be emitted to the current location in the function, and allow it to be PC
504 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
505 // Tell JIT emitter we'll resolve the address.
506 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
507 Reloc, CPI, 0, true));
510 /// emitJumpTableAddress - Arrange for the address of a jump table to
511 /// be emitted to the current location in the function, and allow it to be PC
513 void ARMCodeEmitter::
514 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
515 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
516 Reloc, JTIndex, 0, true));
519 /// emitMachineBasicBlock - Emit the specified address basic block.
520 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
522 intptr_t JTBase) const {
523 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
527 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
528 DEBUG(errs() << " 0x";
529 errs().write_hex(Binary) << "\n");
530 MCE.emitWordLE(Binary);
533 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
534 DEBUG(errs() << " 0x";
535 errs().write_hex(Binary) << "\n");
536 MCE.emitDWordLE(Binary);
539 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
540 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
542 MCE.processDebugLoc(MI.getDebugLoc(), true);
544 ++NumEmitted; // Keep track of the # of mi's emitted
545 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
547 llvm_unreachable("Unhandled instruction encoding format!");
550 if (MI.getOpcode() == ARM::LEApcrelJT) {
551 // Materialize jumptable address.
552 emitLEApcrelJTInstruction(MI);
555 llvm_unreachable("Unhandled instruction encoding!");
557 emitPseudoInstruction(MI);
560 case ARMII::DPSoRegFrm:
561 emitDataProcessingInstruction(MI);
565 emitLoadStoreInstruction(MI);
567 case ARMII::LdMiscFrm:
568 case ARMII::StMiscFrm:
569 emitMiscLoadStoreInstruction(MI);
571 case ARMII::LdStMulFrm:
572 emitLoadStoreMultipleInstruction(MI);
575 emitMulFrmInstruction(MI);
578 emitExtendInstruction(MI);
580 case ARMII::ArithMiscFrm:
581 emitMiscArithInstruction(MI);
584 emitSaturateInstruction(MI);
587 emitBranchInstruction(MI);
589 case ARMII::BrMiscFrm:
590 emitMiscBranchInstruction(MI);
593 case ARMII::VFPUnaryFrm:
594 case ARMII::VFPBinaryFrm:
595 emitVFPArithInstruction(MI);
597 case ARMII::VFPConv1Frm:
598 case ARMII::VFPConv2Frm:
599 case ARMII::VFPConv3Frm:
600 case ARMII::VFPConv4Frm:
601 case ARMII::VFPConv5Frm:
602 emitVFPConversionInstruction(MI);
604 case ARMII::VFPLdStFrm:
605 emitVFPLoadStoreInstruction(MI);
607 case ARMII::VFPLdStMulFrm:
608 emitVFPLoadStoreMultipleInstruction(MI);
611 // NEON instructions.
612 case ARMII::NGetLnFrm:
613 case ARMII::NSetLnFrm:
614 emitNEONLaneInstruction(MI);
617 emitNEONDupInstruction(MI);
619 case ARMII::N1RegModImmFrm:
620 emitNEON1RegModImmInstruction(MI);
622 case ARMII::N2RegFrm:
623 emitNEON2RegInstruction(MI);
625 case ARMII::N3RegFrm:
626 emitNEON3RegInstruction(MI);
629 MCE.processDebugLoc(MI.getDebugLoc(), false);
632 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
633 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
634 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
635 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
637 // Remember the CONSTPOOL_ENTRY address for later relocation.
638 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
640 // Emit constpool island entry. In most cases, the actual values will be
641 // resolved and relocated after code emission.
642 if (MCPE.isMachineConstantPoolEntry()) {
643 ARMConstantPoolValue *ACPV =
644 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
646 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
647 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
649 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
650 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
652 Reloc::Model RelocM = TM.getRelocationModel();
653 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
655 Subtarget->GVIsIndirectSymbol(GV, RelocM),
658 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
659 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
663 const Constant *CV = MCPE.Val.ConstVal;
666 errs() << " ** Constant pool #" << CPI << " @ "
667 << (void*)MCE.getCurrentPCValue() << " ";
668 if (const Function *F = dyn_cast<Function>(CV))
669 errs() << F->getName();
675 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
676 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
678 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
679 uint32_t Val = uint32_t(*CI->getValue().getRawData());
681 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
682 if (CFP->getType()->isFloatTy())
683 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
684 else if (CFP->getType()->isDoubleTy())
685 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
687 llvm_unreachable("Unable to handle this constantpool entry!");
690 llvm_unreachable("Unable to handle this constantpool entry!");
695 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
696 const MachineOperand &MO0 = MI.getOperand(0);
697 const MachineOperand &MO1 = MI.getOperand(1);
699 // Emit the 'movw' instruction.
700 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
702 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
704 // Set the conditional execution predicate.
705 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
708 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
710 // Encode imm16 as imm4:imm12
711 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
712 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
715 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
716 // Emit the 'movt' instruction.
717 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
719 // Set the conditional execution predicate.
720 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
723 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
725 // Encode imm16 as imm4:imm1, same as movw above.
726 Binary |= Hi16 & 0xFFF;
727 Binary |= ((Hi16 >> 12) & 0xF) << 16;
731 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
732 const MachineOperand &MO0 = MI.getOperand(0);
733 const MachineOperand &MO1 = MI.getOperand(1);
734 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
735 "Not a valid so_imm value!");
736 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
737 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
739 // Emit the 'mov' instruction.
740 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
742 // Set the conditional execution predicate.
743 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
746 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
749 // Set bit I(25) to identify this is the immediate form of <shifter_op>
750 Binary |= 1 << ARMII::I_BitShift;
751 Binary |= getMachineSoImmOpValue(V1);
754 // Now the 'orr' instruction.
755 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
757 // Set the conditional execution predicate.
758 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
761 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
764 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
767 // Set bit I(25) to identify this is the immediate form of <shifter_op>
768 Binary |= 1 << ARMII::I_BitShift;
769 Binary |= getMachineSoImmOpValue(V2);
773 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
774 // It's basically add r, pc, (LJTI - $+8)
776 const MCInstrDesc &MCID = MI.getDesc();
778 // Emit the 'add' instruction.
779 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
781 // Set the conditional execution predicate
782 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
784 // Encode S bit if MI modifies CPSR.
785 Binary |= getAddrModeSBit(MI, MCID);
788 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
790 // Encode Rn which is PC.
791 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
793 // Encode the displacement.
794 Binary |= 1 << ARMII::I_BitShift;
795 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
800 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
801 unsigned Opcode = MI.getDesc().Opcode;
803 // Part of binary is determined by TableGn.
804 unsigned Binary = getBinaryCodeForInstr(MI);
806 // Set the conditional execution predicate
807 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
809 // Encode S bit if MI modifies CPSR.
810 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
811 Binary |= 1 << ARMII::S_BitShift;
813 // Encode register def if there is one.
814 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
816 // Encode the shift operation.
823 case ARM::MOVsrl_flag:
825 Binary |= (0x2 << 4) | (1 << 7);
827 case ARM::MOVsra_flag:
829 Binary |= (0x4 << 4) | (1 << 7);
833 // Encode register Rm.
834 Binary |= getMachineOpValue(MI, 1);
839 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
840 DEBUG(errs() << " ** LPC" << LabelID << " @ "
841 << (void*)MCE.getCurrentPCValue() << '\n');
842 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
845 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
846 unsigned Opcode = MI.getDesc().Opcode;
849 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
851 case ARM::BMOVPCRX_CALL: {
852 // First emit mov lr, pc
853 unsigned Binary = 0x01a0e00f;
854 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
857 // and then emit the branch.
858 emitMiscBranchInstruction(MI);
861 case TargetOpcode::INLINEASM: {
862 // We allow inline assembler nodes with empty bodies - they can
863 // implicitly define registers, which is ok for JIT.
864 if (MI.getOperand(0).getSymbolName()[0]) {
865 report_fatal_error("JIT does not support inline asm!");
869 case TargetOpcode::PROLOG_LABEL:
870 case TargetOpcode::EH_LABEL:
871 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
873 case TargetOpcode::IMPLICIT_DEF:
874 case TargetOpcode::KILL:
877 case ARM::CONSTPOOL_ENTRY:
878 emitConstPoolInstruction(MI);
881 // Remember of the address of the PC label for relocation later.
882 addPCLabel(MI.getOperand(2).getImm());
883 // PICADD is just an add instruction that implicitly read pc.
884 emitDataProcessingInstruction(MI, 0, ARM::PC);
891 // Remember of the address of the PC label for relocation later.
892 addPCLabel(MI.getOperand(2).getImm());
893 // These are just load / store instructions that implicitly read pc.
894 emitLoadStoreInstruction(MI, 0, ARM::PC);
901 // Remember of the address of the PC label for relocation later.
902 addPCLabel(MI.getOperand(2).getImm());
903 // These are just load / store instructions that implicitly read pc.
904 emitMiscLoadStoreInstruction(MI, ARM::PC);
909 // Two instructions to materialize a constant.
910 if (Subtarget->hasV6T2Ops())
911 emitMOVi32immInstruction(MI);
913 emitMOVi2piecesInstruction(MI);
916 case ARM::LEApcrelJT:
917 // Materialize jumptable address.
918 emitLEApcrelJTInstruction(MI);
921 case ARM::MOVsrl_flag:
922 case ARM::MOVsra_flag:
923 emitPseudoMoveInstruction(MI);
928 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
929 const MCInstrDesc &MCID,
930 const MachineOperand &MO,
932 unsigned Binary = getMachineOpValue(MI, MO);
934 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
935 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
936 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
938 // Encode the shift opcode.
940 unsigned Rs = MO1.getReg();
942 // Set shift operand (bit[7:4]).
947 // RRX - 0110 and bit[11:8] clear.
949 default: llvm_unreachable("Unknown shift opc!");
950 case ARM_AM::lsl: SBits = 0x1; break;
951 case ARM_AM::lsr: SBits = 0x3; break;
952 case ARM_AM::asr: SBits = 0x5; break;
953 case ARM_AM::ror: SBits = 0x7; break;
954 case ARM_AM::rrx: SBits = 0x6; break;
957 // Set shift operand (bit[6:4]).
963 default: llvm_unreachable("Unknown shift opc!");
964 case ARM_AM::lsl: SBits = 0x0; break;
965 case ARM_AM::lsr: SBits = 0x2; break;
966 case ARM_AM::asr: SBits = 0x4; break;
967 case ARM_AM::ror: SBits = 0x6; break;
970 Binary |= SBits << 4;
971 if (SOpc == ARM_AM::rrx)
974 // Encode the shift operation Rs or shift_imm (except rrx).
976 // Encode Rs bit[11:8].
977 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
978 return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
981 // Encode shift_imm bit[11:7].
982 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
985 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
986 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
987 assert(SoImmVal != -1 && "Not a valid so_imm value!");
989 // Encode rotate_imm.
990 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
991 << ARMII::SoRotImmShift;
994 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
998 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
999 const MCInstrDesc &MCID) const {
1000 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
1001 const MachineOperand &MO = MI.getOperand(i-1);
1002 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1003 return 1 << ARMII::S_BitShift;
1008 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1009 unsigned ImplicitRd,
1010 unsigned ImplicitRn) {
1011 const MCInstrDesc &MCID = MI.getDesc();
1013 // Part of binary is determined by TableGn.
1014 unsigned Binary = getBinaryCodeForInstr(MI);
1016 // Set the conditional execution predicate
1017 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1019 // Encode S bit if MI modifies CPSR.
1020 Binary |= getAddrModeSBit(MI, MCID);
1022 // Encode register def if there is one.
1023 unsigned NumDefs = MCID.getNumDefs();
1026 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1027 else if (ImplicitRd)
1028 // Special handling for implicit use (e.g. PC).
1029 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1031 if (MCID.Opcode == ARM::MOVi16) {
1032 // Get immediate from MI.
1033 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1034 ARM::reloc_arm_movw);
1035 // Encode imm which is the same as in emitMOVi32immInstruction().
1036 Binary |= Lo16 & 0xFFF;
1037 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1040 } else if(MCID.Opcode == ARM::MOVTi16) {
1041 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1042 ARM::reloc_arm_movt) >> 16);
1043 Binary |= Hi16 & 0xFFF;
1044 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1047 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1048 uint32_t v = ~MI.getOperand(2).getImm();
1049 int32_t lsb = countTrailingZeros(v);
1050 int32_t msb = (32 - countLeadingZeros(v)) - 1;
1051 // Instr{20-16} = msb, Instr{11-7} = lsb
1052 Binary |= (msb & 0x1F) << 16;
1053 Binary |= (lsb & 0x1F) << 7;
1056 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1057 // Encode Rn in Instr{0-3}
1058 Binary |= getMachineOpValue(MI, OpIdx++);
1060 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1061 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1063 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1064 Binary |= (widthm1 & 0x1F) << 16;
1065 Binary |= (lsb & 0x1F) << 7;
1070 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1071 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1074 // Encode first non-shifter register operand if there is one.
1075 bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1078 // Special handling for implicit use (e.g. PC).
1079 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1081 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1086 // Encode shifter operand.
1087 const MachineOperand &MO = MI.getOperand(OpIdx);
1088 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1090 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1095 // Encode register Rm.
1096 emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg()));
1101 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1106 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1107 unsigned ImplicitRd,
1108 unsigned ImplicitRn) {
1109 const MCInstrDesc &MCID = MI.getDesc();
1110 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1111 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1113 // Part of binary is determined by TableGn.
1114 unsigned Binary = getBinaryCodeForInstr(MI);
1116 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1117 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1118 MI.getOpcode() == ARM::STRi12) {
1123 // Set the conditional execution predicate
1124 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1128 // Operand 0 of a pre- and post-indexed store is the address base
1129 // writeback. Skip it.
1130 bool Skipped = false;
1131 if (IsPrePost && Form == ARMII::StFrm) {
1136 // Set first operand
1138 // Special handling for implicit use (e.g. PC).
1139 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1141 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1143 // Set second operand
1145 // Special handling for implicit use (e.g. PC).
1146 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1148 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1150 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1151 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1154 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1155 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1156 ? 0 : MI.getOperand(OpIdx+1).getImm();
1158 // Set bit U(23) according to sign of immed value (positive or negative).
1159 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1161 if (!MO2.getReg()) { // is immediate
1162 if (ARM_AM::getAM2Offset(AM2Opc))
1163 // Set the value of offset_12 field
1164 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1169 // Set bit I(25), because this is not in immediate encoding.
1170 Binary |= 1 << ARMII::I_BitShift;
1171 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1172 // Set bit[3:0] to the corresponding Rm register
1173 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1175 // If this instr is in scaled register offset/index instruction, set
1176 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1177 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1178 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1179 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1185 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1186 unsigned ImplicitRn) {
1187 const MCInstrDesc &MCID = MI.getDesc();
1188 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1189 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1191 // Part of binary is determined by TableGn.
1192 unsigned Binary = getBinaryCodeForInstr(MI);
1194 // Set the conditional execution predicate
1195 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1199 // Operand 0 of a pre- and post-indexed store is the address base
1200 // writeback. Skip it.
1201 bool Skipped = false;
1202 if (IsPrePost && Form == ARMII::StMiscFrm) {
1207 // Set first operand
1208 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1210 // Skip LDRD and STRD's second operand.
1211 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1214 // Set second operand
1216 // Special handling for implicit use (e.g. PC).
1217 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1219 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1221 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1222 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1225 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1226 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1227 ? 0 : MI.getOperand(OpIdx+1).getImm();
1229 // Set bit U(23) according to sign of immed value (positive or negative)
1230 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1233 // If this instr is in register offset/index encoding, set bit[3:0]
1234 // to the corresponding Rm register.
1236 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1241 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1242 Binary |= 1 << ARMII::AM3_I_BitShift;
1243 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1245 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1246 Binary |= (ImmOffs & 0xF); // immedL
1252 static unsigned getAddrModeUPBits(unsigned Mode) {
1253 unsigned Binary = 0;
1255 // Set addressing mode by modifying bits U(23) and P(24)
1256 // IA - Increment after - bit U = 1 and bit P = 0
1257 // IB - Increment before - bit U = 1 and bit P = 1
1258 // DA - Decrement after - bit U = 0 and bit P = 0
1259 // DB - Decrement before - bit U = 0 and bit P = 1
1261 default: llvm_unreachable("Unknown addressing sub-mode!");
1262 case ARM_AM::da: break;
1263 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1264 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1265 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1271 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1272 const MCInstrDesc &MCID = MI.getDesc();
1273 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1275 // Part of binary is determined by TableGn.
1276 unsigned Binary = getBinaryCodeForInstr(MI);
1278 // Set the conditional execution predicate
1279 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1281 // Skip operand 0 of an instruction with base register update.
1286 // Set base address operand
1287 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1289 // Set addressing mode by modifying bits U(23) and P(24)
1290 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1291 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1295 Binary |= 0x1 << ARMII::W_BitShift;
1298 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1299 const MachineOperand &MO = MI.getOperand(i);
1300 if (!MO.isReg() || MO.isImplicit())
1302 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg());
1303 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1305 Binary |= 0x1 << RegNum;
1311 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1312 const MCInstrDesc &MCID = MI.getDesc();
1314 // Part of binary is determined by TableGn.
1315 unsigned Binary = getBinaryCodeForInstr(MI);
1317 // Set the conditional execution predicate
1318 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1320 // Encode S bit if MI modifies CPSR.
1321 Binary |= getAddrModeSBit(MI, MCID);
1323 // 32x32->64bit operations have two destination registers. The number
1324 // of register definitions will tell us if that's what we're dealing with.
1326 if (MCID.getNumDefs() == 2)
1327 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1330 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1333 Binary |= getMachineOpValue(MI, OpIdx++);
1336 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1338 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1339 // it as Rn (for multiply, that's in the same offset as RdLo.
1340 if (MCID.getNumOperands() > OpIdx &&
1341 !MCID.OpInfo[OpIdx].isPredicate() &&
1342 !MCID.OpInfo[OpIdx].isOptionalDef())
1343 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1348 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1349 const MCInstrDesc &MCID = MI.getDesc();
1351 // Part of binary is determined by TableGn.
1352 unsigned Binary = getBinaryCodeForInstr(MI);
1354 // Set the conditional execution predicate
1355 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1360 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1362 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1363 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1365 // Two register operand form.
1367 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1370 Binary |= getMachineOpValue(MI, MO2);
1373 Binary |= getMachineOpValue(MI, MO1);
1376 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1377 if (MI.getOperand(OpIdx).isImm() &&
1378 !MCID.OpInfo[OpIdx].isPredicate() &&
1379 !MCID.OpInfo[OpIdx].isOptionalDef())
1380 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1385 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1386 const MCInstrDesc &MCID = MI.getDesc();
1388 // Part of binary is determined by TableGn.
1389 unsigned Binary = getBinaryCodeForInstr(MI);
1391 // Set the conditional execution predicate
1392 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1394 // PKH instructions are finished at this point
1395 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1403 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1405 const MachineOperand &MO = MI.getOperand(OpIdx++);
1406 if (OpIdx == MCID.getNumOperands() ||
1407 MCID.OpInfo[OpIdx].isPredicate() ||
1408 MCID.OpInfo[OpIdx].isOptionalDef()) {
1409 // Encode Rm and it's done.
1410 Binary |= getMachineOpValue(MI, MO);
1416 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1419 Binary |= getMachineOpValue(MI, OpIdx++);
1421 // Encode shift_imm.
1422 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1423 if (MCID.Opcode == ARM::PKHTB) {
1424 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1428 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1429 Binary |= ShiftAmt << ARMII::ShiftShift;
1434 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1435 const MCInstrDesc &MCID = MI.getDesc();
1437 // Part of binary is determined by TableGen.
1438 unsigned Binary = getBinaryCodeForInstr(MI);
1440 // Set the conditional execution predicate
1441 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1444 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1446 // Encode saturate bit position.
1447 unsigned Pos = MI.getOperand(1).getImm();
1448 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1450 assert((Pos < 16 || (Pos < 32 &&
1451 MCID.Opcode != ARM::SSAT16 &&
1452 MCID.Opcode != ARM::USAT16)) &&
1453 "saturate bit position out of range");
1454 Binary |= Pos << 16;
1457 Binary |= getMachineOpValue(MI, 2);
1459 // Encode shift_imm.
1460 if (MCID.getNumOperands() == 4) {
1461 unsigned ShiftOp = MI.getOperand(3).getImm();
1462 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1463 if (Opc == ARM_AM::asr)
1465 unsigned ShiftAmt = MI.getOperand(3).getImm();
1466 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1468 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1469 Binary |= ShiftAmt << ARMII::ShiftShift;
1475 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1476 const MCInstrDesc &MCID = MI.getDesc();
1478 if (MCID.Opcode == ARM::TPsoft) {
1479 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1482 // Part of binary is determined by TableGn.
1483 unsigned Binary = getBinaryCodeForInstr(MI);
1485 // Set the conditional execution predicate
1486 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1488 // Set signed_immed_24 field
1489 Binary |= getMachineOpValue(MI, 0);
1494 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1495 // Remember the base address of the inline jump table.
1496 uintptr_t JTBase = MCE.getCurrentPCValue();
1497 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1498 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1501 // Now emit the jump table entries.
1502 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1503 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1505 // DestBB address - JT base.
1506 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1508 // Absolute DestBB address.
1509 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1514 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1515 const MCInstrDesc &MCID = MI.getDesc();
1517 // Handle jump tables.
1518 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1519 // First emit a ldr pc, [] instruction.
1520 emitDataProcessingInstruction(MI, ARM::PC);
1522 // Then emit the inline jump table.
1524 (MCID.Opcode == ARM::BR_JTr)
1525 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1526 emitInlineJumpTable(JTIndex);
1528 } else if (MCID.Opcode == ARM::BR_JTm) {
1529 // First emit a ldr pc, [] instruction.
1530 emitLoadStoreInstruction(MI, ARM::PC);
1532 // Then emit the inline jump table.
1533 emitInlineJumpTable(MI.getOperand(3).getIndex());
1537 // Part of binary is determined by TableGn.
1538 unsigned Binary = getBinaryCodeForInstr(MI);
1540 // Set the conditional execution predicate
1541 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1543 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1544 // The return register is LR.
1545 Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR);
1547 // otherwise, set the return register
1548 Binary |= getMachineOpValue(MI, 0);
1553 unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
1554 unsigned OpIdx) const {
1555 unsigned RegD = MI.getOperand(OpIdx).getReg();
1556 unsigned Binary = 0;
1557 bool isSPVFP = ARM::SPRRegClass.contains(RegD);
1558 RegD = II->getRegisterInfo().getEncodingValue(RegD);
1560 Binary |= RegD << ARMII::RegRdShift;
1562 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1563 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1568 unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
1569 unsigned OpIdx) const {
1570 unsigned RegN = MI.getOperand(OpIdx).getReg();
1571 unsigned Binary = 0;
1572 bool isSPVFP = ARM::SPRRegClass.contains(RegN);
1573 RegN = II->getRegisterInfo().getEncodingValue(RegN);
1575 Binary |= RegN << ARMII::RegRnShift;
1577 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1578 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1583 unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
1584 unsigned OpIdx) const {
1585 unsigned RegM = MI.getOperand(OpIdx).getReg();
1586 unsigned Binary = 0;
1587 bool isSPVFP = ARM::SPRRegClass.contains(RegM);
1588 RegM = II->getRegisterInfo().getEncodingValue(RegM);
1592 Binary |= ((RegM & 0x1E) >> 1);
1593 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1598 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1599 const MCInstrDesc &MCID = MI.getDesc();
1601 // Part of binary is determined by TableGn.
1602 unsigned Binary = getBinaryCodeForInstr(MI);
1604 // Set the conditional execution predicate
1605 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1608 assert((Binary & ARMII::D_BitShift) == 0 &&
1609 (Binary & ARMII::N_BitShift) == 0 &&
1610 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1613 Binary |= encodeVFPRd(MI, OpIdx++);
1615 // If this is a two-address operand, skip it, e.g. FMACD.
1616 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1620 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1621 Binary |= encodeVFPRn(MI, OpIdx++);
1623 if (OpIdx == MCID.getNumOperands() ||
1624 MCID.OpInfo[OpIdx].isPredicate() ||
1625 MCID.OpInfo[OpIdx].isOptionalDef()) {
1626 // FCMPEZD etc. has only one operand.
1632 Binary |= encodeVFPRm(MI, OpIdx);
1637 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1638 const MCInstrDesc &MCID = MI.getDesc();
1639 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1641 // Part of binary is determined by TableGn.
1642 unsigned Binary = getBinaryCodeForInstr(MI);
1644 // Set the conditional execution predicate
1645 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1649 case ARMII::VFPConv1Frm:
1650 case ARMII::VFPConv2Frm:
1651 case ARMII::VFPConv3Frm:
1653 Binary |= encodeVFPRd(MI, 0);
1655 case ARMII::VFPConv4Frm:
1657 Binary |= encodeVFPRn(MI, 0);
1659 case ARMII::VFPConv5Frm:
1661 Binary |= encodeVFPRm(MI, 0);
1667 case ARMII::VFPConv1Frm:
1669 Binary |= encodeVFPRm(MI, 1);
1671 case ARMII::VFPConv2Frm:
1672 case ARMII::VFPConv3Frm:
1674 Binary |= encodeVFPRn(MI, 1);
1676 case ARMII::VFPConv4Frm:
1677 case ARMII::VFPConv5Frm:
1679 Binary |= encodeVFPRd(MI, 1);
1683 if (Form == ARMII::VFPConv5Frm)
1685 Binary |= encodeVFPRn(MI, 2);
1686 else if (Form == ARMII::VFPConv3Frm)
1688 Binary |= encodeVFPRm(MI, 2);
1693 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1694 // Part of binary is determined by TableGn.
1695 unsigned Binary = getBinaryCodeForInstr(MI);
1697 // Set the conditional execution predicate
1698 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1703 Binary |= encodeVFPRd(MI, OpIdx++);
1705 // Encode address base.
1706 const MachineOperand &Base = MI.getOperand(OpIdx++);
1707 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1709 // If there is a non-zero immediate offset, encode it.
1711 const MachineOperand &Offset = MI.getOperand(OpIdx);
1712 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1713 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1714 Binary |= 1 << ARMII::U_BitShift;
1721 // If immediate offset is omitted, default to +0.
1722 Binary |= 1 << ARMII::U_BitShift;
1728 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1729 const MCInstrDesc &MCID = MI.getDesc();
1730 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1732 // Part of binary is determined by TableGn.
1733 unsigned Binary = getBinaryCodeForInstr(MI);
1735 // Set the conditional execution predicate
1736 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1738 // Skip operand 0 of an instruction with base register update.
1743 // Set base address operand
1744 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1746 // Set addressing mode by modifying bits U(23) and P(24)
1747 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1748 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1752 Binary |= 0x1 << ARMII::W_BitShift;
1754 // First register is encoded in Dd.
1755 Binary |= encodeVFPRd(MI, OpIdx+2);
1757 // Count the number of registers.
1758 unsigned NumRegs = 1;
1759 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1760 const MachineOperand &MO = MI.getOperand(i);
1761 if (!MO.isReg() || MO.isImplicit())
1765 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1766 // Otherwise, it will be 0, in the case of 32-bit registers.
1768 Binary |= NumRegs * 2;
1775 unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
1776 unsigned OpIdx) const {
1777 unsigned RegD = MI.getOperand(OpIdx).getReg();
1778 unsigned Binary = 0;
1779 RegD = II->getRegisterInfo().getEncodingValue(RegD);
1780 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1781 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1785 unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI,
1786 unsigned OpIdx) const {
1787 unsigned RegN = MI.getOperand(OpIdx).getReg();
1788 unsigned Binary = 0;
1789 RegN = II->getRegisterInfo().getEncodingValue(RegN);
1790 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1791 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1795 unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI,
1796 unsigned OpIdx) const {
1797 unsigned RegM = MI.getOperand(OpIdx).getReg();
1798 unsigned Binary = 0;
1799 RegM = II->getRegisterInfo().getEncodingValue(RegM);
1800 Binary |= (RegM & 0xf);
1801 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1805 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1806 /// data-processing instruction to the corresponding Thumb encoding.
1807 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1808 assert((Binary & 0xfe000000) == 0xf2000000 &&
1809 "not an ARM NEON data-processing instruction");
1810 unsigned UBit = (Binary >> 24) & 1;
1811 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1814 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1815 unsigned Binary = getBinaryCodeForInstr(MI);
1817 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1818 const MCInstrDesc &MCID = MI.getDesc();
1819 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1823 } else { // ARMII::NSetLnFrm
1829 // Set the conditional execution predicate
1830 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1832 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1833 RegT = II->getRegisterInfo().getEncodingValue(RegT);
1834 Binary |= (RegT << ARMII::RegRdShift);
1835 Binary |= encodeNEONRn(MI, RegNOpIdx);
1838 if ((Binary & (1 << 22)) != 0)
1839 LaneShift = 0; // 8-bit elements
1840 else if ((Binary & (1 << 5)) != 0)
1841 LaneShift = 1; // 16-bit elements
1843 LaneShift = 2; // 32-bit elements
1845 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1846 unsigned Opc1 = Lane >> 2;
1847 unsigned Opc2 = Lane & 3;
1848 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1849 Binary |= (Opc1 << 21);
1850 Binary |= (Opc2 << 5);
1855 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1856 unsigned Binary = getBinaryCodeForInstr(MI);
1858 // Set the conditional execution predicate
1859 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1861 unsigned RegT = MI.getOperand(1).getReg();
1862 RegT = II->getRegisterInfo().getEncodingValue(RegT);
1863 Binary |= (RegT << ARMII::RegRdShift);
1864 Binary |= encodeNEONRn(MI, 0);
1868 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1869 unsigned Binary = getBinaryCodeForInstr(MI);
1870 // Destination register is encoded in Dd.
1871 Binary |= encodeNEONRd(MI, 0);
1872 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1873 unsigned Imm = MI.getOperand(1).getImm();
1874 unsigned Op = (Imm >> 12) & 1;
1875 unsigned Cmode = (Imm >> 8) & 0xf;
1876 unsigned I = (Imm >> 7) & 1;
1877 unsigned Imm3 = (Imm >> 4) & 0x7;
1878 unsigned Imm4 = Imm & 0xf;
1879 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1881 Binary = convertNEONDataProcToThumb(Binary);
1885 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1886 const MCInstrDesc &MCID = MI.getDesc();
1887 unsigned Binary = getBinaryCodeForInstr(MI);
1888 // Destination register is encoded in Dd; source register in Dm.
1890 Binary |= encodeNEONRd(MI, OpIdx++);
1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1893 Binary |= encodeNEONRm(MI, OpIdx);
1895 Binary = convertNEONDataProcToThumb(Binary);
1896 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1900 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1901 const MCInstrDesc &MCID = MI.getDesc();
1902 unsigned Binary = getBinaryCodeForInstr(MI);
1903 // Destination register is encoded in Dd; source registers in Dn and Dm.
1905 Binary |= encodeNEONRd(MI, OpIdx++);
1906 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1908 Binary |= encodeNEONRn(MI, OpIdx++);
1909 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1911 Binary |= encodeNEONRm(MI, OpIdx);
1913 Binary = convertNEONDataProcToThumb(Binary);
1914 // FIXME: This does not handle VMOVDneon or VMOVQ.
1918 #include "ARMGenCodeEmitter.inc"