1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
199 unsigned Op) const { return 0; }
200 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
202 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
205 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
208 // {12} = (U)nsigned (add == '1', sub == '0')
210 const MachineOperand &MO = MI.getOperand(Op);
211 const MachineOperand &MO1 = MI.getOperand(Op + 1);
213 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
216 unsigned Reg = getARMRegisterNumbering(MO.getReg());
217 int32_t Imm12 = MO1.getImm();
219 Binary = Imm12 & 0xfff;
222 Binary |= (Reg << 13);
226 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
230 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
232 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
234 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
236 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
238 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
240 // {12} = (U)nsigned (add == '1', sub == '0')
242 const MachineOperand &MO = MI.getOperand(Op);
243 const MachineOperand &MO1 = MI.getOperand(Op + 1);
245 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
248 unsigned Reg = getARMRegisterNumbering(MO.getReg());
249 int32_t Imm12 = MO1.getImm();
251 // Special value for #-0
252 if (Imm12 == INT32_MIN)
255 // Immediate is always encoded as positive. The 'U' bit controls add vs
263 uint32_t Binary = Imm12 & 0xfff;
266 Binary |= (Reg << 13);
269 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
272 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
275 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
276 /// machine operand requires relocation, record the relocation and return
278 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
281 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
283 unsigned getShiftOp(unsigned Imm) const ;
285 /// Routines that handle operands which add machine relocations which are
286 /// fixed up by the relocation stage.
287 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
288 bool MayNeedFarStub, bool Indirect,
289 intptr_t ACPV = 0) const;
290 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
291 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
292 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
293 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
294 intptr_t JTBase = 0) const;
298 char ARMCodeEmitter::ID = 0;
300 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
301 /// code to the specified MCE object.
302 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
303 JITCodeEmitter &JCE) {
304 return new ARMCodeEmitter(TM, JCE);
307 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
308 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
309 MF.getTarget().getRelocationModel() != Reloc::Static) &&
310 "JIT relocation model must be set to static or default!");
311 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
312 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
313 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
314 Subtarget = &TM.getSubtarget<ARMSubtarget>();
315 MCPEs = &MF.getConstantPool()->getConstants();
317 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
318 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
319 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
320 JTI->Initialize(MF, IsPIC);
321 MMI = &getAnalysis<MachineModuleInfo>();
322 MCE.setModuleInfo(MMI);
325 DEBUG(errs() << "JITTing function '"
326 << MF.getFunction()->getName() << "'\n");
327 MCE.startFunction(MF);
328 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
330 MCE.StartMachineBasicBlock(MBB);
331 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
335 } while (MCE.finishFunction(MF));
340 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
342 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
343 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
344 default: llvm_unreachable("Unknown shift opc!");
345 case ARM_AM::asr: return 2;
346 case ARM_AM::lsl: return 0;
347 case ARM_AM::lsr: return 1;
349 case ARM_AM::rrx: return 3;
354 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
355 /// machine operand requires relocation, record the relocation and return zero.
356 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
357 const MachineOperand &MO,
359 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
360 && "Relocation to this function should be for movt or movw");
363 return static_cast<unsigned>(MO.getImm());
364 else if (MO.isGlobal())
365 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
366 else if (MO.isSymbol())
367 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
369 emitMachineBasicBlock(MO.getMBB(), Reloc);
374 llvm_unreachable("Unsupported operand type for movw/movt");
379 /// getMachineOpValue - Return binary encoding of operand. If the machine
380 /// operand requires relocation, record the relocation and return zero.
381 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
382 const MachineOperand &MO) const {
384 return getARMRegisterNumbering(MO.getReg());
386 return static_cast<unsigned>(MO.getImm());
387 else if (MO.isGlobal())
388 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
389 else if (MO.isSymbol())
390 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
391 else if (MO.isCPI()) {
392 const TargetInstrDesc &TID = MI.getDesc();
393 // For VFP load, the immediate offset is multiplied by 4.
394 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
395 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
396 emitConstPoolAddress(MO.getIndex(), Reloc);
397 } else if (MO.isJTI())
398 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
400 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
402 llvm_unreachable("Unable to encode MachineOperand!");
406 /// emitGlobalAddress - Emit the specified address to the code stream.
408 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
409 bool MayNeedFarStub, bool Indirect,
410 intptr_t ACPV) const {
411 MachineRelocation MR = Indirect
412 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
413 const_cast<GlobalValue *>(GV),
414 ACPV, MayNeedFarStub)
415 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
416 const_cast<GlobalValue *>(GV), ACPV,
418 MCE.addRelocation(MR);
421 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
422 /// be emitted to the current location in the function, and allow it to be PC
424 void ARMCodeEmitter::
425 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
426 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
430 /// emitConstPoolAddress - Arrange for the address of an constant pool
431 /// to be emitted to the current location in the function, and allow it to be PC
433 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
434 // Tell JIT emitter we'll resolve the address.
435 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
436 Reloc, CPI, 0, true));
439 /// emitJumpTableAddress - Arrange for the address of a jump table to
440 /// be emitted to the current location in the function, and allow it to be PC
442 void ARMCodeEmitter::
443 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
444 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
445 Reloc, JTIndex, 0, true));
448 /// emitMachineBasicBlock - Emit the specified address basic block.
449 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
451 intptr_t JTBase) const {
452 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
456 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
457 DEBUG(errs() << " 0x";
458 errs().write_hex(Binary) << "\n");
459 MCE.emitWordLE(Binary);
462 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
463 DEBUG(errs() << " 0x";
464 errs().write_hex(Binary) << "\n");
465 MCE.emitDWordLE(Binary);
468 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
469 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
471 MCE.processDebugLoc(MI.getDebugLoc(), true);
473 ++NumEmitted; // Keep track of the # of mi's emitted
474 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
476 llvm_unreachable("Unhandled instruction encoding format!");
480 if (MI.getOpcode() == ARM::LEApcrelJT) {
481 // Materialize jumptable address.
482 emitLEApcrelJTInstruction(MI);
485 llvm_unreachable("Unhandled instruction encoding!");
488 emitPseudoInstruction(MI);
491 case ARMII::DPSoRegFrm:
492 emitDataProcessingInstruction(MI);
496 emitLoadStoreInstruction(MI);
498 case ARMII::LdMiscFrm:
499 case ARMII::StMiscFrm:
500 emitMiscLoadStoreInstruction(MI);
502 case ARMII::LdStMulFrm:
503 emitLoadStoreMultipleInstruction(MI);
506 emitMulFrmInstruction(MI);
509 emitExtendInstruction(MI);
511 case ARMII::ArithMiscFrm:
512 emitMiscArithInstruction(MI);
515 emitSaturateInstruction(MI);
518 emitBranchInstruction(MI);
520 case ARMII::BrMiscFrm:
521 emitMiscBranchInstruction(MI);
524 case ARMII::VFPUnaryFrm:
525 case ARMII::VFPBinaryFrm:
526 emitVFPArithInstruction(MI);
528 case ARMII::VFPConv1Frm:
529 case ARMII::VFPConv2Frm:
530 case ARMII::VFPConv3Frm:
531 case ARMII::VFPConv4Frm:
532 case ARMII::VFPConv5Frm:
533 emitVFPConversionInstruction(MI);
535 case ARMII::VFPLdStFrm:
536 emitVFPLoadStoreInstruction(MI);
538 case ARMII::VFPLdStMulFrm:
539 emitVFPLoadStoreMultipleInstruction(MI);
542 // NEON instructions.
543 case ARMII::NGetLnFrm:
544 case ARMII::NSetLnFrm:
545 emitNEONLaneInstruction(MI);
548 emitNEONDupInstruction(MI);
550 case ARMII::N1RegModImmFrm:
551 emitNEON1RegModImmInstruction(MI);
553 case ARMII::N2RegFrm:
554 emitNEON2RegInstruction(MI);
556 case ARMII::N3RegFrm:
557 emitNEON3RegInstruction(MI);
560 MCE.processDebugLoc(MI.getDebugLoc(), false);
563 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
564 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
565 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
566 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
568 // Remember the CONSTPOOL_ENTRY address for later relocation.
569 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
571 // Emit constpool island entry. In most cases, the actual values will be
572 // resolved and relocated after code emission.
573 if (MCPE.isMachineConstantPoolEntry()) {
574 ARMConstantPoolValue *ACPV =
575 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
577 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
578 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
580 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
581 const GlobalValue *GV = ACPV->getGV();
583 Reloc::Model RelocM = TM.getRelocationModel();
584 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
586 Subtarget->GVIsIndirectSymbol(GV, RelocM),
589 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
593 const Constant *CV = MCPE.Val.ConstVal;
596 errs() << " ** Constant pool #" << CPI << " @ "
597 << (void*)MCE.getCurrentPCValue() << " ";
598 if (const Function *F = dyn_cast<Function>(CV))
599 errs() << F->getName();
605 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
606 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
608 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
609 uint32_t Val = uint32_t(*CI->getValue().getRawData());
611 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
612 if (CFP->getType()->isFloatTy())
613 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
614 else if (CFP->getType()->isDoubleTy())
615 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
617 llvm_unreachable("Unable to handle this constantpool entry!");
620 llvm_unreachable("Unable to handle this constantpool entry!");
625 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
626 const MachineOperand &MO0 = MI.getOperand(0);
627 const MachineOperand &MO1 = MI.getOperand(1);
629 // Emit the 'movw' instruction.
630 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
632 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
634 // Set the conditional execution predicate.
635 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
638 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
640 // Encode imm16 as imm4:imm12
641 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
642 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
645 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
646 // Emit the 'movt' instruction.
647 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
649 // Set the conditional execution predicate.
650 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
653 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
655 // Encode imm16 as imm4:imm1, same as movw above.
656 Binary |= Hi16 & 0xFFF;
657 Binary |= ((Hi16 >> 12) & 0xF) << 16;
661 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
662 const MachineOperand &MO0 = MI.getOperand(0);
663 const MachineOperand &MO1 = MI.getOperand(1);
664 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
665 "Not a valid so_imm value!");
666 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
667 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
669 // Emit the 'mov' instruction.
670 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
672 // Set the conditional execution predicate.
673 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
676 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
679 // Set bit I(25) to identify this is the immediate form of <shifter_op>
680 Binary |= 1 << ARMII::I_BitShift;
681 Binary |= getMachineSoImmOpValue(V1);
684 // Now the 'orr' instruction.
685 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
687 // Set the conditional execution predicate.
688 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
691 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
694 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
697 // Set bit I(25) to identify this is the immediate form of <shifter_op>
698 Binary |= 1 << ARMII::I_BitShift;
699 Binary |= getMachineSoImmOpValue(V2);
703 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
704 // It's basically add r, pc, (LJTI - $+8)
706 const TargetInstrDesc &TID = MI.getDesc();
708 // Emit the 'add' instruction.
709 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
711 // Set the conditional execution predicate
712 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
714 // Encode S bit if MI modifies CPSR.
715 Binary |= getAddrModeSBit(MI, TID);
718 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
720 // Encode Rn which is PC.
721 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
723 // Encode the displacement.
724 Binary |= 1 << ARMII::I_BitShift;
725 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
730 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
731 unsigned Opcode = MI.getDesc().Opcode;
733 // Part of binary is determined by TableGn.
734 unsigned Binary = getBinaryCodeForInstr(MI);
736 // Set the conditional execution predicate
737 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
739 // Encode S bit if MI modifies CPSR.
740 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
741 Binary |= 1 << ARMII::S_BitShift;
743 // Encode register def if there is one.
744 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
746 // Encode the shift operation.
753 case ARM::MOVsrl_flag:
755 Binary |= (0x2 << 4) | (1 << 7);
757 case ARM::MOVsra_flag:
759 Binary |= (0x4 << 4) | (1 << 7);
763 // Encode register Rm.
764 Binary |= getMachineOpValue(MI, 1);
769 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
770 DEBUG(errs() << " ** LPC" << LabelID << " @ "
771 << (void*)MCE.getCurrentPCValue() << '\n');
772 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
775 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
776 unsigned Opcode = MI.getDesc().Opcode;
779 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
783 case ARM::BMOVPCRXr9: {
784 // First emit mov lr, pc
785 unsigned Binary = 0x01a0e00f;
786 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
789 // and then emit the branch.
790 emitMiscBranchInstruction(MI);
793 case TargetOpcode::INLINEASM: {
794 // We allow inline assembler nodes with empty bodies - they can
795 // implicitly define registers, which is ok for JIT.
796 if (MI.getOperand(0).getSymbolName()[0]) {
797 report_fatal_error("JIT does not support inline asm!");
801 case TargetOpcode::PROLOG_LABEL:
802 case TargetOpcode::EH_LABEL:
803 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
805 case TargetOpcode::IMPLICIT_DEF:
806 case TargetOpcode::KILL:
809 case ARM::CONSTPOOL_ENTRY:
810 emitConstPoolInstruction(MI);
813 // Remember of the address of the PC label for relocation later.
814 addPCLabel(MI.getOperand(2).getImm());
815 // PICADD is just an add instruction that implicitly read pc.
816 emitDataProcessingInstruction(MI, 0, ARM::PC);
823 // Remember of the address of the PC label for relocation later.
824 addPCLabel(MI.getOperand(2).getImm());
825 // These are just load / store instructions that implicitly read pc.
826 emitLoadStoreInstruction(MI, 0, ARM::PC);
833 // Remember of the address of the PC label for relocation later.
834 addPCLabel(MI.getOperand(2).getImm());
835 // These are just load / store instructions that implicitly read pc.
836 emitMiscLoadStoreInstruction(MI, ARM::PC);
841 // Two instructions to materialize a constant.
842 if (Subtarget->hasV6T2Ops())
843 emitMOVi32immInstruction(MI);
845 emitMOVi2piecesInstruction(MI);
848 case ARM::LEApcrelJT:
849 // Materialize jumptable address.
850 emitLEApcrelJTInstruction(MI);
853 case ARM::MOVsrl_flag:
854 case ARM::MOVsra_flag:
855 emitPseudoMoveInstruction(MI);
860 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
861 const TargetInstrDesc &TID,
862 const MachineOperand &MO,
864 unsigned Binary = getMachineOpValue(MI, MO);
866 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
867 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
868 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
870 // Encode the shift opcode.
872 unsigned Rs = MO1.getReg();
874 // Set shift operand (bit[7:4]).
879 // RRX - 0110 and bit[11:8] clear.
881 default: llvm_unreachable("Unknown shift opc!");
882 case ARM_AM::lsl: SBits = 0x1; break;
883 case ARM_AM::lsr: SBits = 0x3; break;
884 case ARM_AM::asr: SBits = 0x5; break;
885 case ARM_AM::ror: SBits = 0x7; break;
886 case ARM_AM::rrx: SBits = 0x6; break;
889 // Set shift operand (bit[6:4]).
895 default: llvm_unreachable("Unknown shift opc!");
896 case ARM_AM::lsl: SBits = 0x0; break;
897 case ARM_AM::lsr: SBits = 0x2; break;
898 case ARM_AM::asr: SBits = 0x4; break;
899 case ARM_AM::ror: SBits = 0x6; break;
902 Binary |= SBits << 4;
903 if (SOpc == ARM_AM::rrx)
906 // Encode the shift operation Rs or shift_imm (except rrx).
908 // Encode Rs bit[11:8].
909 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
910 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
913 // Encode shift_imm bit[11:7].
914 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
917 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
918 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
919 assert(SoImmVal != -1 && "Not a valid so_imm value!");
921 // Encode rotate_imm.
922 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
923 << ARMII::SoRotImmShift;
926 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
930 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
931 const TargetInstrDesc &TID) const {
932 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
933 const MachineOperand &MO = MI.getOperand(i-1);
934 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
935 return 1 << ARMII::S_BitShift;
940 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
942 unsigned ImplicitRn) {
943 const TargetInstrDesc &TID = MI.getDesc();
945 // Part of binary is determined by TableGn.
946 unsigned Binary = getBinaryCodeForInstr(MI);
948 // Set the conditional execution predicate
949 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
951 // Encode S bit if MI modifies CPSR.
952 Binary |= getAddrModeSBit(MI, TID);
954 // Encode register def if there is one.
955 unsigned NumDefs = TID.getNumDefs();
958 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
960 // Special handling for implicit use (e.g. PC).
961 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
963 if (TID.Opcode == ARM::MOVi16) {
964 // Get immediate from MI.
965 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
966 ARM::reloc_arm_movw);
967 // Encode imm which is the same as in emitMOVi32immInstruction().
968 Binary |= Lo16 & 0xFFF;
969 Binary |= ((Lo16 >> 12) & 0xF) << 16;
972 } else if(TID.Opcode == ARM::MOVTi16) {
973 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
974 ARM::reloc_arm_movt) >> 16);
975 Binary |= Hi16 & 0xFFF;
976 Binary |= ((Hi16 >> 12) & 0xF) << 16;
979 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
980 uint32_t v = ~MI.getOperand(2).getImm();
981 int32_t lsb = CountTrailingZeros_32(v);
982 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
983 // Instr{20-16} = msb, Instr{11-7} = lsb
984 Binary |= (msb & 0x1F) << 16;
985 Binary |= (lsb & 0x1F) << 7;
988 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
989 // Encode Rn in Instr{0-3}
990 Binary |= getMachineOpValue(MI, OpIdx++);
992 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
993 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
995 // Instr{20-16} = widthm1, Instr{11-7} = lsb
996 Binary |= (widthm1 & 0x1F) << 16;
997 Binary |= (lsb & 0x1F) << 7;
1002 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1003 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1006 // Encode first non-shifter register operand if there is one.
1007 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1010 // Special handling for implicit use (e.g. PC).
1011 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1013 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1018 // Encode shifter operand.
1019 const MachineOperand &MO = MI.getOperand(OpIdx);
1020 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1022 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1027 // Encode register Rm.
1028 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1033 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1038 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1039 unsigned ImplicitRd,
1040 unsigned ImplicitRn) {
1041 const TargetInstrDesc &TID = MI.getDesc();
1042 unsigned Form = TID.TSFlags & ARMII::FormMask;
1043 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1045 // Part of binary is determined by TableGn.
1046 unsigned Binary = getBinaryCodeForInstr(MI);
1048 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1049 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1050 MI.getOpcode() == ARM::STRi12) {
1055 // Set the conditional execution predicate
1056 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1060 // Operand 0 of a pre- and post-indexed store is the address base
1061 // writeback. Skip it.
1062 bool Skipped = false;
1063 if (IsPrePost && Form == ARMII::StFrm) {
1068 // Set first operand
1070 // Special handling for implicit use (e.g. PC).
1071 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1073 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1075 // Set second operand
1077 // Special handling for implicit use (e.g. PC).
1078 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1080 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1082 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1083 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1086 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1087 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1088 ? 0 : MI.getOperand(OpIdx+1).getImm();
1090 // Set bit U(23) according to sign of immed value (positive or negative).
1091 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1093 if (!MO2.getReg()) { // is immediate
1094 if (ARM_AM::getAM2Offset(AM2Opc))
1095 // Set the value of offset_12 field
1096 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1101 // Set bit I(25), because this is not in immediate encoding.
1102 Binary |= 1 << ARMII::I_BitShift;
1103 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1104 // Set bit[3:0] to the corresponding Rm register
1105 Binary |= getARMRegisterNumbering(MO2.getReg());
1107 // If this instr is in scaled register offset/index instruction, set
1108 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1109 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1110 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1111 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1117 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1118 unsigned ImplicitRn) {
1119 const TargetInstrDesc &TID = MI.getDesc();
1120 unsigned Form = TID.TSFlags & ARMII::FormMask;
1121 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1123 // Part of binary is determined by TableGn.
1124 unsigned Binary = getBinaryCodeForInstr(MI);
1126 // Set the conditional execution predicate
1127 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1131 // Operand 0 of a pre- and post-indexed store is the address base
1132 // writeback. Skip it.
1133 bool Skipped = false;
1134 if (IsPrePost && Form == ARMII::StMiscFrm) {
1139 // Set first operand
1140 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1142 // Skip LDRD and STRD's second operand.
1143 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1146 // Set second operand
1148 // Special handling for implicit use (e.g. PC).
1149 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1151 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1153 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1154 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1157 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1158 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1159 ? 0 : MI.getOperand(OpIdx+1).getImm();
1161 // Set bit U(23) according to sign of immed value (positive or negative)
1162 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1165 // If this instr is in register offset/index encoding, set bit[3:0]
1166 // to the corresponding Rm register.
1168 Binary |= getARMRegisterNumbering(MO2.getReg());
1173 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1174 Binary |= 1 << ARMII::AM3_I_BitShift;
1175 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1177 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1178 Binary |= (ImmOffs & 0xF); // immedL
1184 static unsigned getAddrModeUPBits(unsigned Mode) {
1185 unsigned Binary = 0;
1187 // Set addressing mode by modifying bits U(23) and P(24)
1188 // IA - Increment after - bit U = 1 and bit P = 0
1189 // IB - Increment before - bit U = 1 and bit P = 1
1190 // DA - Decrement after - bit U = 0 and bit P = 0
1191 // DB - Decrement before - bit U = 0 and bit P = 1
1193 default: llvm_unreachable("Unknown addressing sub-mode!");
1194 case ARM_AM::da: break;
1195 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1196 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1197 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1203 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1204 const TargetInstrDesc &TID = MI.getDesc();
1205 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1207 // Part of binary is determined by TableGn.
1208 unsigned Binary = getBinaryCodeForInstr(MI);
1210 // Set the conditional execution predicate
1211 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1213 // Skip operand 0 of an instruction with base register update.
1218 // Set base address operand
1219 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1221 // Set addressing mode by modifying bits U(23) and P(24)
1222 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1223 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1227 Binary |= 0x1 << ARMII::W_BitShift;
1230 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1231 const MachineOperand &MO = MI.getOperand(i);
1232 if (!MO.isReg() || MO.isImplicit())
1234 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1235 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1237 Binary |= 0x1 << RegNum;
1243 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1244 const TargetInstrDesc &TID = MI.getDesc();
1246 // Part of binary is determined by TableGn.
1247 unsigned Binary = getBinaryCodeForInstr(MI);
1249 // Set the conditional execution predicate
1250 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1252 // Encode S bit if MI modifies CPSR.
1253 Binary |= getAddrModeSBit(MI, TID);
1255 // 32x32->64bit operations have two destination registers. The number
1256 // of register definitions will tell us if that's what we're dealing with.
1258 if (TID.getNumDefs() == 2)
1259 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1262 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1265 Binary |= getMachineOpValue(MI, OpIdx++);
1268 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1270 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1271 // it as Rn (for multiply, that's in the same offset as RdLo.
1272 if (TID.getNumOperands() > OpIdx &&
1273 !TID.OpInfo[OpIdx].isPredicate() &&
1274 !TID.OpInfo[OpIdx].isOptionalDef())
1275 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1280 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1281 const TargetInstrDesc &TID = MI.getDesc();
1283 // Part of binary is determined by TableGn.
1284 unsigned Binary = getBinaryCodeForInstr(MI);
1286 // Set the conditional execution predicate
1287 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1292 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1294 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1295 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1297 // Two register operand form.
1299 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1302 Binary |= getMachineOpValue(MI, MO2);
1305 Binary |= getMachineOpValue(MI, MO1);
1308 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1309 if (MI.getOperand(OpIdx).isImm() &&
1310 !TID.OpInfo[OpIdx].isPredicate() &&
1311 !TID.OpInfo[OpIdx].isOptionalDef())
1312 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1317 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1318 const TargetInstrDesc &TID = MI.getDesc();
1320 // Part of binary is determined by TableGn.
1321 unsigned Binary = getBinaryCodeForInstr(MI);
1323 // Set the conditional execution predicate
1324 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1329 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1331 const MachineOperand &MO = MI.getOperand(OpIdx++);
1332 if (OpIdx == TID.getNumOperands() ||
1333 TID.OpInfo[OpIdx].isPredicate() ||
1334 TID.OpInfo[OpIdx].isOptionalDef()) {
1335 // Encode Rm and it's done.
1336 Binary |= getMachineOpValue(MI, MO);
1342 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1345 Binary |= getMachineOpValue(MI, OpIdx++);
1347 // Encode shift_imm.
1348 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1349 if (TID.Opcode == ARM::PKHTB) {
1350 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1354 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1355 Binary |= ShiftAmt << ARMII::ShiftShift;
1360 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1361 const TargetInstrDesc &TID = MI.getDesc();
1363 // Part of binary is determined by TableGen.
1364 unsigned Binary = getBinaryCodeForInstr(MI);
1366 // Set the conditional execution predicate
1367 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1370 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1372 // Encode saturate bit position.
1373 unsigned Pos = MI.getOperand(1).getImm();
1374 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1376 assert((Pos < 16 || (Pos < 32 &&
1377 TID.Opcode != ARM::SSAT16 &&
1378 TID.Opcode != ARM::USAT16)) &&
1379 "saturate bit position out of range");
1380 Binary |= Pos << 16;
1383 Binary |= getMachineOpValue(MI, 2);
1385 // Encode shift_imm.
1386 if (TID.getNumOperands() == 4) {
1387 unsigned ShiftOp = MI.getOperand(3).getImm();
1388 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1389 if (Opc == ARM_AM::asr)
1391 unsigned ShiftAmt = MI.getOperand(3).getImm();
1392 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1394 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1395 Binary |= ShiftAmt << ARMII::ShiftShift;
1401 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1402 const TargetInstrDesc &TID = MI.getDesc();
1404 if (TID.Opcode == ARM::TPsoft) {
1405 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1408 // Part of binary is determined by TableGn.
1409 unsigned Binary = getBinaryCodeForInstr(MI);
1411 // Set the conditional execution predicate
1412 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1414 // Set signed_immed_24 field
1415 Binary |= getMachineOpValue(MI, 0);
1420 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1421 // Remember the base address of the inline jump table.
1422 uintptr_t JTBase = MCE.getCurrentPCValue();
1423 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1424 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1427 // Now emit the jump table entries.
1428 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1429 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1431 // DestBB address - JT base.
1432 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1434 // Absolute DestBB address.
1435 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1440 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1441 const TargetInstrDesc &TID = MI.getDesc();
1443 // Handle jump tables.
1444 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1445 // First emit a ldr pc, [] instruction.
1446 emitDataProcessingInstruction(MI, ARM::PC);
1448 // Then emit the inline jump table.
1450 (TID.Opcode == ARM::BR_JTr)
1451 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1452 emitInlineJumpTable(JTIndex);
1454 } else if (TID.Opcode == ARM::BR_JTm) {
1455 // First emit a ldr pc, [] instruction.
1456 emitLoadStoreInstruction(MI, ARM::PC);
1458 // Then emit the inline jump table.
1459 emitInlineJumpTable(MI.getOperand(3).getIndex());
1463 // Part of binary is determined by TableGn.
1464 unsigned Binary = getBinaryCodeForInstr(MI);
1466 // Set the conditional execution predicate
1467 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1469 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1470 // The return register is LR.
1471 Binary |= getARMRegisterNumbering(ARM::LR);
1473 // otherwise, set the return register
1474 Binary |= getMachineOpValue(MI, 0);
1479 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1480 unsigned RegD = MI.getOperand(OpIdx).getReg();
1481 unsigned Binary = 0;
1482 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1483 RegD = getARMRegisterNumbering(RegD);
1485 Binary |= RegD << ARMII::RegRdShift;
1487 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1488 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1493 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1494 unsigned RegN = MI.getOperand(OpIdx).getReg();
1495 unsigned Binary = 0;
1496 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1497 RegN = getARMRegisterNumbering(RegN);
1499 Binary |= RegN << ARMII::RegRnShift;
1501 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1502 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1507 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1508 unsigned RegM = MI.getOperand(OpIdx).getReg();
1509 unsigned Binary = 0;
1510 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1511 RegM = getARMRegisterNumbering(RegM);
1515 Binary |= ((RegM & 0x1E) >> 1);
1516 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1521 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1522 const TargetInstrDesc &TID = MI.getDesc();
1524 // Part of binary is determined by TableGn.
1525 unsigned Binary = getBinaryCodeForInstr(MI);
1527 // Set the conditional execution predicate
1528 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1531 assert((Binary & ARMII::D_BitShift) == 0 &&
1532 (Binary & ARMII::N_BitShift) == 0 &&
1533 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1536 Binary |= encodeVFPRd(MI, OpIdx++);
1538 // If this is a two-address operand, skip it, e.g. FMACD.
1539 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1543 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1544 Binary |= encodeVFPRn(MI, OpIdx++);
1546 if (OpIdx == TID.getNumOperands() ||
1547 TID.OpInfo[OpIdx].isPredicate() ||
1548 TID.OpInfo[OpIdx].isOptionalDef()) {
1549 // FCMPEZD etc. has only one operand.
1555 Binary |= encodeVFPRm(MI, OpIdx);
1560 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1561 const TargetInstrDesc &TID = MI.getDesc();
1562 unsigned Form = TID.TSFlags & ARMII::FormMask;
1564 // Part of binary is determined by TableGn.
1565 unsigned Binary = getBinaryCodeForInstr(MI);
1567 // Set the conditional execution predicate
1568 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1572 case ARMII::VFPConv1Frm:
1573 case ARMII::VFPConv2Frm:
1574 case ARMII::VFPConv3Frm:
1576 Binary |= encodeVFPRd(MI, 0);
1578 case ARMII::VFPConv4Frm:
1580 Binary |= encodeVFPRn(MI, 0);
1582 case ARMII::VFPConv5Frm:
1584 Binary |= encodeVFPRm(MI, 0);
1590 case ARMII::VFPConv1Frm:
1592 Binary |= encodeVFPRm(MI, 1);
1594 case ARMII::VFPConv2Frm:
1595 case ARMII::VFPConv3Frm:
1597 Binary |= encodeVFPRn(MI, 1);
1599 case ARMII::VFPConv4Frm:
1600 case ARMII::VFPConv5Frm:
1602 Binary |= encodeVFPRd(MI, 1);
1606 if (Form == ARMII::VFPConv5Frm)
1608 Binary |= encodeVFPRn(MI, 2);
1609 else if (Form == ARMII::VFPConv3Frm)
1611 Binary |= encodeVFPRm(MI, 2);
1616 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1617 // Part of binary is determined by TableGn.
1618 unsigned Binary = getBinaryCodeForInstr(MI);
1620 // Set the conditional execution predicate
1621 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1626 Binary |= encodeVFPRd(MI, OpIdx++);
1628 // Encode address base.
1629 const MachineOperand &Base = MI.getOperand(OpIdx++);
1630 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1632 // If there is a non-zero immediate offset, encode it.
1634 const MachineOperand &Offset = MI.getOperand(OpIdx);
1635 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1636 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1637 Binary |= 1 << ARMII::U_BitShift;
1644 // If immediate offset is omitted, default to +0.
1645 Binary |= 1 << ARMII::U_BitShift;
1651 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1652 const TargetInstrDesc &TID = MI.getDesc();
1653 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1655 // Part of binary is determined by TableGn.
1656 unsigned Binary = getBinaryCodeForInstr(MI);
1658 // Set the conditional execution predicate
1659 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1661 // Skip operand 0 of an instruction with base register update.
1666 // Set base address operand
1667 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1669 // Set addressing mode by modifying bits U(23) and P(24)
1670 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1671 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1675 Binary |= 0x1 << ARMII::W_BitShift;
1677 // First register is encoded in Dd.
1678 Binary |= encodeVFPRd(MI, OpIdx+2);
1680 // Count the number of registers.
1681 unsigned NumRegs = 1;
1682 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1683 const MachineOperand &MO = MI.getOperand(i);
1684 if (!MO.isReg() || MO.isImplicit())
1688 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1689 // Otherwise, it will be 0, in the case of 32-bit registers.
1691 Binary |= NumRegs * 2;
1698 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1699 unsigned RegD = MI.getOperand(OpIdx).getReg();
1700 unsigned Binary = 0;
1701 RegD = getARMRegisterNumbering(RegD);
1702 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1703 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1707 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1708 unsigned RegN = MI.getOperand(OpIdx).getReg();
1709 unsigned Binary = 0;
1710 RegN = getARMRegisterNumbering(RegN);
1711 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1712 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1716 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1717 unsigned RegM = MI.getOperand(OpIdx).getReg();
1718 unsigned Binary = 0;
1719 RegM = getARMRegisterNumbering(RegM);
1720 Binary |= (RegM & 0xf);
1721 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1725 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1726 /// data-processing instruction to the corresponding Thumb encoding.
1727 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1728 assert((Binary & 0xfe000000) == 0xf2000000 &&
1729 "not an ARM NEON data-processing instruction");
1730 unsigned UBit = (Binary >> 24) & 1;
1731 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1734 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1735 unsigned Binary = getBinaryCodeForInstr(MI);
1737 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1738 const TargetInstrDesc &TID = MI.getDesc();
1739 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1743 } else { // ARMII::NSetLnFrm
1749 // Set the conditional execution predicate
1750 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1752 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1753 RegT = getARMRegisterNumbering(RegT);
1754 Binary |= (RegT << ARMII::RegRdShift);
1755 Binary |= encodeNEONRn(MI, RegNOpIdx);
1758 if ((Binary & (1 << 22)) != 0)
1759 LaneShift = 0; // 8-bit elements
1760 else if ((Binary & (1 << 5)) != 0)
1761 LaneShift = 1; // 16-bit elements
1763 LaneShift = 2; // 32-bit elements
1765 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1766 unsigned Opc1 = Lane >> 2;
1767 unsigned Opc2 = Lane & 3;
1768 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1769 Binary |= (Opc1 << 21);
1770 Binary |= (Opc2 << 5);
1775 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1776 unsigned Binary = getBinaryCodeForInstr(MI);
1778 // Set the conditional execution predicate
1779 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1781 unsigned RegT = MI.getOperand(1).getReg();
1782 RegT = getARMRegisterNumbering(RegT);
1783 Binary |= (RegT << ARMII::RegRdShift);
1784 Binary |= encodeNEONRn(MI, 0);
1788 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1789 unsigned Binary = getBinaryCodeForInstr(MI);
1790 // Destination register is encoded in Dd.
1791 Binary |= encodeNEONRd(MI, 0);
1792 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1793 unsigned Imm = MI.getOperand(1).getImm();
1794 unsigned Op = (Imm >> 12) & 1;
1795 unsigned Cmode = (Imm >> 8) & 0xf;
1796 unsigned I = (Imm >> 7) & 1;
1797 unsigned Imm3 = (Imm >> 4) & 0x7;
1798 unsigned Imm4 = Imm & 0xf;
1799 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1801 Binary = convertNEONDataProcToThumb(Binary);
1805 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1806 const TargetInstrDesc &TID = MI.getDesc();
1807 unsigned Binary = getBinaryCodeForInstr(MI);
1808 // Destination register is encoded in Dd; source register in Dm.
1810 Binary |= encodeNEONRd(MI, OpIdx++);
1811 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1813 Binary |= encodeNEONRm(MI, OpIdx);
1815 Binary = convertNEONDataProcToThumb(Binary);
1816 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1820 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1821 const TargetInstrDesc &TID = MI.getDesc();
1822 unsigned Binary = getBinaryCodeForInstr(MI);
1823 // Destination register is encoded in Dd; source registers in Dn and Dm.
1825 Binary |= encodeNEONRd(MI, OpIdx++);
1826 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1828 Binary |= encodeNEONRn(MI, OpIdx++);
1829 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1831 Binary |= encodeNEONRm(MI, OpIdx);
1833 Binary = convertNEONDataProcToThumb(Binary);
1834 // FIXME: This does not handle VMOVDneon or VMOVQ.
1838 #include "ARMGenCodeEmitter.inc"