1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class Emitter : public MachineFunctionPass, public ARMCodeEmitter {
60 const ARMInstrInfo *II;
62 const ARMSubtarget *Subtarget;
65 const std::vector<MachineConstantPoolEntry> *MCPEs;
66 const std::vector<MachineJumpTableEntry> *MJTEs;
69 void getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addRequired<MachineModuleInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
76 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
77 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
78 MCE(mce), MCPEs(0), MJTEs(0),
79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
80 Emitter(TargetMachine &tm, CodeEmitter &mce,
81 const ARMInstrInfo &ii, const TargetData &td)
82 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
83 MCE(mce), MCPEs(0), MJTEs(0),
84 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
86 bool runOnMachineFunction(MachineFunction &MF);
88 virtual const char *getPassName() const {
89 return "ARM Machine Code Emitter";
92 void emitInstruction(const MachineInstr &MI);
96 void emitWordLE(unsigned Binary);
98 void emitDWordLE(uint64_t Binary);
100 void emitConstPoolInstruction(const MachineInstr &MI);
102 void emitMOVi2piecesInstruction(const MachineInstr &MI);
104 void emitLEApcrelJTInstruction(const MachineInstr &MI);
106 void emitPseudoMoveInstruction(const MachineInstr &MI);
108 void addPCLabel(unsigned LabelID);
110 void emitPseudoInstruction(const MachineInstr &MI);
112 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
113 const TargetInstrDesc &TID,
114 const MachineOperand &MO,
117 unsigned getMachineSoImmOpValue(unsigned SoImm);
119 unsigned getAddrModeSBit(const MachineInstr &MI,
120 const TargetInstrDesc &TID) const;
122 void emitDataProcessingInstruction(const MachineInstr &MI,
123 unsigned ImplicitRd = 0,
124 unsigned ImplicitRn = 0);
126 void emitLoadStoreInstruction(const MachineInstr &MI,
127 unsigned ImplicitRd = 0,
128 unsigned ImplicitRn = 0);
130 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
131 unsigned ImplicitRn = 0);
133 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
135 void emitMulFrmInstruction(const MachineInstr &MI);
137 void emitExtendInstruction(const MachineInstr &MI);
139 void emitMiscArithInstruction(const MachineInstr &MI);
141 void emitBranchInstruction(const MachineInstr &MI);
143 void emitInlineJumpTable(unsigned JTIndex);
145 void emitMiscBranchInstruction(const MachineInstr &MI);
147 void emitVFPArithInstruction(const MachineInstr &MI);
149 void emitVFPConversionInstruction(const MachineInstr &MI);
151 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
153 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
155 void emitMiscInstruction(const MachineInstr &MI);
157 /// getMachineOpValue - Return binary encoding of operand. If the machine
158 /// operand requires relocation, record the relocation and return zero.
159 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
160 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
161 return getMachineOpValue(MI, MI.getOperand(OpIdx));
164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166 unsigned getShiftOp(unsigned Imm) const ;
168 /// Routines that handle operands which add machine relocations which are
169 /// fixed up by the relocation stage.
170 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
171 bool MayNeedFarStub, bool Indirect,
173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177 intptr_t JTBase = 0);
179 template <class CodeEmitter>
180 char Emitter<CodeEmitter>::ID = 0;
183 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
184 /// to the specified MCE object.
186 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
187 MachineCodeEmitter &MCE) {
188 return new Emitter<MachineCodeEmitter>(TM, MCE);
190 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
191 JITCodeEmitter &JCE) {
192 return new Emitter<JITCodeEmitter>(TM, JCE);
194 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
195 ObjectCodeEmitter &OCE) {
196 return new Emitter<ObjectCodeEmitter>(TM, OCE);
199 template<class CodeEmitter>
200 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
201 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
202 MF.getTarget().getRelocationModel() != Reloc::Static) &&
203 "JIT relocation model must be set to static or default!");
204 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
205 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
206 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
207 Subtarget = &TM.getSubtarget<ARMSubtarget>();
208 MCPEs = &MF.getConstantPool()->getConstants();
209 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
210 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
211 JTI->Initialize(MF, IsPIC);
212 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
215 DEBUG(errs() << "JITTing function '"
216 << MF.getFunction()->getName() << "'\n");
217 MCE.startFunction(MF);
218 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
220 MCE.StartMachineBasicBlock(MBB);
221 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
225 } while (MCE.finishFunction(MF));
230 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
232 template<class CodeEmitter>
233 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
234 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
235 default: llvm_unreachable("Unknown shift opc!");
236 case ARM_AM::asr: return 2;
237 case ARM_AM::lsl: return 0;
238 case ARM_AM::lsr: return 1;
240 case ARM_AM::rrx: return 3;
245 /// getMachineOpValue - Return binary encoding of operand. If the machine
246 /// operand requires relocation, record the relocation and return zero.
247 template<class CodeEmitter>
248 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
249 const MachineOperand &MO) {
251 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
253 return static_cast<unsigned>(MO.getImm());
254 else if (MO.isGlobal())
255 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
256 else if (MO.isSymbol())
257 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
258 else if (MO.isCPI()) {
259 const TargetInstrDesc &TID = MI.getDesc();
260 // For VFP load, the immediate offset is multiplied by 4.
261 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
262 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
263 emitConstPoolAddress(MO.getIndex(), Reloc);
264 } else if (MO.isJTI())
265 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
267 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
277 /// emitGlobalAddress - Emit the specified address to the code stream.
279 template<class CodeEmitter>
280 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
281 bool MayNeedFarStub, bool Indirect,
283 MachineRelocation MR = Indirect
284 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
285 GV, ACPV, MayNeedFarStub)
286 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
287 GV, ACPV, MayNeedFarStub);
288 MCE.addRelocation(MR);
291 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
292 /// be emitted to the current location in the function, and allow it to be PC
294 template<class CodeEmitter>
295 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
297 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
301 /// emitConstPoolAddress - Arrange for the address of an constant pool
302 /// to be emitted to the current location in the function, and allow it to be PC
304 template<class CodeEmitter>
305 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
307 // Tell JIT emitter we'll resolve the address.
308 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
309 Reloc, CPI, 0, true));
312 /// emitJumpTableAddress - Arrange for the address of a jump table to
313 /// be emitted to the current location in the function, and allow it to be PC
315 template<class CodeEmitter>
316 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
318 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
319 Reloc, JTIndex, 0, true));
322 /// emitMachineBasicBlock - Emit the specified address basic block.
323 template<class CodeEmitter>
324 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
325 unsigned Reloc, intptr_t JTBase) {
326 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
330 template<class CodeEmitter>
331 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
332 DEBUG(errs() << " 0x";
333 errs().write_hex(Binary) << "\n");
334 MCE.emitWordLE(Binary);
337 template<class CodeEmitter>
338 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
339 DEBUG(errs() << " 0x";
340 errs().write_hex(Binary) << "\n");
341 MCE.emitDWordLE(Binary);
344 template<class CodeEmitter>
345 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
346 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
348 MCE.processDebugLoc(MI.getDebugLoc(), true);
350 NumEmitted++; // Keep track of the # of mi's emitted
351 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
353 llvm_unreachable("Unhandled instruction encoding format!");
357 emitPseudoInstruction(MI);
360 case ARMII::DPSoRegFrm:
361 emitDataProcessingInstruction(MI);
365 emitLoadStoreInstruction(MI);
367 case ARMII::LdMiscFrm:
368 case ARMII::StMiscFrm:
369 emitMiscLoadStoreInstruction(MI);
371 case ARMII::LdStMulFrm:
372 emitLoadStoreMultipleInstruction(MI);
375 emitMulFrmInstruction(MI);
378 emitExtendInstruction(MI);
380 case ARMII::ArithMiscFrm:
381 emitMiscArithInstruction(MI);
384 emitBranchInstruction(MI);
386 case ARMII::BrMiscFrm:
387 emitMiscBranchInstruction(MI);
390 case ARMII::VFPUnaryFrm:
391 case ARMII::VFPBinaryFrm:
392 emitVFPArithInstruction(MI);
394 case ARMII::VFPConv1Frm:
395 case ARMII::VFPConv2Frm:
396 case ARMII::VFPConv3Frm:
397 case ARMII::VFPConv4Frm:
398 case ARMII::VFPConv5Frm:
399 emitVFPConversionInstruction(MI);
401 case ARMII::VFPLdStFrm:
402 emitVFPLoadStoreInstruction(MI);
404 case ARMII::VFPLdStMulFrm:
405 emitVFPLoadStoreMultipleInstruction(MI);
407 case ARMII::VFPMiscFrm:
408 emitMiscInstruction(MI);
411 MCE.processDebugLoc(MI.getDebugLoc(), false);
414 template<class CodeEmitter>
415 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
416 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
417 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
418 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
420 // Remember the CONSTPOOL_ENTRY address for later relocation.
421 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
423 // Emit constpool island entry. In most cases, the actual values will be
424 // resolved and relocated after code emission.
425 if (MCPE.isMachineConstantPoolEntry()) {
426 ARMConstantPoolValue *ACPV =
427 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
429 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
430 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
432 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
433 GlobalValue *GV = ACPV->getGV();
435 Reloc::Model RelocM = TM.getRelocationModel();
436 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
438 Subtarget->GVIsIndirectSymbol(GV, RelocM),
441 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
445 Constant *CV = MCPE.Val.ConstVal;
448 errs() << " ** Constant pool #" << CPI << " @ "
449 << (void*)MCE.getCurrentPCValue() << " ";
450 if (const Function *F = dyn_cast<Function>(CV))
451 errs() << F->getName();
457 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
458 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
460 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
461 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
463 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
464 if (CFP->getType()->isFloatTy())
465 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
466 else if (CFP->getType()->isDoubleTy())
467 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
469 llvm_unreachable("Unable to handle this constantpool entry!");
472 llvm_unreachable("Unable to handle this constantpool entry!");
477 template<class CodeEmitter>
478 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
479 const MachineOperand &MO0 = MI.getOperand(0);
480 const MachineOperand &MO1 = MI.getOperand(1);
481 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
482 "Not a valid so_imm value!");
483 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
484 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
486 // Emit the 'mov' instruction.
487 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
489 // Set the conditional execution predicate.
490 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
493 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
496 // Set bit I(25) to identify this is the immediate form of <shifter_op>
497 Binary |= 1 << ARMII::I_BitShift;
498 Binary |= getMachineSoImmOpValue(V1);
501 // Now the 'orr' instruction.
502 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
504 // Set the conditional execution predicate.
505 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
508 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
511 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
514 // Set bit I(25) to identify this is the immediate form of <shifter_op>
515 Binary |= 1 << ARMII::I_BitShift;
516 Binary |= getMachineSoImmOpValue(V2);
520 template<class CodeEmitter>
521 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
522 // It's basically add r, pc, (LJTI - $+8)
524 const TargetInstrDesc &TID = MI.getDesc();
526 // Emit the 'add' instruction.
527 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
529 // Set the conditional execution predicate
530 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
532 // Encode S bit if MI modifies CPSR.
533 Binary |= getAddrModeSBit(MI, TID);
536 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
538 // Encode Rn which is PC.
539 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
541 // Encode the displacement.
542 Binary |= 1 << ARMII::I_BitShift;
543 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
548 template<class CodeEmitter>
549 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
550 unsigned Opcode = MI.getDesc().Opcode;
552 // Part of binary is determined by TableGn.
553 unsigned Binary = getBinaryCodeForInstr(MI);
555 // Set the conditional execution predicate
556 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
558 // Encode S bit if MI modifies CPSR.
559 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
560 Binary |= 1 << ARMII::S_BitShift;
562 // Encode register def if there is one.
563 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
565 // Encode the shift operation.
572 case ARM::MOVsrl_flag:
574 Binary |= (0x2 << 4) | (1 << 7);
576 case ARM::MOVsra_flag:
578 Binary |= (0x4 << 4) | (1 << 7);
582 // Encode register Rm.
583 Binary |= getMachineOpValue(MI, 1);
588 template<class CodeEmitter>
589 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
590 DEBUG(errs() << " ** LPC" << LabelID << " @ "
591 << (void*)MCE.getCurrentPCValue() << '\n');
592 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
595 template<class CodeEmitter>
596 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
597 unsigned Opcode = MI.getDesc().Opcode;
600 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
601 // FIXME: Add support for MOVimm32.
602 case TargetInstrInfo::INLINEASM: {
603 // We allow inline assembler nodes with empty bodies - they can
604 // implicitly define registers, which is ok for JIT.
605 if (MI.getOperand(0).getSymbolName()[0]) {
606 llvm_report_error("JIT does not support inline asm!");
610 case TargetInstrInfo::DBG_LABEL:
611 case TargetInstrInfo::EH_LABEL:
612 MCE.emitLabel(MI.getOperand(0).getImm());
614 case TargetInstrInfo::IMPLICIT_DEF:
615 case TargetInstrInfo::KILL:
619 case ARM::CONSTPOOL_ENTRY:
620 emitConstPoolInstruction(MI);
623 // Remember of the address of the PC label for relocation later.
624 addPCLabel(MI.getOperand(2).getImm());
625 // PICADD is just an add instruction that implicitly read pc.
626 emitDataProcessingInstruction(MI, 0, ARM::PC);
633 // Remember of the address of the PC label for relocation later.
634 addPCLabel(MI.getOperand(2).getImm());
635 // These are just load / store instructions that implicitly read pc.
636 emitLoadStoreInstruction(MI, 0, ARM::PC);
643 // Remember of the address of the PC label for relocation later.
644 addPCLabel(MI.getOperand(2).getImm());
645 // These are just load / store instructions that implicitly read pc.
646 emitMiscLoadStoreInstruction(MI, ARM::PC);
649 case ARM::MOVi2pieces:
650 // Two instructions to materialize a constant.
651 emitMOVi2piecesInstruction(MI);
653 case ARM::LEApcrelJT:
654 // Materialize jumptable address.
655 emitLEApcrelJTInstruction(MI);
658 case ARM::MOVsrl_flag:
659 case ARM::MOVsra_flag:
660 emitPseudoMoveInstruction(MI);
665 template<class CodeEmitter>
666 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
667 const MachineInstr &MI,
668 const TargetInstrDesc &TID,
669 const MachineOperand &MO,
671 unsigned Binary = getMachineOpValue(MI, MO);
673 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
674 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
675 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
677 // Encode the shift opcode.
679 unsigned Rs = MO1.getReg();
681 // Set shift operand (bit[7:4]).
686 // RRX - 0110 and bit[11:8] clear.
688 default: llvm_unreachable("Unknown shift opc!");
689 case ARM_AM::lsl: SBits = 0x1; break;
690 case ARM_AM::lsr: SBits = 0x3; break;
691 case ARM_AM::asr: SBits = 0x5; break;
692 case ARM_AM::ror: SBits = 0x7; break;
693 case ARM_AM::rrx: SBits = 0x6; break;
696 // Set shift operand (bit[6:4]).
702 default: llvm_unreachable("Unknown shift opc!");
703 case ARM_AM::lsl: SBits = 0x0; break;
704 case ARM_AM::lsr: SBits = 0x2; break;
705 case ARM_AM::asr: SBits = 0x4; break;
706 case ARM_AM::ror: SBits = 0x6; break;
709 Binary |= SBits << 4;
710 if (SOpc == ARM_AM::rrx)
713 // Encode the shift operation Rs or shift_imm (except rrx).
715 // Encode Rs bit[11:8].
716 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
718 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
721 // Encode shift_imm bit[11:7].
722 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
725 template<class CodeEmitter>
726 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
727 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
728 assert(SoImmVal != -1 && "Not a valid so_imm value!");
730 // Encode rotate_imm.
731 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
732 << ARMII::SoRotImmShift;
735 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
739 template<class CodeEmitter>
740 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
741 const TargetInstrDesc &TID) const {
742 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
743 const MachineOperand &MO = MI.getOperand(i-1);
744 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
745 return 1 << ARMII::S_BitShift;
750 template<class CodeEmitter>
751 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
752 const MachineInstr &MI,
754 unsigned ImplicitRn) {
755 const TargetInstrDesc &TID = MI.getDesc();
757 if (TID.Opcode == ARM::BFC) {
758 llvm_report_error("ARMv6t2 JIT is not yet supported.");
761 // Part of binary is determined by TableGn.
762 unsigned Binary = getBinaryCodeForInstr(MI);
764 // Set the conditional execution predicate
765 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
767 // Encode S bit if MI modifies CPSR.
768 Binary |= getAddrModeSBit(MI, TID);
770 // Encode register def if there is one.
771 unsigned NumDefs = TID.getNumDefs();
774 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
776 // Special handling for implicit use (e.g. PC).
777 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
778 << ARMII::RegRdShift);
780 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
781 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
784 // Encode first non-shifter register operand if there is one.
785 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
788 // Special handling for implicit use (e.g. PC).
789 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
790 << ARMII::RegRnShift);
792 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
797 // Encode shifter operand.
798 const MachineOperand &MO = MI.getOperand(OpIdx);
799 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
801 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
806 // Encode register Rm.
807 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
812 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
817 template<class CodeEmitter>
818 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
819 const MachineInstr &MI,
821 unsigned ImplicitRn) {
822 const TargetInstrDesc &TID = MI.getDesc();
823 unsigned Form = TID.TSFlags & ARMII::FormMask;
824 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
826 // Part of binary is determined by TableGn.
827 unsigned Binary = getBinaryCodeForInstr(MI);
829 // Set the conditional execution predicate
830 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
834 // Operand 0 of a pre- and post-indexed store is the address base
835 // writeback. Skip it.
836 bool Skipped = false;
837 if (IsPrePost && Form == ARMII::StFrm) {
844 // Special handling for implicit use (e.g. PC).
845 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
846 << ARMII::RegRdShift);
848 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
850 // Set second operand
852 // Special handling for implicit use (e.g. PC).
853 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
854 << ARMII::RegRnShift);
856 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
858 // If this is a two-address operand, skip it. e.g. LDR_PRE.
859 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
862 const MachineOperand &MO2 = MI.getOperand(OpIdx);
863 unsigned AM2Opc = (ImplicitRn == ARM::PC)
864 ? 0 : MI.getOperand(OpIdx+1).getImm();
866 // Set bit U(23) according to sign of immed value (positive or negative).
867 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
869 if (!MO2.getReg()) { // is immediate
870 if (ARM_AM::getAM2Offset(AM2Opc))
871 // Set the value of offset_12 field
872 Binary |= ARM_AM::getAM2Offset(AM2Opc);
877 // Set bit I(25), because this is not in immediate enconding.
878 Binary |= 1 << ARMII::I_BitShift;
879 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
880 // Set bit[3:0] to the corresponding Rm register
881 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
883 // If this instr is in scaled register offset/index instruction, set
884 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
885 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
886 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
887 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
893 template<class CodeEmitter>
894 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
895 unsigned ImplicitRn) {
896 const TargetInstrDesc &TID = MI.getDesc();
897 unsigned Form = TID.TSFlags & ARMII::FormMask;
898 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
900 // Part of binary is determined by TableGn.
901 unsigned Binary = getBinaryCodeForInstr(MI);
903 // Set the conditional execution predicate
904 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
908 // Operand 0 of a pre- and post-indexed store is the address base
909 // writeback. Skip it.
910 bool Skipped = false;
911 if (IsPrePost && Form == ARMII::StMiscFrm) {
917 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
919 // Skip LDRD and STRD's second operand.
920 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
923 // Set second operand
925 // Special handling for implicit use (e.g. PC).
926 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
927 << ARMII::RegRnShift);
929 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
931 // If this is a two-address operand, skip it. e.g. LDRH_POST.
932 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
935 const MachineOperand &MO2 = MI.getOperand(OpIdx);
936 unsigned AM3Opc = (ImplicitRn == ARM::PC)
937 ? 0 : MI.getOperand(OpIdx+1).getImm();
939 // Set bit U(23) according to sign of immed value (positive or negative)
940 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
943 // If this instr is in register offset/index encoding, set bit[3:0]
944 // to the corresponding Rm register.
946 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
951 // This instr is in immediate offset/index encoding, set bit 22 to 1.
952 Binary |= 1 << ARMII::AM3_I_BitShift;
953 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
955 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
956 Binary |= (ImmOffs & 0xF); // immedL
962 static unsigned getAddrModeUPBits(unsigned Mode) {
965 // Set addressing mode by modifying bits U(23) and P(24)
966 // IA - Increment after - bit U = 1 and bit P = 0
967 // IB - Increment before - bit U = 1 and bit P = 1
968 // DA - Decrement after - bit U = 0 and bit P = 0
969 // DB - Decrement before - bit U = 0 and bit P = 1
971 default: llvm_unreachable("Unknown addressing sub-mode!");
972 case ARM_AM::da: break;
973 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
974 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
975 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
981 template<class CodeEmitter>
982 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
983 const MachineInstr &MI) {
984 // Part of binary is determined by TableGn.
985 unsigned Binary = getBinaryCodeForInstr(MI);
987 // Set the conditional execution predicate
988 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
990 // Set base address operand
991 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
993 // Set addressing mode by modifying bits U(23) and P(24)
994 const MachineOperand &MO = MI.getOperand(1);
995 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
998 if (ARM_AM::getAM4WBFlag(MO.getImm()))
999 Binary |= 0x1 << ARMII::W_BitShift;
1002 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1003 const MachineOperand &MO = MI.getOperand(i);
1004 if (!MO.isReg() || MO.isImplicit())
1006 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1007 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1009 Binary |= 0x1 << RegNum;
1015 template<class CodeEmitter>
1016 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1017 const TargetInstrDesc &TID = MI.getDesc();
1019 // Part of binary is determined by TableGn.
1020 unsigned Binary = getBinaryCodeForInstr(MI);
1022 // Set the conditional execution predicate
1023 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1025 // Encode S bit if MI modifies CPSR.
1026 Binary |= getAddrModeSBit(MI, TID);
1028 // 32x32->64bit operations have two destination registers. The number
1029 // of register definitions will tell us if that's what we're dealing with.
1031 if (TID.getNumDefs() == 2)
1032 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1035 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1038 Binary |= getMachineOpValue(MI, OpIdx++);
1041 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1043 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1044 // it as Rn (for multiply, that's in the same offset as RdLo.
1045 if (TID.getNumOperands() > OpIdx &&
1046 !TID.OpInfo[OpIdx].isPredicate() &&
1047 !TID.OpInfo[OpIdx].isOptionalDef())
1048 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1053 template<class CodeEmitter>
1054 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1055 const TargetInstrDesc &TID = MI.getDesc();
1057 // Part of binary is determined by TableGn.
1058 unsigned Binary = getBinaryCodeForInstr(MI);
1060 // Set the conditional execution predicate
1061 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1066 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1068 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1069 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1071 // Two register operand form.
1073 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1076 Binary |= getMachineOpValue(MI, MO2);
1079 Binary |= getMachineOpValue(MI, MO1);
1082 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1083 if (MI.getOperand(OpIdx).isImm() &&
1084 !TID.OpInfo[OpIdx].isPredicate() &&
1085 !TID.OpInfo[OpIdx].isOptionalDef())
1086 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1091 template<class CodeEmitter>
1092 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1093 const TargetInstrDesc &TID = MI.getDesc();
1095 // Part of binary is determined by TableGn.
1096 unsigned Binary = getBinaryCodeForInstr(MI);
1098 // Set the conditional execution predicate
1099 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1104 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1106 const MachineOperand &MO = MI.getOperand(OpIdx++);
1107 if (OpIdx == TID.getNumOperands() ||
1108 TID.OpInfo[OpIdx].isPredicate() ||
1109 TID.OpInfo[OpIdx].isOptionalDef()) {
1110 // Encode Rm and it's done.
1111 Binary |= getMachineOpValue(MI, MO);
1117 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1120 Binary |= getMachineOpValue(MI, OpIdx++);
1122 // Encode shift_imm.
1123 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1124 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1125 Binary |= ShiftAmt << ARMII::ShiftShift;
1130 template<class CodeEmitter>
1131 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1132 const TargetInstrDesc &TID = MI.getDesc();
1134 if (TID.Opcode == ARM::TPsoft) {
1135 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1138 // Part of binary is determined by TableGn.
1139 unsigned Binary = getBinaryCodeForInstr(MI);
1141 // Set the conditional execution predicate
1142 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1144 // Set signed_immed_24 field
1145 Binary |= getMachineOpValue(MI, 0);
1150 template<class CodeEmitter>
1151 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1152 // Remember the base address of the inline jump table.
1153 uintptr_t JTBase = MCE.getCurrentPCValue();
1154 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1155 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1158 // Now emit the jump table entries.
1159 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1160 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1162 // DestBB address - JT base.
1163 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1165 // Absolute DestBB address.
1166 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1171 template<class CodeEmitter>
1172 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1173 const TargetInstrDesc &TID = MI.getDesc();
1175 // Handle jump tables.
1176 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1177 // First emit a ldr pc, [] instruction.
1178 emitDataProcessingInstruction(MI, ARM::PC);
1180 // Then emit the inline jump table.
1182 (TID.Opcode == ARM::BR_JTr)
1183 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1184 emitInlineJumpTable(JTIndex);
1186 } else if (TID.Opcode == ARM::BR_JTm) {
1187 // First emit a ldr pc, [] instruction.
1188 emitLoadStoreInstruction(MI, ARM::PC);
1190 // Then emit the inline jump table.
1191 emitInlineJumpTable(MI.getOperand(3).getIndex());
1195 // Part of binary is determined by TableGn.
1196 unsigned Binary = getBinaryCodeForInstr(MI);
1198 // Set the conditional execution predicate
1199 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1201 if (TID.Opcode == ARM::BX_RET)
1202 // The return register is LR.
1203 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1205 // otherwise, set the return register
1206 Binary |= getMachineOpValue(MI, 0);
1211 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1212 unsigned RegD = MI.getOperand(OpIdx).getReg();
1213 unsigned Binary = 0;
1214 bool isSPVFP = false;
1215 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1217 Binary |= RegD << ARMII::RegRdShift;
1219 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1220 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1225 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1226 unsigned RegN = MI.getOperand(OpIdx).getReg();
1227 unsigned Binary = 0;
1228 bool isSPVFP = false;
1229 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1231 Binary |= RegN << ARMII::RegRnShift;
1233 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1234 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1239 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1240 unsigned RegM = MI.getOperand(OpIdx).getReg();
1241 unsigned Binary = 0;
1242 bool isSPVFP = false;
1243 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1247 Binary |= ((RegM & 0x1E) >> 1);
1248 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1253 template<class CodeEmitter>
1254 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1255 const TargetInstrDesc &TID = MI.getDesc();
1257 // Part of binary is determined by TableGn.
1258 unsigned Binary = getBinaryCodeForInstr(MI);
1260 // Set the conditional execution predicate
1261 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1264 assert((Binary & ARMII::D_BitShift) == 0 &&
1265 (Binary & ARMII::N_BitShift) == 0 &&
1266 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1269 Binary |= encodeVFPRd(MI, OpIdx++);
1271 // If this is a two-address operand, skip it, e.g. FMACD.
1272 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1276 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1277 Binary |= encodeVFPRn(MI, OpIdx++);
1279 if (OpIdx == TID.getNumOperands() ||
1280 TID.OpInfo[OpIdx].isPredicate() ||
1281 TID.OpInfo[OpIdx].isOptionalDef()) {
1282 // FCMPEZD etc. has only one operand.
1288 Binary |= encodeVFPRm(MI, OpIdx);
1293 template<class CodeEmitter>
1294 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1295 const MachineInstr &MI) {
1296 const TargetInstrDesc &TID = MI.getDesc();
1297 unsigned Form = TID.TSFlags & ARMII::FormMask;
1299 // Part of binary is determined by TableGn.
1300 unsigned Binary = getBinaryCodeForInstr(MI);
1302 // Set the conditional execution predicate
1303 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1307 case ARMII::VFPConv1Frm:
1308 case ARMII::VFPConv2Frm:
1309 case ARMII::VFPConv3Frm:
1311 Binary |= encodeVFPRd(MI, 0);
1313 case ARMII::VFPConv4Frm:
1315 Binary |= encodeVFPRn(MI, 0);
1317 case ARMII::VFPConv5Frm:
1319 Binary |= encodeVFPRm(MI, 0);
1325 case ARMII::VFPConv1Frm:
1327 Binary |= encodeVFPRm(MI, 1);
1329 case ARMII::VFPConv2Frm:
1330 case ARMII::VFPConv3Frm:
1332 Binary |= encodeVFPRn(MI, 1);
1334 case ARMII::VFPConv4Frm:
1335 case ARMII::VFPConv5Frm:
1337 Binary |= encodeVFPRd(MI, 1);
1341 if (Form == ARMII::VFPConv5Frm)
1343 Binary |= encodeVFPRn(MI, 2);
1344 else if (Form == ARMII::VFPConv3Frm)
1346 Binary |= encodeVFPRm(MI, 2);
1351 template<class CodeEmitter>
1352 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1353 // Part of binary is determined by TableGn.
1354 unsigned Binary = getBinaryCodeForInstr(MI);
1356 // Set the conditional execution predicate
1357 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1362 Binary |= encodeVFPRd(MI, OpIdx++);
1364 // Encode address base.
1365 const MachineOperand &Base = MI.getOperand(OpIdx++);
1366 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1368 // If there is a non-zero immediate offset, encode it.
1370 const MachineOperand &Offset = MI.getOperand(OpIdx);
1371 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1372 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1373 Binary |= 1 << ARMII::U_BitShift;
1380 // If immediate offset is omitted, default to +0.
1381 Binary |= 1 << ARMII::U_BitShift;
1386 template<class CodeEmitter>
1387 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1388 const MachineInstr &MI) {
1389 // Part of binary is determined by TableGn.
1390 unsigned Binary = getBinaryCodeForInstr(MI);
1392 // Set the conditional execution predicate
1393 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1395 // Set base address operand
1396 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1398 // Set addressing mode by modifying bits U(23) and P(24)
1399 const MachineOperand &MO = MI.getOperand(1);
1400 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1403 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1404 Binary |= 0x1 << ARMII::W_BitShift;
1406 // First register is encoded in Dd.
1407 Binary |= encodeVFPRd(MI, 5);
1409 // Number of registers are encoded in offset field.
1410 unsigned NumRegs = 1;
1411 for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
1412 const MachineOperand &MO = MI.getOperand(i);
1413 if (!MO.isReg() || MO.isImplicit())
1417 Binary |= NumRegs * 2;
1422 template<class CodeEmitter>
1423 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1424 // Part of binary is determined by TableGn.
1425 unsigned Binary = getBinaryCodeForInstr(MI);
1427 // Set the conditional execution predicate
1428 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1433 #include "ARMGenCodeEmitter.inc"