1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
59 void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<MachineModuleInfo>();
61 MachineFunctionPass::getAnalysisUsage(AU);
66 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
67 : MachineFunctionPass(&ID), JTI(0),
68 II((const ARMInstrInfo *)tm.getInstrInfo()),
69 TD(tm.getTargetData()), TM(tm),
70 MCE(mce), MCPEs(0), MJTEs(0),
71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73 /// getBinaryCodeForInstr - This function, generated by the
74 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75 /// machine instructions.
76 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78 bool runOnMachineFunction(MachineFunction &MF);
80 virtual const char *getPassName() const {
81 return "ARM Machine Code Emitter";
84 void emitInstruction(const MachineInstr &MI);
88 void emitWordLE(unsigned Binary);
89 void emitDWordLE(uint64_t Binary);
90 void emitConstPoolInstruction(const MachineInstr &MI);
91 void emitMOVi32immInstruction(const MachineInstr &MI);
92 void emitMOVi2piecesInstruction(const MachineInstr &MI);
93 void emitLEApcrelJTInstruction(const MachineInstr &MI);
94 void emitPseudoMoveInstruction(const MachineInstr &MI);
95 void addPCLabel(unsigned LabelID);
96 void emitPseudoInstruction(const MachineInstr &MI);
97 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
98 const TargetInstrDesc &TID,
99 const MachineOperand &MO,
102 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitBranchInstruction(const MachineInstr &MI);
128 void emitInlineJumpTable(unsigned JTIndex);
130 void emitMiscBranchInstruction(const MachineInstr &MI);
132 void emitVFPArithInstruction(const MachineInstr &MI);
134 void emitVFPConversionInstruction(const MachineInstr &MI);
136 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
140 void emitMiscInstruction(const MachineInstr &MI);
142 void emitNEON1RegModImm(const MachineInstr &MI);
144 /// getMachineOpValue - Return binary encoding of operand. If the machine
145 /// operand requires relocation, record the relocation and return zero.
146 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
147 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
148 return getMachineOpValue(MI, MI.getOperand(OpIdx));
151 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
152 /// machine operand requires relocation, record the relocation and return
154 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
156 unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
158 return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
161 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
163 unsigned getShiftOp(unsigned Imm) const ;
165 /// Routines that handle operands which add machine relocations which are
166 /// fixed up by the relocation stage.
167 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
168 bool MayNeedFarStub, bool Indirect,
170 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
171 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
172 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
173 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
174 intptr_t JTBase = 0);
178 char ARMCodeEmitter::ID = 0;
180 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
181 /// code to the specified MCE object.
182 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
183 JITCodeEmitter &JCE) {
184 return new ARMCodeEmitter(TM, JCE);
187 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
188 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
189 MF.getTarget().getRelocationModel() != Reloc::Static) &&
190 "JIT relocation model must be set to static or default!");
191 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
192 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
193 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
194 Subtarget = &TM.getSubtarget<ARMSubtarget>();
195 MCPEs = &MF.getConstantPool()->getConstants();
197 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
198 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
199 JTI->Initialize(MF, IsPIC);
200 MMI = &getAnalysis<MachineModuleInfo>();
201 MCE.setModuleInfo(MMI);
204 DEBUG(errs() << "JITTing function '"
205 << MF.getFunction()->getName() << "'\n");
206 MCE.startFunction(MF);
207 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
209 MCE.StartMachineBasicBlock(MBB);
210 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
214 } while (MCE.finishFunction(MF));
219 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
221 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
222 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
223 default: llvm_unreachable("Unknown shift opc!");
224 case ARM_AM::asr: return 2;
225 case ARM_AM::lsl: return 0;
226 case ARM_AM::lsr: return 1;
228 case ARM_AM::rrx: return 3;
233 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
234 /// machine operand requires relocation, record the relocation and return zero.
235 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
236 const MachineOperand &MO,
238 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
239 && "Relocation to this function should be for movt or movw");
242 return static_cast<unsigned>(MO.getImm());
243 else if (MO.isGlobal())
244 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
245 else if (MO.isSymbol())
246 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
248 emitMachineBasicBlock(MO.getMBB(), Reloc);
253 llvm_unreachable("Unsupported operand type for movw/movt");
258 /// getMachineOpValue - Return binary encoding of operand. If the machine
259 /// operand requires relocation, record the relocation and return zero.
260 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
261 const MachineOperand &MO) {
263 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
265 return static_cast<unsigned>(MO.getImm());
266 else if (MO.isGlobal())
267 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
268 else if (MO.isSymbol())
269 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
270 else if (MO.isCPI()) {
271 const TargetInstrDesc &TID = MI.getDesc();
272 // For VFP load, the immediate offset is multiplied by 4.
273 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
274 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
275 emitConstPoolAddress(MO.getIndex(), Reloc);
276 } else if (MO.isJTI())
277 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
279 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
289 /// emitGlobalAddress - Emit the specified address to the code stream.
291 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
292 bool MayNeedFarStub, bool Indirect,
294 MachineRelocation MR = Indirect
295 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
296 const_cast<GlobalValue *>(GV),
297 ACPV, MayNeedFarStub)
298 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
299 const_cast<GlobalValue *>(GV), ACPV,
301 MCE.addRelocation(MR);
304 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
305 /// be emitted to the current location in the function, and allow it to be PC
307 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
308 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
312 /// emitConstPoolAddress - Arrange for the address of an constant pool
313 /// to be emitted to the current location in the function, and allow it to be PC
315 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
316 // Tell JIT emitter we'll resolve the address.
317 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
318 Reloc, CPI, 0, true));
321 /// emitJumpTableAddress - Arrange for the address of a jump table to
322 /// be emitted to the current location in the function, and allow it to be PC
324 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
325 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
326 Reloc, JTIndex, 0, true));
329 /// emitMachineBasicBlock - Emit the specified address basic block.
330 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
331 unsigned Reloc, intptr_t JTBase) {
332 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
336 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
337 DEBUG(errs() << " 0x";
338 errs().write_hex(Binary) << "\n");
339 MCE.emitWordLE(Binary);
342 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
343 DEBUG(errs() << " 0x";
344 errs().write_hex(Binary) << "\n");
345 MCE.emitDWordLE(Binary);
348 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
349 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
351 MCE.processDebugLoc(MI.getDebugLoc(), true);
353 NumEmitted++; // Keep track of the # of mi's emitted
354 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
356 llvm_unreachable("Unhandled instruction encoding format!");
360 emitPseudoInstruction(MI);
363 case ARMII::DPSoRegFrm:
364 emitDataProcessingInstruction(MI);
368 emitLoadStoreInstruction(MI);
370 case ARMII::LdMiscFrm:
371 case ARMII::StMiscFrm:
372 emitMiscLoadStoreInstruction(MI);
374 case ARMII::LdStMulFrm:
375 emitLoadStoreMultipleInstruction(MI);
378 emitMulFrmInstruction(MI);
381 emitExtendInstruction(MI);
383 case ARMII::ArithMiscFrm:
384 emitMiscArithInstruction(MI);
387 emitBranchInstruction(MI);
389 case ARMII::BrMiscFrm:
390 emitMiscBranchInstruction(MI);
393 case ARMII::VFPUnaryFrm:
394 case ARMII::VFPBinaryFrm:
395 emitVFPArithInstruction(MI);
397 case ARMII::VFPConv1Frm:
398 case ARMII::VFPConv2Frm:
399 case ARMII::VFPConv3Frm:
400 case ARMII::VFPConv4Frm:
401 case ARMII::VFPConv5Frm:
402 emitVFPConversionInstruction(MI);
404 case ARMII::VFPLdStFrm:
405 emitVFPLoadStoreInstruction(MI);
407 case ARMII::VFPLdStMulFrm:
408 emitVFPLoadStoreMultipleInstruction(MI);
410 case ARMII::VFPMiscFrm:
411 emitMiscInstruction(MI);
413 // NEON instructions.
414 case ARMII::N1RegModImmFrm:
415 emitNEON1RegModImm(MI);
418 MCE.processDebugLoc(MI.getDebugLoc(), false);
421 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
422 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
423 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
424 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
426 // Remember the CONSTPOOL_ENTRY address for later relocation.
427 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
429 // Emit constpool island entry. In most cases, the actual values will be
430 // resolved and relocated after code emission.
431 if (MCPE.isMachineConstantPoolEntry()) {
432 ARMConstantPoolValue *ACPV =
433 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
435 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
436 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
438 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
439 const GlobalValue *GV = ACPV->getGV();
441 Reloc::Model RelocM = TM.getRelocationModel();
442 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
444 Subtarget->GVIsIndirectSymbol(GV, RelocM),
447 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
451 const Constant *CV = MCPE.Val.ConstVal;
454 errs() << " ** Constant pool #" << CPI << " @ "
455 << (void*)MCE.getCurrentPCValue() << " ";
456 if (const Function *F = dyn_cast<Function>(CV))
457 errs() << F->getName();
463 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
464 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
466 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
467 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
469 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
470 if (CFP->getType()->isFloatTy())
471 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
472 else if (CFP->getType()->isDoubleTy())
473 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
475 llvm_unreachable("Unable to handle this constantpool entry!");
478 llvm_unreachable("Unable to handle this constantpool entry!");
483 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
484 const MachineOperand &MO0 = MI.getOperand(0);
485 const MachineOperand &MO1 = MI.getOperand(1);
487 // Emit the 'movw' instruction.
488 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
490 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
492 // Set the conditional execution predicate.
493 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
496 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
498 // Encode imm16 as imm4:imm12
499 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
500 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
503 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
504 // Emit the 'movt' instruction.
505 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
507 // Set the conditional execution predicate.
508 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
511 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
513 // Encode imm16 as imm4:imm1, same as movw above.
514 Binary |= Hi16 & 0xFFF;
515 Binary |= ((Hi16 >> 12) & 0xF) << 16;
519 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
520 const MachineOperand &MO0 = MI.getOperand(0);
521 const MachineOperand &MO1 = MI.getOperand(1);
522 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
523 "Not a valid so_imm value!");
524 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
525 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
527 // Emit the 'mov' instruction.
528 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
530 // Set the conditional execution predicate.
531 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
534 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
537 // Set bit I(25) to identify this is the immediate form of <shifter_op>
538 Binary |= 1 << ARMII::I_BitShift;
539 Binary |= getMachineSoImmOpValue(V1);
542 // Now the 'orr' instruction.
543 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
545 // Set the conditional execution predicate.
546 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
549 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
552 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
555 // Set bit I(25) to identify this is the immediate form of <shifter_op>
556 Binary |= 1 << ARMII::I_BitShift;
557 Binary |= getMachineSoImmOpValue(V2);
561 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
562 // It's basically add r, pc, (LJTI - $+8)
564 const TargetInstrDesc &TID = MI.getDesc();
566 // Emit the 'add' instruction.
567 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
569 // Set the conditional execution predicate
570 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
572 // Encode S bit if MI modifies CPSR.
573 Binary |= getAddrModeSBit(MI, TID);
576 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
578 // Encode Rn which is PC.
579 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
581 // Encode the displacement.
582 Binary |= 1 << ARMII::I_BitShift;
583 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
588 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
589 unsigned Opcode = MI.getDesc().Opcode;
591 // Part of binary is determined by TableGn.
592 unsigned Binary = getBinaryCodeForInstr(MI);
594 // Set the conditional execution predicate
595 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
597 // Encode S bit if MI modifies CPSR.
598 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
599 Binary |= 1 << ARMII::S_BitShift;
601 // Encode register def if there is one.
602 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
604 // Encode the shift operation.
611 case ARM::MOVsrl_flag:
613 Binary |= (0x2 << 4) | (1 << 7);
615 case ARM::MOVsra_flag:
617 Binary |= (0x4 << 4) | (1 << 7);
621 // Encode register Rm.
622 Binary |= getMachineOpValue(MI, 1);
627 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
628 DEBUG(errs() << " ** LPC" << LabelID << " @ "
629 << (void*)MCE.getCurrentPCValue() << '\n');
630 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
633 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
634 unsigned Opcode = MI.getDesc().Opcode;
637 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
638 case TargetOpcode::INLINEASM: {
639 // We allow inline assembler nodes with empty bodies - they can
640 // implicitly define registers, which is ok for JIT.
641 if (MI.getOperand(0).getSymbolName()[0]) {
642 report_fatal_error("JIT does not support inline asm!");
646 case TargetOpcode::DBG_LABEL:
647 case TargetOpcode::EH_LABEL:
648 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
650 case TargetOpcode::IMPLICIT_DEF:
651 case TargetOpcode::KILL:
654 case ARM::CONSTPOOL_ENTRY:
655 emitConstPoolInstruction(MI);
658 // Remember of the address of the PC label for relocation later.
659 addPCLabel(MI.getOperand(2).getImm());
660 // PICADD is just an add instruction that implicitly read pc.
661 emitDataProcessingInstruction(MI, 0, ARM::PC);
668 // Remember of the address of the PC label for relocation later.
669 addPCLabel(MI.getOperand(2).getImm());
670 // These are just load / store instructions that implicitly read pc.
671 emitLoadStoreInstruction(MI, 0, ARM::PC);
678 // Remember of the address of the PC label for relocation later.
679 addPCLabel(MI.getOperand(2).getImm());
680 // These are just load / store instructions that implicitly read pc.
681 emitMiscLoadStoreInstruction(MI, ARM::PC);
686 emitMOVi32immInstruction(MI);
689 case ARM::MOVi2pieces:
690 // Two instructions to materialize a constant.
691 emitMOVi2piecesInstruction(MI);
693 case ARM::LEApcrelJT:
694 // Materialize jumptable address.
695 emitLEApcrelJTInstruction(MI);
698 case ARM::MOVsrl_flag:
699 case ARM::MOVsra_flag:
700 emitPseudoMoveInstruction(MI);
705 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
706 const TargetInstrDesc &TID,
707 const MachineOperand &MO,
709 unsigned Binary = getMachineOpValue(MI, MO);
711 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
712 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
713 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
715 // Encode the shift opcode.
717 unsigned Rs = MO1.getReg();
719 // Set shift operand (bit[7:4]).
724 // RRX - 0110 and bit[11:8] clear.
726 default: llvm_unreachable("Unknown shift opc!");
727 case ARM_AM::lsl: SBits = 0x1; break;
728 case ARM_AM::lsr: SBits = 0x3; break;
729 case ARM_AM::asr: SBits = 0x5; break;
730 case ARM_AM::ror: SBits = 0x7; break;
731 case ARM_AM::rrx: SBits = 0x6; break;
734 // Set shift operand (bit[6:4]).
740 default: llvm_unreachable("Unknown shift opc!");
741 case ARM_AM::lsl: SBits = 0x0; break;
742 case ARM_AM::lsr: SBits = 0x2; break;
743 case ARM_AM::asr: SBits = 0x4; break;
744 case ARM_AM::ror: SBits = 0x6; break;
747 Binary |= SBits << 4;
748 if (SOpc == ARM_AM::rrx)
751 // Encode the shift operation Rs or shift_imm (except rrx).
753 // Encode Rs bit[11:8].
754 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
756 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
759 // Encode shift_imm bit[11:7].
760 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
763 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
764 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
765 assert(SoImmVal != -1 && "Not a valid so_imm value!");
767 // Encode rotate_imm.
768 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
769 << ARMII::SoRotImmShift;
772 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
776 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
777 const TargetInstrDesc &TID) const {
778 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
779 const MachineOperand &MO = MI.getOperand(i-1);
780 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
781 return 1 << ARMII::S_BitShift;
786 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
788 unsigned ImplicitRn) {
789 const TargetInstrDesc &TID = MI.getDesc();
791 // Part of binary is determined by TableGn.
792 unsigned Binary = getBinaryCodeForInstr(MI);
794 // Set the conditional execution predicate
795 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
797 // Encode S bit if MI modifies CPSR.
798 Binary |= getAddrModeSBit(MI, TID);
800 // Encode register def if there is one.
801 unsigned NumDefs = TID.getNumDefs();
804 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
806 // Special handling for implicit use (e.g. PC).
807 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
808 << ARMII::RegRdShift);
810 if (TID.Opcode == ARM::MOVi16) {
811 // Get immediate from MI.
812 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
813 ARM::reloc_arm_movw);
814 // Encode imm which is the same as in emitMOVi32immInstruction().
815 Binary |= Lo16 & 0xFFF;
816 Binary |= ((Lo16 >> 12) & 0xF) << 16;
819 } else if(TID.Opcode == ARM::MOVTi16) {
820 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
821 ARM::reloc_arm_movt) >> 16);
822 Binary |= Hi16 & 0xFFF;
823 Binary |= ((Hi16 >> 12) & 0xF) << 16;
826 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
827 uint32_t v = ~MI.getOperand(2).getImm();
828 int32_t lsb = CountTrailingZeros_32(v);
829 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
830 // Instr{20-16} = msb, Instr{11-7} = lsb
831 Binary |= (msb & 0x1F) << 16;
832 Binary |= (lsb & 0x1F) << 7;
835 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
836 // Encode Rn in Instr{0-3}
837 Binary |= getMachineOpValue(MI, OpIdx++);
839 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
840 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
842 // Instr{20-16} = widthm1, Instr{11-7} = lsb
843 Binary |= (widthm1 & 0x1F) << 16;
844 Binary |= (lsb & 0x1F) << 7;
849 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
850 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
853 // Encode first non-shifter register operand if there is one.
854 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
857 // Special handling for implicit use (e.g. PC).
858 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
859 << ARMII::RegRnShift);
861 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
866 // Encode shifter operand.
867 const MachineOperand &MO = MI.getOperand(OpIdx);
868 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
870 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
875 // Encode register Rm.
876 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
881 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
886 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
888 unsigned ImplicitRn) {
889 const TargetInstrDesc &TID = MI.getDesc();
890 unsigned Form = TID.TSFlags & ARMII::FormMask;
891 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
893 // Part of binary is determined by TableGn.
894 unsigned Binary = getBinaryCodeForInstr(MI);
896 // Set the conditional execution predicate
897 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
901 // Operand 0 of a pre- and post-indexed store is the address base
902 // writeback. Skip it.
903 bool Skipped = false;
904 if (IsPrePost && Form == ARMII::StFrm) {
911 // Special handling for implicit use (e.g. PC).
912 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
913 << ARMII::RegRdShift);
915 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
917 // Set second operand
919 // Special handling for implicit use (e.g. PC).
920 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
921 << ARMII::RegRnShift);
923 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
925 // If this is a two-address operand, skip it. e.g. LDR_PRE.
926 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
929 const MachineOperand &MO2 = MI.getOperand(OpIdx);
930 unsigned AM2Opc = (ImplicitRn == ARM::PC)
931 ? 0 : MI.getOperand(OpIdx+1).getImm();
933 // Set bit U(23) according to sign of immed value (positive or negative).
934 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
936 if (!MO2.getReg()) { // is immediate
937 if (ARM_AM::getAM2Offset(AM2Opc))
938 // Set the value of offset_12 field
939 Binary |= ARM_AM::getAM2Offset(AM2Opc);
944 // Set bit I(25), because this is not in immediate enconding.
945 Binary |= 1 << ARMII::I_BitShift;
946 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
947 // Set bit[3:0] to the corresponding Rm register
948 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
950 // If this instr is in scaled register offset/index instruction, set
951 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
952 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
953 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
954 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
960 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
961 unsigned ImplicitRn) {
962 const TargetInstrDesc &TID = MI.getDesc();
963 unsigned Form = TID.TSFlags & ARMII::FormMask;
964 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
966 // Part of binary is determined by TableGn.
967 unsigned Binary = getBinaryCodeForInstr(MI);
969 // Set the conditional execution predicate
970 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
974 // Operand 0 of a pre- and post-indexed store is the address base
975 // writeback. Skip it.
976 bool Skipped = false;
977 if (IsPrePost && Form == ARMII::StMiscFrm) {
983 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
985 // Skip LDRD and STRD's second operand.
986 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
989 // Set second operand
991 // Special handling for implicit use (e.g. PC).
992 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
993 << ARMII::RegRnShift);
995 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
997 // If this is a two-address operand, skip it. e.g. LDRH_POST.
998 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1001 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1002 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1003 ? 0 : MI.getOperand(OpIdx+1).getImm();
1005 // Set bit U(23) according to sign of immed value (positive or negative)
1006 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1009 // If this instr is in register offset/index encoding, set bit[3:0]
1010 // to the corresponding Rm register.
1012 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1017 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1018 Binary |= 1 << ARMII::AM3_I_BitShift;
1019 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1021 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1022 Binary |= (ImmOffs & 0xF); // immedL
1028 static unsigned getAddrModeUPBits(unsigned Mode) {
1029 unsigned Binary = 0;
1031 // Set addressing mode by modifying bits U(23) and P(24)
1032 // IA - Increment after - bit U = 1 and bit P = 0
1033 // IB - Increment before - bit U = 1 and bit P = 1
1034 // DA - Decrement after - bit U = 0 and bit P = 0
1035 // DB - Decrement before - bit U = 0 and bit P = 1
1037 default: llvm_unreachable("Unknown addressing sub-mode!");
1038 case ARM_AM::da: break;
1039 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1040 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1041 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1047 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1048 const TargetInstrDesc &TID = MI.getDesc();
1049 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1051 // Part of binary is determined by TableGn.
1052 unsigned Binary = getBinaryCodeForInstr(MI);
1054 // Set the conditional execution predicate
1055 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1057 // Skip operand 0 of an instruction with base register update.
1062 // Set base address operand
1063 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1065 // Set addressing mode by modifying bits U(23) and P(24)
1066 const MachineOperand &MO = MI.getOperand(OpIdx++);
1067 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1071 Binary |= 0x1 << ARMII::W_BitShift;
1074 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1075 const MachineOperand &MO = MI.getOperand(i);
1076 if (!MO.isReg() || MO.isImplicit())
1078 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1079 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1081 Binary |= 0x1 << RegNum;
1087 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1088 const TargetInstrDesc &TID = MI.getDesc();
1090 // Part of binary is determined by TableGn.
1091 unsigned Binary = getBinaryCodeForInstr(MI);
1093 // Set the conditional execution predicate
1094 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1096 // Encode S bit if MI modifies CPSR.
1097 Binary |= getAddrModeSBit(MI, TID);
1099 // 32x32->64bit operations have two destination registers. The number
1100 // of register definitions will tell us if that's what we're dealing with.
1102 if (TID.getNumDefs() == 2)
1103 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1106 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1109 Binary |= getMachineOpValue(MI, OpIdx++);
1112 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1114 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1115 // it as Rn (for multiply, that's in the same offset as RdLo.
1116 if (TID.getNumOperands() > OpIdx &&
1117 !TID.OpInfo[OpIdx].isPredicate() &&
1118 !TID.OpInfo[OpIdx].isOptionalDef())
1119 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1124 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1125 const TargetInstrDesc &TID = MI.getDesc();
1127 // Part of binary is determined by TableGn.
1128 unsigned Binary = getBinaryCodeForInstr(MI);
1130 // Set the conditional execution predicate
1131 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1136 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1138 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1139 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1141 // Two register operand form.
1143 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1146 Binary |= getMachineOpValue(MI, MO2);
1149 Binary |= getMachineOpValue(MI, MO1);
1152 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1153 if (MI.getOperand(OpIdx).isImm() &&
1154 !TID.OpInfo[OpIdx].isPredicate() &&
1155 !TID.OpInfo[OpIdx].isOptionalDef())
1156 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1161 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1162 const TargetInstrDesc &TID = MI.getDesc();
1164 // Part of binary is determined by TableGn.
1165 unsigned Binary = getBinaryCodeForInstr(MI);
1167 // Set the conditional execution predicate
1168 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1173 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1175 const MachineOperand &MO = MI.getOperand(OpIdx++);
1176 if (OpIdx == TID.getNumOperands() ||
1177 TID.OpInfo[OpIdx].isPredicate() ||
1178 TID.OpInfo[OpIdx].isOptionalDef()) {
1179 // Encode Rm and it's done.
1180 Binary |= getMachineOpValue(MI, MO);
1186 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1189 Binary |= getMachineOpValue(MI, OpIdx++);
1191 // Encode shift_imm.
1192 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1193 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1194 Binary |= ShiftAmt << ARMII::ShiftShift;
1199 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1200 const TargetInstrDesc &TID = MI.getDesc();
1202 if (TID.Opcode == ARM::TPsoft) {
1203 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1206 // Part of binary is determined by TableGn.
1207 unsigned Binary = getBinaryCodeForInstr(MI);
1209 // Set the conditional execution predicate
1210 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1212 // Set signed_immed_24 field
1213 Binary |= getMachineOpValue(MI, 0);
1218 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1219 // Remember the base address of the inline jump table.
1220 uintptr_t JTBase = MCE.getCurrentPCValue();
1221 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1222 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1225 // Now emit the jump table entries.
1226 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1227 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1229 // DestBB address - JT base.
1230 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1232 // Absolute DestBB address.
1233 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1238 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1239 const TargetInstrDesc &TID = MI.getDesc();
1241 // Handle jump tables.
1242 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1243 // First emit a ldr pc, [] instruction.
1244 emitDataProcessingInstruction(MI, ARM::PC);
1246 // Then emit the inline jump table.
1248 (TID.Opcode == ARM::BR_JTr)
1249 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1250 emitInlineJumpTable(JTIndex);
1252 } else if (TID.Opcode == ARM::BR_JTm) {
1253 // First emit a ldr pc, [] instruction.
1254 emitLoadStoreInstruction(MI, ARM::PC);
1256 // Then emit the inline jump table.
1257 emitInlineJumpTable(MI.getOperand(3).getIndex());
1261 // Part of binary is determined by TableGn.
1262 unsigned Binary = getBinaryCodeForInstr(MI);
1264 // Set the conditional execution predicate
1265 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1267 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1268 // The return register is LR.
1269 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1271 // otherwise, set the return register
1272 Binary |= getMachineOpValue(MI, 0);
1277 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1278 unsigned RegD = MI.getOperand(OpIdx).getReg();
1279 unsigned Binary = 0;
1280 bool isSPVFP = false;
1281 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1283 Binary |= RegD << ARMII::RegRdShift;
1285 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1286 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1291 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1292 unsigned RegN = MI.getOperand(OpIdx).getReg();
1293 unsigned Binary = 0;
1294 bool isSPVFP = false;
1295 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1297 Binary |= RegN << ARMII::RegRnShift;
1299 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1300 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1305 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1306 unsigned RegM = MI.getOperand(OpIdx).getReg();
1307 unsigned Binary = 0;
1308 bool isSPVFP = false;
1309 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1313 Binary |= ((RegM & 0x1E) >> 1);
1314 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1319 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1320 const TargetInstrDesc &TID = MI.getDesc();
1322 // Part of binary is determined by TableGn.
1323 unsigned Binary = getBinaryCodeForInstr(MI);
1325 // Set the conditional execution predicate
1326 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1329 assert((Binary & ARMII::D_BitShift) == 0 &&
1330 (Binary & ARMII::N_BitShift) == 0 &&
1331 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1334 Binary |= encodeVFPRd(MI, OpIdx++);
1336 // If this is a two-address operand, skip it, e.g. FMACD.
1337 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1341 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1342 Binary |= encodeVFPRn(MI, OpIdx++);
1344 if (OpIdx == TID.getNumOperands() ||
1345 TID.OpInfo[OpIdx].isPredicate() ||
1346 TID.OpInfo[OpIdx].isOptionalDef()) {
1347 // FCMPEZD etc. has only one operand.
1353 Binary |= encodeVFPRm(MI, OpIdx);
1358 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1359 const TargetInstrDesc &TID = MI.getDesc();
1360 unsigned Form = TID.TSFlags & ARMII::FormMask;
1362 // Part of binary is determined by TableGn.
1363 unsigned Binary = getBinaryCodeForInstr(MI);
1365 // Set the conditional execution predicate
1366 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1370 case ARMII::VFPConv1Frm:
1371 case ARMII::VFPConv2Frm:
1372 case ARMII::VFPConv3Frm:
1374 Binary |= encodeVFPRd(MI, 0);
1376 case ARMII::VFPConv4Frm:
1378 Binary |= encodeVFPRn(MI, 0);
1380 case ARMII::VFPConv5Frm:
1382 Binary |= encodeVFPRm(MI, 0);
1388 case ARMII::VFPConv1Frm:
1390 Binary |= encodeVFPRm(MI, 1);
1392 case ARMII::VFPConv2Frm:
1393 case ARMII::VFPConv3Frm:
1395 Binary |= encodeVFPRn(MI, 1);
1397 case ARMII::VFPConv4Frm:
1398 case ARMII::VFPConv5Frm:
1400 Binary |= encodeVFPRd(MI, 1);
1404 if (Form == ARMII::VFPConv5Frm)
1406 Binary |= encodeVFPRn(MI, 2);
1407 else if (Form == ARMII::VFPConv3Frm)
1409 Binary |= encodeVFPRm(MI, 2);
1414 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1415 // Part of binary is determined by TableGn.
1416 unsigned Binary = getBinaryCodeForInstr(MI);
1418 // Set the conditional execution predicate
1419 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1424 Binary |= encodeVFPRd(MI, OpIdx++);
1426 // Encode address base.
1427 const MachineOperand &Base = MI.getOperand(OpIdx++);
1428 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1430 // If there is a non-zero immediate offset, encode it.
1432 const MachineOperand &Offset = MI.getOperand(OpIdx);
1433 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1434 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1435 Binary |= 1 << ARMII::U_BitShift;
1442 // If immediate offset is omitted, default to +0.
1443 Binary |= 1 << ARMII::U_BitShift;
1449 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1450 const TargetInstrDesc &TID = MI.getDesc();
1451 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1453 // Part of binary is determined by TableGn.
1454 unsigned Binary = getBinaryCodeForInstr(MI);
1456 // Set the conditional execution predicate
1457 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1459 // Skip operand 0 of an instruction with base register update.
1464 // Set base address operand
1465 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1467 // Set addressing mode by modifying bits U(23) and P(24)
1468 const MachineOperand &MO = MI.getOperand(OpIdx++);
1469 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1473 Binary |= 0x1 << ARMII::W_BitShift;
1475 // First register is encoded in Dd.
1476 Binary |= encodeVFPRd(MI, OpIdx+2);
1478 // Number of registers are encoded in offset field.
1479 unsigned NumRegs = 1;
1480 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1481 const MachineOperand &MO = MI.getOperand(i);
1482 if (!MO.isReg() || MO.isImplicit())
1486 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1487 // Otherwise, it will be 0, in the case of 32-bit registers.
1489 Binary |= NumRegs * 2;
1496 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1497 unsigned Opcode = MI.getDesc().Opcode;
1498 // Part of binary is determined by TableGn.
1499 unsigned Binary = getBinaryCodeForInstr(MI);
1501 // Set the conditional execution predicate
1502 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1506 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1509 // No further encoding needed.
1514 const MachineOperand &MO0 = MI.getOperand(0);
1516 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1517 << ARMII::RegRdShift;
1522 case ARM::FCONSTS: {
1524 Binary |= encodeVFPRd(MI, 0);
1526 // Encode imm., Table A7-18 VFP modified immediate constants
1527 const MachineOperand &MO1 = MI.getOperand(1);
1528 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1529 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1530 unsigned ModifiedImm;
1532 if(Opcode == ARM::FCONSTS)
1533 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1534 (Imm & 0x03F80000) >> 19; // bcdefgh
1535 else // Opcode == ARM::FCONSTD
1536 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1537 (Imm & 0x007F0000) >> 16; // bcdefgh
1539 // Insts{19-16} = abcd, Insts{3-0} = efgh
1540 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1541 Binary |= (ModifiedImm & 0xF);
1549 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1550 unsigned RegD = MI.getOperand(OpIdx).getReg();
1551 unsigned Binary = 0;
1552 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1553 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1554 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1558 void ARMCodeEmitter::emitNEON1RegModImm(const MachineInstr &MI) {
1559 unsigned Binary = getBinaryCodeForInstr(MI);
1560 // Destination register is encoded in Dd.
1561 Binary |= encodeNEONRd(MI, 0);
1562 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1563 unsigned Imm = MI.getOperand(1).getImm();
1564 unsigned Op = (Imm >> 12) & 1;
1565 Binary |= (Op << 5);
1566 unsigned Cmode = (Imm >> 8) & 0xf;
1567 Binary |= (Cmode << 8);
1568 unsigned I = (Imm >> 7) & 1;
1569 Binary |= (I << 24);
1570 unsigned Imm3 = (Imm >> 4) & 0x7;
1571 Binary |= (Imm3 << 16);
1572 unsigned Imm4 = Imm & 0xf;
1577 #include "ARMGenCodeEmitter.inc"