1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
212 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
216 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
220 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
227 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
229 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
231 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
232 unsigned Op) const { return 0; }
233 unsigned getMsbOpValue(const MachineInstr &MI,
234 unsigned Op) const { return 0; }
235 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
237 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
240 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
243 // {12} = (U)nsigned (add == '1', sub == '0')
245 const MachineOperand &MO = MI.getOperand(Op);
246 const MachineOperand &MO1 = MI.getOperand(Op + 1);
248 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
251 unsigned Reg = getARMRegisterNumbering(MO.getReg());
252 int32_t Imm12 = MO1.getImm();
254 Binary = Imm12 & 0xfff;
257 Binary |= (Reg << 13);
261 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
265 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
267 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
269 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
273 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
275 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
277 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
279 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
281 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
283 // {12} = (U)nsigned (add == '1', sub == '0')
285 const MachineOperand &MO = MI.getOperand(Op);
286 const MachineOperand &MO1 = MI.getOperand(Op + 1);
288 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
291 unsigned Reg = getARMRegisterNumbering(MO.getReg());
292 int32_t Imm12 = MO1.getImm();
294 // Special value for #-0
295 if (Imm12 == INT32_MIN)
298 // Immediate is always encoded as positive. The 'U' bit controls add vs
306 uint32_t Binary = Imm12 & 0xfff;
309 Binary |= (Reg << 13);
312 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
315 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
318 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
320 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
322 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
324 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
327 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
328 /// machine operand requires relocation, record the relocation and return
330 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
333 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
335 unsigned getShiftOp(unsigned Imm) const ;
337 /// Routines that handle operands which add machine relocations which are
338 /// fixed up by the relocation stage.
339 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
340 bool MayNeedFarStub, bool Indirect,
341 intptr_t ACPV = 0) const;
342 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
343 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
344 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
345 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
346 intptr_t JTBase = 0) const;
350 char ARMCodeEmitter::ID = 0;
352 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
353 /// code to the specified MCE object.
354 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
355 JITCodeEmitter &JCE) {
356 return new ARMCodeEmitter(TM, JCE);
359 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
360 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
361 MF.getTarget().getRelocationModel() != Reloc::Static) &&
362 "JIT relocation model must be set to static or default!");
363 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
364 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
365 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
366 Subtarget = &TM.getSubtarget<ARMSubtarget>();
367 MCPEs = &MF.getConstantPool()->getConstants();
369 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
370 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
371 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
372 JTI->Initialize(MF, IsPIC);
373 MMI = &getAnalysis<MachineModuleInfo>();
374 MCE.setModuleInfo(MMI);
377 DEBUG(errs() << "JITTing function '"
378 << MF.getFunction()->getName() << "'\n");
379 MCE.startFunction(MF);
380 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
382 MCE.StartMachineBasicBlock(MBB);
383 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
387 } while (MCE.finishFunction(MF));
392 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
394 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
395 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
396 default: llvm_unreachable("Unknown shift opc!");
397 case ARM_AM::asr: return 2;
398 case ARM_AM::lsl: return 0;
399 case ARM_AM::lsr: return 1;
401 case ARM_AM::rrx: return 3;
406 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
407 /// machine operand requires relocation, record the relocation and return zero.
408 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
409 const MachineOperand &MO,
411 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
412 && "Relocation to this function should be for movt or movw");
415 return static_cast<unsigned>(MO.getImm());
416 else if (MO.isGlobal())
417 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
418 else if (MO.isSymbol())
419 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
421 emitMachineBasicBlock(MO.getMBB(), Reloc);
426 llvm_unreachable("Unsupported operand type for movw/movt");
431 /// getMachineOpValue - Return binary encoding of operand. If the machine
432 /// operand requires relocation, record the relocation and return zero.
433 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
434 const MachineOperand &MO) const {
436 return getARMRegisterNumbering(MO.getReg());
438 return static_cast<unsigned>(MO.getImm());
439 else if (MO.isGlobal())
440 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
441 else if (MO.isSymbol())
442 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
443 else if (MO.isCPI()) {
444 const TargetInstrDesc &TID = MI.getDesc();
445 // For VFP load, the immediate offset is multiplied by 4.
446 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
447 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
448 emitConstPoolAddress(MO.getIndex(), Reloc);
449 } else if (MO.isJTI())
450 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
452 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
454 llvm_unreachable("Unable to encode MachineOperand!");
458 /// emitGlobalAddress - Emit the specified address to the code stream.
460 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
461 bool MayNeedFarStub, bool Indirect,
462 intptr_t ACPV) const {
463 MachineRelocation MR = Indirect
464 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
465 const_cast<GlobalValue *>(GV),
466 ACPV, MayNeedFarStub)
467 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
468 const_cast<GlobalValue *>(GV), ACPV,
470 MCE.addRelocation(MR);
473 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
474 /// be emitted to the current location in the function, and allow it to be PC
476 void ARMCodeEmitter::
477 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
478 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
482 /// emitConstPoolAddress - Arrange for the address of an constant pool
483 /// to be emitted to the current location in the function, and allow it to be PC
485 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
486 // Tell JIT emitter we'll resolve the address.
487 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
488 Reloc, CPI, 0, true));
491 /// emitJumpTableAddress - Arrange for the address of a jump table to
492 /// be emitted to the current location in the function, and allow it to be PC
494 void ARMCodeEmitter::
495 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
496 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
497 Reloc, JTIndex, 0, true));
500 /// emitMachineBasicBlock - Emit the specified address basic block.
501 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
503 intptr_t JTBase) const {
504 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
508 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
509 DEBUG(errs() << " 0x";
510 errs().write_hex(Binary) << "\n");
511 MCE.emitWordLE(Binary);
514 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
515 DEBUG(errs() << " 0x";
516 errs().write_hex(Binary) << "\n");
517 MCE.emitDWordLE(Binary);
520 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
521 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
523 MCE.processDebugLoc(MI.getDebugLoc(), true);
525 ++NumEmitted; // Keep track of the # of mi's emitted
526 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
528 llvm_unreachable("Unhandled instruction encoding format!");
532 if (MI.getOpcode() == ARM::LEApcrelJT) {
533 // Materialize jumptable address.
534 emitLEApcrelJTInstruction(MI);
537 llvm_unreachable("Unhandled instruction encoding!");
540 emitPseudoInstruction(MI);
543 case ARMII::DPSoRegFrm:
544 emitDataProcessingInstruction(MI);
548 emitLoadStoreInstruction(MI);
550 case ARMII::LdMiscFrm:
551 case ARMII::StMiscFrm:
552 emitMiscLoadStoreInstruction(MI);
554 case ARMII::LdStMulFrm:
555 emitLoadStoreMultipleInstruction(MI);
558 emitMulFrmInstruction(MI);
561 emitExtendInstruction(MI);
563 case ARMII::ArithMiscFrm:
564 emitMiscArithInstruction(MI);
567 emitSaturateInstruction(MI);
570 emitBranchInstruction(MI);
572 case ARMII::BrMiscFrm:
573 emitMiscBranchInstruction(MI);
576 case ARMII::VFPUnaryFrm:
577 case ARMII::VFPBinaryFrm:
578 emitVFPArithInstruction(MI);
580 case ARMII::VFPConv1Frm:
581 case ARMII::VFPConv2Frm:
582 case ARMII::VFPConv3Frm:
583 case ARMII::VFPConv4Frm:
584 case ARMII::VFPConv5Frm:
585 emitVFPConversionInstruction(MI);
587 case ARMII::VFPLdStFrm:
588 emitVFPLoadStoreInstruction(MI);
590 case ARMII::VFPLdStMulFrm:
591 emitVFPLoadStoreMultipleInstruction(MI);
594 // NEON instructions.
595 case ARMII::NGetLnFrm:
596 case ARMII::NSetLnFrm:
597 emitNEONLaneInstruction(MI);
600 emitNEONDupInstruction(MI);
602 case ARMII::N1RegModImmFrm:
603 emitNEON1RegModImmInstruction(MI);
605 case ARMII::N2RegFrm:
606 emitNEON2RegInstruction(MI);
608 case ARMII::N3RegFrm:
609 emitNEON3RegInstruction(MI);
612 MCE.processDebugLoc(MI.getDebugLoc(), false);
615 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
616 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
617 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
618 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
620 // Remember the CONSTPOOL_ENTRY address for later relocation.
621 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
623 // Emit constpool island entry. In most cases, the actual values will be
624 // resolved and relocated after code emission.
625 if (MCPE.isMachineConstantPoolEntry()) {
626 ARMConstantPoolValue *ACPV =
627 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
629 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
630 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
632 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
633 const GlobalValue *GV = ACPV->getGV();
635 Reloc::Model RelocM = TM.getRelocationModel();
636 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
638 Subtarget->GVIsIndirectSymbol(GV, RelocM),
641 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
645 const Constant *CV = MCPE.Val.ConstVal;
648 errs() << " ** Constant pool #" << CPI << " @ "
649 << (void*)MCE.getCurrentPCValue() << " ";
650 if (const Function *F = dyn_cast<Function>(CV))
651 errs() << F->getName();
657 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
658 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
660 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
661 uint32_t Val = uint32_t(*CI->getValue().getRawData());
663 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
664 if (CFP->getType()->isFloatTy())
665 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
666 else if (CFP->getType()->isDoubleTy())
667 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
669 llvm_unreachable("Unable to handle this constantpool entry!");
672 llvm_unreachable("Unable to handle this constantpool entry!");
677 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
678 const MachineOperand &MO0 = MI.getOperand(0);
679 const MachineOperand &MO1 = MI.getOperand(1);
681 // Emit the 'movw' instruction.
682 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
684 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
686 // Set the conditional execution predicate.
687 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
690 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
692 // Encode imm16 as imm4:imm12
693 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
694 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
697 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
698 // Emit the 'movt' instruction.
699 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
701 // Set the conditional execution predicate.
702 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
705 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
707 // Encode imm16 as imm4:imm1, same as movw above.
708 Binary |= Hi16 & 0xFFF;
709 Binary |= ((Hi16 >> 12) & 0xF) << 16;
713 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
714 const MachineOperand &MO0 = MI.getOperand(0);
715 const MachineOperand &MO1 = MI.getOperand(1);
716 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
717 "Not a valid so_imm value!");
718 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
719 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
721 // Emit the 'mov' instruction.
722 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
724 // Set the conditional execution predicate.
725 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
728 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
731 // Set bit I(25) to identify this is the immediate form of <shifter_op>
732 Binary |= 1 << ARMII::I_BitShift;
733 Binary |= getMachineSoImmOpValue(V1);
736 // Now the 'orr' instruction.
737 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
739 // Set the conditional execution predicate.
740 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
743 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
746 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
749 // Set bit I(25) to identify this is the immediate form of <shifter_op>
750 Binary |= 1 << ARMII::I_BitShift;
751 Binary |= getMachineSoImmOpValue(V2);
755 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
756 // It's basically add r, pc, (LJTI - $+8)
758 const TargetInstrDesc &TID = MI.getDesc();
760 // Emit the 'add' instruction.
761 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
763 // Set the conditional execution predicate
764 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
766 // Encode S bit if MI modifies CPSR.
767 Binary |= getAddrModeSBit(MI, TID);
770 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
772 // Encode Rn which is PC.
773 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
775 // Encode the displacement.
776 Binary |= 1 << ARMII::I_BitShift;
777 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
782 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
783 unsigned Opcode = MI.getDesc().Opcode;
785 // Part of binary is determined by TableGn.
786 unsigned Binary = getBinaryCodeForInstr(MI);
788 // Set the conditional execution predicate
789 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
791 // Encode S bit if MI modifies CPSR.
792 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
793 Binary |= 1 << ARMII::S_BitShift;
795 // Encode register def if there is one.
796 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
798 // Encode the shift operation.
805 case ARM::MOVsrl_flag:
807 Binary |= (0x2 << 4) | (1 << 7);
809 case ARM::MOVsra_flag:
811 Binary |= (0x4 << 4) | (1 << 7);
815 // Encode register Rm.
816 Binary |= getMachineOpValue(MI, 1);
821 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
822 DEBUG(errs() << " ** LPC" << LabelID << " @ "
823 << (void*)MCE.getCurrentPCValue() << '\n');
824 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
827 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
828 unsigned Opcode = MI.getDesc().Opcode;
831 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
833 case ARM::BMOVPCRX_CALL:
835 case ARM::BMOVPCRXr9_CALL: {
836 // First emit mov lr, pc
837 unsigned Binary = 0x01a0e00f;
838 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
841 // and then emit the branch.
842 emitMiscBranchInstruction(MI);
845 case TargetOpcode::INLINEASM: {
846 // We allow inline assembler nodes with empty bodies - they can
847 // implicitly define registers, which is ok for JIT.
848 if (MI.getOperand(0).getSymbolName()[0]) {
849 report_fatal_error("JIT does not support inline asm!");
853 case TargetOpcode::PROLOG_LABEL:
854 case TargetOpcode::EH_LABEL:
855 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
857 case TargetOpcode::IMPLICIT_DEF:
858 case TargetOpcode::KILL:
861 case ARM::CONSTPOOL_ENTRY:
862 emitConstPoolInstruction(MI);
865 // Remember of the address of the PC label for relocation later.
866 addPCLabel(MI.getOperand(2).getImm());
867 // PICADD is just an add instruction that implicitly read pc.
868 emitDataProcessingInstruction(MI, 0, ARM::PC);
875 // Remember of the address of the PC label for relocation later.
876 addPCLabel(MI.getOperand(2).getImm());
877 // These are just load / store instructions that implicitly read pc.
878 emitLoadStoreInstruction(MI, 0, ARM::PC);
885 // Remember of the address of the PC label for relocation later.
886 addPCLabel(MI.getOperand(2).getImm());
887 // These are just load / store instructions that implicitly read pc.
888 emitMiscLoadStoreInstruction(MI, ARM::PC);
893 // Two instructions to materialize a constant.
894 if (Subtarget->hasV6T2Ops())
895 emitMOVi32immInstruction(MI);
897 emitMOVi2piecesInstruction(MI);
900 case ARM::LEApcrelJT:
901 // Materialize jumptable address.
902 emitLEApcrelJTInstruction(MI);
905 case ARM::MOVsrl_flag:
906 case ARM::MOVsra_flag:
907 emitPseudoMoveInstruction(MI);
912 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
913 const TargetInstrDesc &TID,
914 const MachineOperand &MO,
916 unsigned Binary = getMachineOpValue(MI, MO);
918 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
919 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
920 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
922 // Encode the shift opcode.
924 unsigned Rs = MO1.getReg();
926 // Set shift operand (bit[7:4]).
931 // RRX - 0110 and bit[11:8] clear.
933 default: llvm_unreachable("Unknown shift opc!");
934 case ARM_AM::lsl: SBits = 0x1; break;
935 case ARM_AM::lsr: SBits = 0x3; break;
936 case ARM_AM::asr: SBits = 0x5; break;
937 case ARM_AM::ror: SBits = 0x7; break;
938 case ARM_AM::rrx: SBits = 0x6; break;
941 // Set shift operand (bit[6:4]).
947 default: llvm_unreachable("Unknown shift opc!");
948 case ARM_AM::lsl: SBits = 0x0; break;
949 case ARM_AM::lsr: SBits = 0x2; break;
950 case ARM_AM::asr: SBits = 0x4; break;
951 case ARM_AM::ror: SBits = 0x6; break;
954 Binary |= SBits << 4;
955 if (SOpc == ARM_AM::rrx)
958 // Encode the shift operation Rs or shift_imm (except rrx).
960 // Encode Rs bit[11:8].
961 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
962 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
965 // Encode shift_imm bit[11:7].
966 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
969 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
970 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
971 assert(SoImmVal != -1 && "Not a valid so_imm value!");
973 // Encode rotate_imm.
974 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
975 << ARMII::SoRotImmShift;
978 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
982 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
983 const TargetInstrDesc &TID) const {
984 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){
985 const MachineOperand &MO = MI.getOperand(i-1);
986 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
987 return 1 << ARMII::S_BitShift;
992 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
994 unsigned ImplicitRn) {
995 const TargetInstrDesc &TID = MI.getDesc();
997 // Part of binary is determined by TableGn.
998 unsigned Binary = getBinaryCodeForInstr(MI);
1000 // Set the conditional execution predicate
1001 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1003 // Encode S bit if MI modifies CPSR.
1004 Binary |= getAddrModeSBit(MI, TID);
1006 // Encode register def if there is one.
1007 unsigned NumDefs = TID.getNumDefs();
1010 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1011 else if (ImplicitRd)
1012 // Special handling for implicit use (e.g. PC).
1013 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1015 if (TID.Opcode == ARM::MOVi16) {
1016 // Get immediate from MI.
1017 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1018 ARM::reloc_arm_movw);
1019 // Encode imm which is the same as in emitMOVi32immInstruction().
1020 Binary |= Lo16 & 0xFFF;
1021 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1024 } else if(TID.Opcode == ARM::MOVTi16) {
1025 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1026 ARM::reloc_arm_movt) >> 16);
1027 Binary |= Hi16 & 0xFFF;
1028 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1031 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1032 uint32_t v = ~MI.getOperand(2).getImm();
1033 int32_t lsb = CountTrailingZeros_32(v);
1034 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1035 // Instr{20-16} = msb, Instr{11-7} = lsb
1036 Binary |= (msb & 0x1F) << 16;
1037 Binary |= (lsb & 0x1F) << 7;
1040 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1041 // Encode Rn in Instr{0-3}
1042 Binary |= getMachineOpValue(MI, OpIdx++);
1044 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1045 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1047 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1048 Binary |= (widthm1 & 0x1F) << 16;
1049 Binary |= (lsb & 0x1F) << 7;
1054 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1055 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1058 // Encode first non-shifter register operand if there is one.
1059 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1062 // Special handling for implicit use (e.g. PC).
1063 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1065 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1070 // Encode shifter operand.
1071 const MachineOperand &MO = MI.getOperand(OpIdx);
1072 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1074 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1079 // Encode register Rm.
1080 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1085 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1090 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1091 unsigned ImplicitRd,
1092 unsigned ImplicitRn) {
1093 const TargetInstrDesc &TID = MI.getDesc();
1094 unsigned Form = TID.TSFlags & ARMII::FormMask;
1095 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1097 // Part of binary is determined by TableGn.
1098 unsigned Binary = getBinaryCodeForInstr(MI);
1100 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1101 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1102 MI.getOpcode() == ARM::STRi12) {
1107 // Set the conditional execution predicate
1108 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1112 // Operand 0 of a pre- and post-indexed store is the address base
1113 // writeback. Skip it.
1114 bool Skipped = false;
1115 if (IsPrePost && Form == ARMII::StFrm) {
1120 // Set first operand
1122 // Special handling for implicit use (e.g. PC).
1123 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1125 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1127 // Set second operand
1129 // Special handling for implicit use (e.g. PC).
1130 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1132 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1134 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1135 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1138 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1139 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1140 ? 0 : MI.getOperand(OpIdx+1).getImm();
1142 // Set bit U(23) according to sign of immed value (positive or negative).
1143 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1145 if (!MO2.getReg()) { // is immediate
1146 if (ARM_AM::getAM2Offset(AM2Opc))
1147 // Set the value of offset_12 field
1148 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1153 // Set bit I(25), because this is not in immediate encoding.
1154 Binary |= 1 << ARMII::I_BitShift;
1155 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1156 // Set bit[3:0] to the corresponding Rm register
1157 Binary |= getARMRegisterNumbering(MO2.getReg());
1159 // If this instr is in scaled register offset/index instruction, set
1160 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1161 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1162 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1163 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1169 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1170 unsigned ImplicitRn) {
1171 const TargetInstrDesc &TID = MI.getDesc();
1172 unsigned Form = TID.TSFlags & ARMII::FormMask;
1173 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1175 // Part of binary is determined by TableGn.
1176 unsigned Binary = getBinaryCodeForInstr(MI);
1178 // Set the conditional execution predicate
1179 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1183 // Operand 0 of a pre- and post-indexed store is the address base
1184 // writeback. Skip it.
1185 bool Skipped = false;
1186 if (IsPrePost && Form == ARMII::StMiscFrm) {
1191 // Set first operand
1192 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1194 // Skip LDRD and STRD's second operand.
1195 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1198 // Set second operand
1200 // Special handling for implicit use (e.g. PC).
1201 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1203 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1205 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1206 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1209 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1210 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1211 ? 0 : MI.getOperand(OpIdx+1).getImm();
1213 // Set bit U(23) according to sign of immed value (positive or negative)
1214 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1217 // If this instr is in register offset/index encoding, set bit[3:0]
1218 // to the corresponding Rm register.
1220 Binary |= getARMRegisterNumbering(MO2.getReg());
1225 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1226 Binary |= 1 << ARMII::AM3_I_BitShift;
1227 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1229 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1230 Binary |= (ImmOffs & 0xF); // immedL
1236 static unsigned getAddrModeUPBits(unsigned Mode) {
1237 unsigned Binary = 0;
1239 // Set addressing mode by modifying bits U(23) and P(24)
1240 // IA - Increment after - bit U = 1 and bit P = 0
1241 // IB - Increment before - bit U = 1 and bit P = 1
1242 // DA - Decrement after - bit U = 0 and bit P = 0
1243 // DB - Decrement before - bit U = 0 and bit P = 1
1245 default: llvm_unreachable("Unknown addressing sub-mode!");
1246 case ARM_AM::da: break;
1247 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1248 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1249 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1255 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1256 const TargetInstrDesc &TID = MI.getDesc();
1257 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1259 // Part of binary is determined by TableGn.
1260 unsigned Binary = getBinaryCodeForInstr(MI);
1262 // Set the conditional execution predicate
1263 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1265 // Skip operand 0 of an instruction with base register update.
1270 // Set base address operand
1271 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1273 // Set addressing mode by modifying bits U(23) and P(24)
1274 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1275 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1279 Binary |= 0x1 << ARMII::W_BitShift;
1282 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1283 const MachineOperand &MO = MI.getOperand(i);
1284 if (!MO.isReg() || MO.isImplicit())
1286 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1287 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1289 Binary |= 0x1 << RegNum;
1295 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1296 const TargetInstrDesc &TID = MI.getDesc();
1298 // Part of binary is determined by TableGn.
1299 unsigned Binary = getBinaryCodeForInstr(MI);
1301 // Set the conditional execution predicate
1302 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1304 // Encode S bit if MI modifies CPSR.
1305 Binary |= getAddrModeSBit(MI, TID);
1307 // 32x32->64bit operations have two destination registers. The number
1308 // of register definitions will tell us if that's what we're dealing with.
1310 if (TID.getNumDefs() == 2)
1311 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1314 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1317 Binary |= getMachineOpValue(MI, OpIdx++);
1320 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1322 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1323 // it as Rn (for multiply, that's in the same offset as RdLo.
1324 if (TID.getNumOperands() > OpIdx &&
1325 !TID.OpInfo[OpIdx].isPredicate() &&
1326 !TID.OpInfo[OpIdx].isOptionalDef())
1327 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1332 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1333 const TargetInstrDesc &TID = MI.getDesc();
1335 // Part of binary is determined by TableGn.
1336 unsigned Binary = getBinaryCodeForInstr(MI);
1338 // Set the conditional execution predicate
1339 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1346 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1347 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1349 // Two register operand form.
1351 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1354 Binary |= getMachineOpValue(MI, MO2);
1357 Binary |= getMachineOpValue(MI, MO1);
1360 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1361 if (MI.getOperand(OpIdx).isImm() &&
1362 !TID.OpInfo[OpIdx].isPredicate() &&
1363 !TID.OpInfo[OpIdx].isOptionalDef())
1364 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1369 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1370 const TargetInstrDesc &TID = MI.getDesc();
1372 // Part of binary is determined by TableGn.
1373 unsigned Binary = getBinaryCodeForInstr(MI);
1375 // Set the conditional execution predicate
1376 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1378 // PKH instructions are finished at this point
1379 if (TID.Opcode == ARM::PKHBT || TID.Opcode == ARM::PKHTB) {
1387 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1389 const MachineOperand &MO = MI.getOperand(OpIdx++);
1390 if (OpIdx == TID.getNumOperands() ||
1391 TID.OpInfo[OpIdx].isPredicate() ||
1392 TID.OpInfo[OpIdx].isOptionalDef()) {
1393 // Encode Rm and it's done.
1394 Binary |= getMachineOpValue(MI, MO);
1400 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1403 Binary |= getMachineOpValue(MI, OpIdx++);
1405 // Encode shift_imm.
1406 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1407 if (TID.Opcode == ARM::PKHTB) {
1408 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1412 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1413 Binary |= ShiftAmt << ARMII::ShiftShift;
1418 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1419 const TargetInstrDesc &TID = MI.getDesc();
1421 // Part of binary is determined by TableGen.
1422 unsigned Binary = getBinaryCodeForInstr(MI);
1424 // Set the conditional execution predicate
1425 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1428 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1430 // Encode saturate bit position.
1431 unsigned Pos = MI.getOperand(1).getImm();
1432 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1434 assert((Pos < 16 || (Pos < 32 &&
1435 TID.Opcode != ARM::SSAT16 &&
1436 TID.Opcode != ARM::USAT16)) &&
1437 "saturate bit position out of range");
1438 Binary |= Pos << 16;
1441 Binary |= getMachineOpValue(MI, 2);
1443 // Encode shift_imm.
1444 if (TID.getNumOperands() == 4) {
1445 unsigned ShiftOp = MI.getOperand(3).getImm();
1446 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1447 if (Opc == ARM_AM::asr)
1449 unsigned ShiftAmt = MI.getOperand(3).getImm();
1450 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1452 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1453 Binary |= ShiftAmt << ARMII::ShiftShift;
1459 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1460 const TargetInstrDesc &TID = MI.getDesc();
1462 if (TID.Opcode == ARM::TPsoft) {
1463 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1466 // Part of binary is determined by TableGn.
1467 unsigned Binary = getBinaryCodeForInstr(MI);
1469 // Set the conditional execution predicate
1470 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1472 // Set signed_immed_24 field
1473 Binary |= getMachineOpValue(MI, 0);
1478 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1479 // Remember the base address of the inline jump table.
1480 uintptr_t JTBase = MCE.getCurrentPCValue();
1481 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1482 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1485 // Now emit the jump table entries.
1486 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1487 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1489 // DestBB address - JT base.
1490 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1492 // Absolute DestBB address.
1493 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1498 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1499 const TargetInstrDesc &TID = MI.getDesc();
1501 // Handle jump tables.
1502 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1503 // First emit a ldr pc, [] instruction.
1504 emitDataProcessingInstruction(MI, ARM::PC);
1506 // Then emit the inline jump table.
1508 (TID.Opcode == ARM::BR_JTr)
1509 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1510 emitInlineJumpTable(JTIndex);
1512 } else if (TID.Opcode == ARM::BR_JTm) {
1513 // First emit a ldr pc, [] instruction.
1514 emitLoadStoreInstruction(MI, ARM::PC);
1516 // Then emit the inline jump table.
1517 emitInlineJumpTable(MI.getOperand(3).getIndex());
1521 // Part of binary is determined by TableGn.
1522 unsigned Binary = getBinaryCodeForInstr(MI);
1524 // Set the conditional execution predicate
1525 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1527 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1528 // The return register is LR.
1529 Binary |= getARMRegisterNumbering(ARM::LR);
1531 // otherwise, set the return register
1532 Binary |= getMachineOpValue(MI, 0);
1537 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1538 unsigned RegD = MI.getOperand(OpIdx).getReg();
1539 unsigned Binary = 0;
1540 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1541 RegD = getARMRegisterNumbering(RegD);
1543 Binary |= RegD << ARMII::RegRdShift;
1545 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1546 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1551 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1552 unsigned RegN = MI.getOperand(OpIdx).getReg();
1553 unsigned Binary = 0;
1554 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1555 RegN = getARMRegisterNumbering(RegN);
1557 Binary |= RegN << ARMII::RegRnShift;
1559 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1560 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1565 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1566 unsigned RegM = MI.getOperand(OpIdx).getReg();
1567 unsigned Binary = 0;
1568 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1569 RegM = getARMRegisterNumbering(RegM);
1573 Binary |= ((RegM & 0x1E) >> 1);
1574 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1579 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1580 const TargetInstrDesc &TID = MI.getDesc();
1582 // Part of binary is determined by TableGn.
1583 unsigned Binary = getBinaryCodeForInstr(MI);
1585 // Set the conditional execution predicate
1586 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1589 assert((Binary & ARMII::D_BitShift) == 0 &&
1590 (Binary & ARMII::N_BitShift) == 0 &&
1591 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1594 Binary |= encodeVFPRd(MI, OpIdx++);
1596 // If this is a two-address operand, skip it, e.g. FMACD.
1597 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1601 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1602 Binary |= encodeVFPRn(MI, OpIdx++);
1604 if (OpIdx == TID.getNumOperands() ||
1605 TID.OpInfo[OpIdx].isPredicate() ||
1606 TID.OpInfo[OpIdx].isOptionalDef()) {
1607 // FCMPEZD etc. has only one operand.
1613 Binary |= encodeVFPRm(MI, OpIdx);
1618 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1619 const TargetInstrDesc &TID = MI.getDesc();
1620 unsigned Form = TID.TSFlags & ARMII::FormMask;
1622 // Part of binary is determined by TableGn.
1623 unsigned Binary = getBinaryCodeForInstr(MI);
1625 // Set the conditional execution predicate
1626 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1630 case ARMII::VFPConv1Frm:
1631 case ARMII::VFPConv2Frm:
1632 case ARMII::VFPConv3Frm:
1634 Binary |= encodeVFPRd(MI, 0);
1636 case ARMII::VFPConv4Frm:
1638 Binary |= encodeVFPRn(MI, 0);
1640 case ARMII::VFPConv5Frm:
1642 Binary |= encodeVFPRm(MI, 0);
1648 case ARMII::VFPConv1Frm:
1650 Binary |= encodeVFPRm(MI, 1);
1652 case ARMII::VFPConv2Frm:
1653 case ARMII::VFPConv3Frm:
1655 Binary |= encodeVFPRn(MI, 1);
1657 case ARMII::VFPConv4Frm:
1658 case ARMII::VFPConv5Frm:
1660 Binary |= encodeVFPRd(MI, 1);
1664 if (Form == ARMII::VFPConv5Frm)
1666 Binary |= encodeVFPRn(MI, 2);
1667 else if (Form == ARMII::VFPConv3Frm)
1669 Binary |= encodeVFPRm(MI, 2);
1674 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1675 // Part of binary is determined by TableGn.
1676 unsigned Binary = getBinaryCodeForInstr(MI);
1678 // Set the conditional execution predicate
1679 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1684 Binary |= encodeVFPRd(MI, OpIdx++);
1686 // Encode address base.
1687 const MachineOperand &Base = MI.getOperand(OpIdx++);
1688 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1690 // If there is a non-zero immediate offset, encode it.
1692 const MachineOperand &Offset = MI.getOperand(OpIdx);
1693 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1694 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1695 Binary |= 1 << ARMII::U_BitShift;
1702 // If immediate offset is omitted, default to +0.
1703 Binary |= 1 << ARMII::U_BitShift;
1709 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1710 const TargetInstrDesc &TID = MI.getDesc();
1711 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1713 // Part of binary is determined by TableGn.
1714 unsigned Binary = getBinaryCodeForInstr(MI);
1716 // Set the conditional execution predicate
1717 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1719 // Skip operand 0 of an instruction with base register update.
1724 // Set base address operand
1725 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1727 // Set addressing mode by modifying bits U(23) and P(24)
1728 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1729 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1733 Binary |= 0x1 << ARMII::W_BitShift;
1735 // First register is encoded in Dd.
1736 Binary |= encodeVFPRd(MI, OpIdx+2);
1738 // Count the number of registers.
1739 unsigned NumRegs = 1;
1740 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1741 const MachineOperand &MO = MI.getOperand(i);
1742 if (!MO.isReg() || MO.isImplicit())
1746 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1747 // Otherwise, it will be 0, in the case of 32-bit registers.
1749 Binary |= NumRegs * 2;
1756 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1757 unsigned RegD = MI.getOperand(OpIdx).getReg();
1758 unsigned Binary = 0;
1759 RegD = getARMRegisterNumbering(RegD);
1760 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1761 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1765 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1766 unsigned RegN = MI.getOperand(OpIdx).getReg();
1767 unsigned Binary = 0;
1768 RegN = getARMRegisterNumbering(RegN);
1769 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1770 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1774 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1775 unsigned RegM = MI.getOperand(OpIdx).getReg();
1776 unsigned Binary = 0;
1777 RegM = getARMRegisterNumbering(RegM);
1778 Binary |= (RegM & 0xf);
1779 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1783 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1784 /// data-processing instruction to the corresponding Thumb encoding.
1785 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1786 assert((Binary & 0xfe000000) == 0xf2000000 &&
1787 "not an ARM NEON data-processing instruction");
1788 unsigned UBit = (Binary >> 24) & 1;
1789 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1792 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1793 unsigned Binary = getBinaryCodeForInstr(MI);
1795 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1796 const TargetInstrDesc &TID = MI.getDesc();
1797 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1801 } else { // ARMII::NSetLnFrm
1807 // Set the conditional execution predicate
1808 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1810 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1811 RegT = getARMRegisterNumbering(RegT);
1812 Binary |= (RegT << ARMII::RegRdShift);
1813 Binary |= encodeNEONRn(MI, RegNOpIdx);
1816 if ((Binary & (1 << 22)) != 0)
1817 LaneShift = 0; // 8-bit elements
1818 else if ((Binary & (1 << 5)) != 0)
1819 LaneShift = 1; // 16-bit elements
1821 LaneShift = 2; // 32-bit elements
1823 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1824 unsigned Opc1 = Lane >> 2;
1825 unsigned Opc2 = Lane & 3;
1826 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1827 Binary |= (Opc1 << 21);
1828 Binary |= (Opc2 << 5);
1833 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1834 unsigned Binary = getBinaryCodeForInstr(MI);
1836 // Set the conditional execution predicate
1837 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1839 unsigned RegT = MI.getOperand(1).getReg();
1840 RegT = getARMRegisterNumbering(RegT);
1841 Binary |= (RegT << ARMII::RegRdShift);
1842 Binary |= encodeNEONRn(MI, 0);
1846 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1847 unsigned Binary = getBinaryCodeForInstr(MI);
1848 // Destination register is encoded in Dd.
1849 Binary |= encodeNEONRd(MI, 0);
1850 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1851 unsigned Imm = MI.getOperand(1).getImm();
1852 unsigned Op = (Imm >> 12) & 1;
1853 unsigned Cmode = (Imm >> 8) & 0xf;
1854 unsigned I = (Imm >> 7) & 1;
1855 unsigned Imm3 = (Imm >> 4) & 0x7;
1856 unsigned Imm4 = Imm & 0xf;
1857 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1859 Binary = convertNEONDataProcToThumb(Binary);
1863 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1864 const TargetInstrDesc &TID = MI.getDesc();
1865 unsigned Binary = getBinaryCodeForInstr(MI);
1866 // Destination register is encoded in Dd; source register in Dm.
1868 Binary |= encodeNEONRd(MI, OpIdx++);
1869 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1871 Binary |= encodeNEONRm(MI, OpIdx);
1873 Binary = convertNEONDataProcToThumb(Binary);
1874 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1878 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1879 const TargetInstrDesc &TID = MI.getDesc();
1880 unsigned Binary = getBinaryCodeForInstr(MI);
1881 // Destination register is encoded in Dd; source registers in Dn and Dm.
1883 Binary |= encodeNEONRd(MI, OpIdx++);
1884 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1886 Binary |= encodeNEONRn(MI, OpIdx++);
1887 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1889 Binary |= encodeNEONRm(MI, OpIdx);
1891 Binary = convertNEONDataProcToThumb(Binary);
1892 // FIXME: This does not handle VMOVDneon or VMOVQ.
1896 #include "ARMGenCodeEmitter.inc"