1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitMiscInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
155 return getMachineOpValue(MI, MI.getOperand(OpIdx));
158 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
159 /// machine operand requires relocation, record the relocation and return
161 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166 unsigned getShiftOp(unsigned Imm) const ;
168 /// Routines that handle operands which add machine relocations which are
169 /// fixed up by the relocation stage.
170 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
171 bool MayNeedFarStub, bool Indirect,
173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177 intptr_t JTBase = 0);
181 char ARMCodeEmitter::ID = 0;
183 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
184 /// code to the specified MCE object.
185 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
186 JITCodeEmitter &JCE) {
187 return new ARMCodeEmitter(TM, JCE);
190 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
191 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
192 MF.getTarget().getRelocationModel() != Reloc::Static) &&
193 "JIT relocation model must be set to static or default!");
194 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
195 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
196 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
197 Subtarget = &TM.getSubtarget<ARMSubtarget>();
198 MCPEs = &MF.getConstantPool()->getConstants();
200 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
203 JTI->Initialize(MF, IsPIC);
204 MMI = &getAnalysis<MachineModuleInfo>();
205 MCE.setModuleInfo(MMI);
208 DEBUG(errs() << "JITTing function '"
209 << MF.getFunction()->getName() << "'\n");
210 MCE.startFunction(MF);
211 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
213 MCE.StartMachineBasicBlock(MBB);
214 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
218 } while (MCE.finishFunction(MF));
223 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
225 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
226 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
227 default: llvm_unreachable("Unknown shift opc!");
228 case ARM_AM::asr: return 2;
229 case ARM_AM::lsl: return 0;
230 case ARM_AM::lsr: return 1;
232 case ARM_AM::rrx: return 3;
237 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
238 /// machine operand requires relocation, record the relocation and return zero.
239 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
240 const MachineOperand &MO,
242 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
243 && "Relocation to this function should be for movt or movw");
246 return static_cast<unsigned>(MO.getImm());
247 else if (MO.isGlobal())
248 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
249 else if (MO.isSymbol())
250 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
252 emitMachineBasicBlock(MO.getMBB(), Reloc);
257 llvm_unreachable("Unsupported operand type for movw/movt");
262 /// getMachineOpValue - Return binary encoding of operand. If the machine
263 /// operand requires relocation, record the relocation and return zero.
264 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
265 const MachineOperand &MO) {
267 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
269 return static_cast<unsigned>(MO.getImm());
270 else if (MO.isGlobal())
271 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
272 else if (MO.isSymbol())
273 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
274 else if (MO.isCPI()) {
275 const TargetInstrDesc &TID = MI.getDesc();
276 // For VFP load, the immediate offset is multiplied by 4.
277 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
278 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
279 emitConstPoolAddress(MO.getIndex(), Reloc);
280 } else if (MO.isJTI())
281 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
283 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
293 /// emitGlobalAddress - Emit the specified address to the code stream.
295 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
296 bool MayNeedFarStub, bool Indirect,
298 MachineRelocation MR = Indirect
299 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
300 const_cast<GlobalValue *>(GV),
301 ACPV, MayNeedFarStub)
302 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
303 const_cast<GlobalValue *>(GV), ACPV,
305 MCE.addRelocation(MR);
308 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
309 /// be emitted to the current location in the function, and allow it to be PC
311 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
312 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
316 /// emitConstPoolAddress - Arrange for the address of an constant pool
317 /// to be emitted to the current location in the function, and allow it to be PC
319 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
320 // Tell JIT emitter we'll resolve the address.
321 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
322 Reloc, CPI, 0, true));
325 /// emitJumpTableAddress - Arrange for the address of a jump table to
326 /// be emitted to the current location in the function, and allow it to be PC
328 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
329 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
330 Reloc, JTIndex, 0, true));
333 /// emitMachineBasicBlock - Emit the specified address basic block.
334 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
335 unsigned Reloc, intptr_t JTBase) {
336 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
340 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
341 DEBUG(errs() << " 0x";
342 errs().write_hex(Binary) << "\n");
343 MCE.emitWordLE(Binary);
346 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
347 DEBUG(errs() << " 0x";
348 errs().write_hex(Binary) << "\n");
349 MCE.emitDWordLE(Binary);
352 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
353 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
355 MCE.processDebugLoc(MI.getDebugLoc(), true);
357 ++NumEmitted; // Keep track of the # of mi's emitted
358 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
360 llvm_unreachable("Unhandled instruction encoding format!");
364 emitPseudoInstruction(MI);
367 case ARMII::DPSoRegFrm:
368 emitDataProcessingInstruction(MI);
372 emitLoadStoreInstruction(MI);
374 case ARMII::LdMiscFrm:
375 case ARMII::StMiscFrm:
376 emitMiscLoadStoreInstruction(MI);
378 case ARMII::LdStMulFrm:
379 emitLoadStoreMultipleInstruction(MI);
382 emitMulFrmInstruction(MI);
385 emitExtendInstruction(MI);
387 case ARMII::ArithMiscFrm:
388 emitMiscArithInstruction(MI);
391 emitSaturateInstruction(MI);
394 emitBranchInstruction(MI);
396 case ARMII::BrMiscFrm:
397 emitMiscBranchInstruction(MI);
400 case ARMII::VFPUnaryFrm:
401 case ARMII::VFPBinaryFrm:
402 emitVFPArithInstruction(MI);
404 case ARMII::VFPConv1Frm:
405 case ARMII::VFPConv2Frm:
406 case ARMII::VFPConv3Frm:
407 case ARMII::VFPConv4Frm:
408 case ARMII::VFPConv5Frm:
409 emitVFPConversionInstruction(MI);
411 case ARMII::VFPLdStFrm:
412 emitVFPLoadStoreInstruction(MI);
414 case ARMII::VFPLdStMulFrm:
415 emitVFPLoadStoreMultipleInstruction(MI);
417 case ARMII::VFPMiscFrm:
418 emitMiscInstruction(MI);
420 // NEON instructions.
421 case ARMII::NGetLnFrm:
422 case ARMII::NSetLnFrm:
423 emitNEONLaneInstruction(MI);
426 emitNEONDupInstruction(MI);
428 case ARMII::N1RegModImmFrm:
429 emitNEON1RegModImmInstruction(MI);
431 case ARMII::N2RegFrm:
432 emitNEON2RegInstruction(MI);
434 case ARMII::N3RegFrm:
435 emitNEON3RegInstruction(MI);
438 MCE.processDebugLoc(MI.getDebugLoc(), false);
441 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
442 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
443 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
444 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
446 // Remember the CONSTPOOL_ENTRY address for later relocation.
447 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
449 // Emit constpool island entry. In most cases, the actual values will be
450 // resolved and relocated after code emission.
451 if (MCPE.isMachineConstantPoolEntry()) {
452 ARMConstantPoolValue *ACPV =
453 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
455 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
456 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
458 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
459 const GlobalValue *GV = ACPV->getGV();
461 Reloc::Model RelocM = TM.getRelocationModel();
462 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
464 Subtarget->GVIsIndirectSymbol(GV, RelocM),
467 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
471 const Constant *CV = MCPE.Val.ConstVal;
474 errs() << " ** Constant pool #" << CPI << " @ "
475 << (void*)MCE.getCurrentPCValue() << " ";
476 if (const Function *F = dyn_cast<Function>(CV))
477 errs() << F->getName();
483 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
484 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
486 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
487 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
489 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
490 if (CFP->getType()->isFloatTy())
491 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
492 else if (CFP->getType()->isDoubleTy())
493 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
495 llvm_unreachable("Unable to handle this constantpool entry!");
498 llvm_unreachable("Unable to handle this constantpool entry!");
503 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
504 const MachineOperand &MO0 = MI.getOperand(0);
505 const MachineOperand &MO1 = MI.getOperand(1);
507 // Emit the 'movw' instruction.
508 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
510 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
512 // Set the conditional execution predicate.
513 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
516 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
518 // Encode imm16 as imm4:imm12
519 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
520 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
523 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
524 // Emit the 'movt' instruction.
525 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
527 // Set the conditional execution predicate.
528 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
531 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
533 // Encode imm16 as imm4:imm1, same as movw above.
534 Binary |= Hi16 & 0xFFF;
535 Binary |= ((Hi16 >> 12) & 0xF) << 16;
539 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
540 const MachineOperand &MO0 = MI.getOperand(0);
541 const MachineOperand &MO1 = MI.getOperand(1);
542 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
543 "Not a valid so_imm value!");
544 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
545 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
547 // Emit the 'mov' instruction.
548 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
550 // Set the conditional execution predicate.
551 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
554 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
557 // Set bit I(25) to identify this is the immediate form of <shifter_op>
558 Binary |= 1 << ARMII::I_BitShift;
559 Binary |= getMachineSoImmOpValue(V1);
562 // Now the 'orr' instruction.
563 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
565 // Set the conditional execution predicate.
566 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
569 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
572 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
575 // Set bit I(25) to identify this is the immediate form of <shifter_op>
576 Binary |= 1 << ARMII::I_BitShift;
577 Binary |= getMachineSoImmOpValue(V2);
581 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
582 // It's basically add r, pc, (LJTI - $+8)
584 const TargetInstrDesc &TID = MI.getDesc();
586 // Emit the 'add' instruction.
587 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
589 // Set the conditional execution predicate
590 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
592 // Encode S bit if MI modifies CPSR.
593 Binary |= getAddrModeSBit(MI, TID);
596 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
598 // Encode Rn which is PC.
599 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
601 // Encode the displacement.
602 Binary |= 1 << ARMII::I_BitShift;
603 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
608 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
609 unsigned Opcode = MI.getDesc().Opcode;
611 // Part of binary is determined by TableGn.
612 unsigned Binary = getBinaryCodeForInstr(MI);
614 // Set the conditional execution predicate
615 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
617 // Encode S bit if MI modifies CPSR.
618 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
619 Binary |= 1 << ARMII::S_BitShift;
621 // Encode register def if there is one.
622 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
624 // Encode the shift operation.
631 case ARM::MOVsrl_flag:
633 Binary |= (0x2 << 4) | (1 << 7);
635 case ARM::MOVsra_flag:
637 Binary |= (0x4 << 4) | (1 << 7);
641 // Encode register Rm.
642 Binary |= getMachineOpValue(MI, 1);
647 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
648 DEBUG(errs() << " ** LPC" << LabelID << " @ "
649 << (void*)MCE.getCurrentPCValue() << '\n');
650 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
653 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
654 unsigned Opcode = MI.getDesc().Opcode;
657 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
661 case ARM::BMOVPCRXr9: {
662 // First emit mov lr, pc
663 unsigned Binary = 0x01a0e00f;
664 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
667 // and then emit the branch.
668 emitMiscBranchInstruction(MI);
671 case TargetOpcode::INLINEASM: {
672 // We allow inline assembler nodes with empty bodies - they can
673 // implicitly define registers, which is ok for JIT.
674 if (MI.getOperand(0).getSymbolName()[0]) {
675 report_fatal_error("JIT does not support inline asm!");
679 case TargetOpcode::PROLOG_LABEL:
680 case TargetOpcode::EH_LABEL:
681 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
683 case TargetOpcode::IMPLICIT_DEF:
684 case TargetOpcode::KILL:
687 case ARM::CONSTPOOL_ENTRY:
688 emitConstPoolInstruction(MI);
691 // Remember of the address of the PC label for relocation later.
692 addPCLabel(MI.getOperand(2).getImm());
693 // PICADD is just an add instruction that implicitly read pc.
694 emitDataProcessingInstruction(MI, 0, ARM::PC);
701 // Remember of the address of the PC label for relocation later.
702 addPCLabel(MI.getOperand(2).getImm());
703 // These are just load / store instructions that implicitly read pc.
704 emitLoadStoreInstruction(MI, 0, ARM::PC);
711 // Remember of the address of the PC label for relocation later.
712 addPCLabel(MI.getOperand(2).getImm());
713 // These are just load / store instructions that implicitly read pc.
714 emitMiscLoadStoreInstruction(MI, ARM::PC);
719 emitMOVi32immInstruction(MI);
722 case ARM::MOVi2pieces:
723 // Two instructions to materialize a constant.
724 emitMOVi2piecesInstruction(MI);
726 case ARM::LEApcrelJT:
727 // Materialize jumptable address.
728 emitLEApcrelJTInstruction(MI);
731 case ARM::MOVsrl_flag:
732 case ARM::MOVsra_flag:
733 emitPseudoMoveInstruction(MI);
738 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
739 const TargetInstrDesc &TID,
740 const MachineOperand &MO,
742 unsigned Binary = getMachineOpValue(MI, MO);
744 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
745 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
746 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
748 // Encode the shift opcode.
750 unsigned Rs = MO1.getReg();
752 // Set shift operand (bit[7:4]).
757 // RRX - 0110 and bit[11:8] clear.
759 default: llvm_unreachable("Unknown shift opc!");
760 case ARM_AM::lsl: SBits = 0x1; break;
761 case ARM_AM::lsr: SBits = 0x3; break;
762 case ARM_AM::asr: SBits = 0x5; break;
763 case ARM_AM::ror: SBits = 0x7; break;
764 case ARM_AM::rrx: SBits = 0x6; break;
767 // Set shift operand (bit[6:4]).
773 default: llvm_unreachable("Unknown shift opc!");
774 case ARM_AM::lsl: SBits = 0x0; break;
775 case ARM_AM::lsr: SBits = 0x2; break;
776 case ARM_AM::asr: SBits = 0x4; break;
777 case ARM_AM::ror: SBits = 0x6; break;
780 Binary |= SBits << 4;
781 if (SOpc == ARM_AM::rrx)
784 // Encode the shift operation Rs or shift_imm (except rrx).
786 // Encode Rs bit[11:8].
787 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
789 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
792 // Encode shift_imm bit[11:7].
793 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
796 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
797 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
798 assert(SoImmVal != -1 && "Not a valid so_imm value!");
800 // Encode rotate_imm.
801 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
802 << ARMII::SoRotImmShift;
805 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
809 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
810 const TargetInstrDesc &TID) const {
811 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
812 const MachineOperand &MO = MI.getOperand(i-1);
813 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
814 return 1 << ARMII::S_BitShift;
819 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
821 unsigned ImplicitRn) {
822 const TargetInstrDesc &TID = MI.getDesc();
824 // Part of binary is determined by TableGn.
825 unsigned Binary = getBinaryCodeForInstr(MI);
827 // Set the conditional execution predicate
828 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
830 // Encode S bit if MI modifies CPSR.
831 Binary |= getAddrModeSBit(MI, TID);
833 // Encode register def if there is one.
834 unsigned NumDefs = TID.getNumDefs();
837 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
839 // Special handling for implicit use (e.g. PC).
840 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
841 << ARMII::RegRdShift);
843 if (TID.Opcode == ARM::MOVi16) {
844 // Get immediate from MI.
845 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
846 ARM::reloc_arm_movw);
847 // Encode imm which is the same as in emitMOVi32immInstruction().
848 Binary |= Lo16 & 0xFFF;
849 Binary |= ((Lo16 >> 12) & 0xF) << 16;
852 } else if(TID.Opcode == ARM::MOVTi16) {
853 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
854 ARM::reloc_arm_movt) >> 16);
855 Binary |= Hi16 & 0xFFF;
856 Binary |= ((Hi16 >> 12) & 0xF) << 16;
859 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
860 uint32_t v = ~MI.getOperand(2).getImm();
861 int32_t lsb = CountTrailingZeros_32(v);
862 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
863 // Instr{20-16} = msb, Instr{11-7} = lsb
864 Binary |= (msb & 0x1F) << 16;
865 Binary |= (lsb & 0x1F) << 7;
868 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
869 // Encode Rn in Instr{0-3}
870 Binary |= getMachineOpValue(MI, OpIdx++);
872 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
873 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
875 // Instr{20-16} = widthm1, Instr{11-7} = lsb
876 Binary |= (widthm1 & 0x1F) << 16;
877 Binary |= (lsb & 0x1F) << 7;
882 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
883 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
886 // Encode first non-shifter register operand if there is one.
887 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
890 // Special handling for implicit use (e.g. PC).
891 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
892 << ARMII::RegRnShift);
894 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
899 // Encode shifter operand.
900 const MachineOperand &MO = MI.getOperand(OpIdx);
901 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
903 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
908 // Encode register Rm.
909 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
914 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
919 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
921 unsigned ImplicitRn) {
922 const TargetInstrDesc &TID = MI.getDesc();
923 unsigned Form = TID.TSFlags & ARMII::FormMask;
924 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
926 // Part of binary is determined by TableGn.
927 unsigned Binary = getBinaryCodeForInstr(MI);
929 // Set the conditional execution predicate
930 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
934 // Operand 0 of a pre- and post-indexed store is the address base
935 // writeback. Skip it.
936 bool Skipped = false;
937 if (IsPrePost && Form == ARMII::StFrm) {
944 // Special handling for implicit use (e.g. PC).
945 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
946 << ARMII::RegRdShift);
948 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
950 // Set second operand
952 // Special handling for implicit use (e.g. PC).
953 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
954 << ARMII::RegRnShift);
956 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
958 // If this is a two-address operand, skip it. e.g. LDR_PRE.
959 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
962 const MachineOperand &MO2 = MI.getOperand(OpIdx);
963 unsigned AM2Opc = (ImplicitRn == ARM::PC)
964 ? 0 : MI.getOperand(OpIdx+1).getImm();
966 // Set bit U(23) according to sign of immed value (positive or negative).
967 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
969 if (!MO2.getReg()) { // is immediate
970 if (ARM_AM::getAM2Offset(AM2Opc))
971 // Set the value of offset_12 field
972 Binary |= ARM_AM::getAM2Offset(AM2Opc);
977 // Set bit I(25), because this is not in immediate enconding.
978 Binary |= 1 << ARMII::I_BitShift;
979 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
980 // Set bit[3:0] to the corresponding Rm register
981 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
983 // If this instr is in scaled register offset/index instruction, set
984 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
985 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
986 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
987 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
993 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
994 unsigned ImplicitRn) {
995 const TargetInstrDesc &TID = MI.getDesc();
996 unsigned Form = TID.TSFlags & ARMII::FormMask;
997 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
999 // Part of binary is determined by TableGn.
1000 unsigned Binary = getBinaryCodeForInstr(MI);
1002 // Set the conditional execution predicate
1003 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1007 // Operand 0 of a pre- and post-indexed store is the address base
1008 // writeback. Skip it.
1009 bool Skipped = false;
1010 if (IsPrePost && Form == ARMII::StMiscFrm) {
1015 // Set first operand
1016 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1018 // Skip LDRD and STRD's second operand.
1019 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1022 // Set second operand
1024 // Special handling for implicit use (e.g. PC).
1025 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1026 << ARMII::RegRnShift);
1028 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1030 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1031 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1034 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1035 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1036 ? 0 : MI.getOperand(OpIdx+1).getImm();
1038 // Set bit U(23) according to sign of immed value (positive or negative)
1039 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1042 // If this instr is in register offset/index encoding, set bit[3:0]
1043 // to the corresponding Rm register.
1045 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1050 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1051 Binary |= 1 << ARMII::AM3_I_BitShift;
1052 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1054 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1055 Binary |= (ImmOffs & 0xF); // immedL
1061 static unsigned getAddrModeUPBits(unsigned Mode) {
1062 unsigned Binary = 0;
1064 // Set addressing mode by modifying bits U(23) and P(24)
1065 // IA - Increment after - bit U = 1 and bit P = 0
1066 // IB - Increment before - bit U = 1 and bit P = 1
1067 // DA - Decrement after - bit U = 0 and bit P = 0
1068 // DB - Decrement before - bit U = 0 and bit P = 1
1070 default: llvm_unreachable("Unknown addressing sub-mode!");
1071 case ARM_AM::da: break;
1072 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1073 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1074 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1080 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1081 const TargetInstrDesc &TID = MI.getDesc();
1082 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1084 // Part of binary is determined by TableGn.
1085 unsigned Binary = getBinaryCodeForInstr(MI);
1087 // Set the conditional execution predicate
1088 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1090 // Skip operand 0 of an instruction with base register update.
1095 // Set base address operand
1096 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1098 // Set addressing mode by modifying bits U(23) and P(24)
1099 const MachineOperand &MO = MI.getOperand(OpIdx++);
1100 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1104 Binary |= 0x1 << ARMII::W_BitShift;
1107 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1108 const MachineOperand &MO = MI.getOperand(i);
1109 if (!MO.isReg() || MO.isImplicit())
1111 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1112 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1114 Binary |= 0x1 << RegNum;
1120 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1121 const TargetInstrDesc &TID = MI.getDesc();
1123 // Part of binary is determined by TableGn.
1124 unsigned Binary = getBinaryCodeForInstr(MI);
1126 // Set the conditional execution predicate
1127 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1129 // Encode S bit if MI modifies CPSR.
1130 Binary |= getAddrModeSBit(MI, TID);
1132 // 32x32->64bit operations have two destination registers. The number
1133 // of register definitions will tell us if that's what we're dealing with.
1135 if (TID.getNumDefs() == 2)
1136 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1139 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1142 Binary |= getMachineOpValue(MI, OpIdx++);
1145 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1147 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1148 // it as Rn (for multiply, that's in the same offset as RdLo.
1149 if (TID.getNumOperands() > OpIdx &&
1150 !TID.OpInfo[OpIdx].isPredicate() &&
1151 !TID.OpInfo[OpIdx].isOptionalDef())
1152 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1157 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1158 const TargetInstrDesc &TID = MI.getDesc();
1160 // Part of binary is determined by TableGn.
1161 unsigned Binary = getBinaryCodeForInstr(MI);
1163 // Set the conditional execution predicate
1164 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1169 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1171 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1172 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1174 // Two register operand form.
1176 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1179 Binary |= getMachineOpValue(MI, MO2);
1182 Binary |= getMachineOpValue(MI, MO1);
1185 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1186 if (MI.getOperand(OpIdx).isImm() &&
1187 !TID.OpInfo[OpIdx].isPredicate() &&
1188 !TID.OpInfo[OpIdx].isOptionalDef())
1189 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1194 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1195 const TargetInstrDesc &TID = MI.getDesc();
1197 // Part of binary is determined by TableGn.
1198 unsigned Binary = getBinaryCodeForInstr(MI);
1200 // Set the conditional execution predicate
1201 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1206 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1208 const MachineOperand &MO = MI.getOperand(OpIdx++);
1209 if (OpIdx == TID.getNumOperands() ||
1210 TID.OpInfo[OpIdx].isPredicate() ||
1211 TID.OpInfo[OpIdx].isOptionalDef()) {
1212 // Encode Rm and it's done.
1213 Binary |= getMachineOpValue(MI, MO);
1219 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1222 Binary |= getMachineOpValue(MI, OpIdx++);
1224 // Encode shift_imm.
1225 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1226 if (TID.Opcode == ARM::PKHTB) {
1227 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1231 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1232 Binary |= ShiftAmt << ARMII::ShiftShift;
1237 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1238 const TargetInstrDesc &TID = MI.getDesc();
1240 // Part of binary is determined by TableGen.
1241 unsigned Binary = getBinaryCodeForInstr(MI);
1243 // Set the conditional execution predicate
1244 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1247 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1249 // Encode saturate bit position.
1250 unsigned Pos = MI.getOperand(1).getImm();
1251 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1253 assert((Pos < 16 || (Pos < 32 &&
1254 TID.Opcode != ARM::SSAT16 &&
1255 TID.Opcode != ARM::USAT16)) &&
1256 "saturate bit position out of range");
1257 Binary |= Pos << 16;
1260 Binary |= getMachineOpValue(MI, 2);
1262 // Encode shift_imm.
1263 if (TID.getNumOperands() == 4) {
1264 unsigned ShiftOp = MI.getOperand(3).getImm();
1265 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1266 if (Opc == ARM_AM::asr)
1268 unsigned ShiftAmt = MI.getOperand(3).getImm();
1269 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1271 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1272 Binary |= ShiftAmt << ARMII::ShiftShift;
1278 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1279 const TargetInstrDesc &TID = MI.getDesc();
1281 if (TID.Opcode == ARM::TPsoft) {
1282 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1285 // Part of binary is determined by TableGn.
1286 unsigned Binary = getBinaryCodeForInstr(MI);
1288 // Set the conditional execution predicate
1289 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1291 // Set signed_immed_24 field
1292 Binary |= getMachineOpValue(MI, 0);
1297 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1298 // Remember the base address of the inline jump table.
1299 uintptr_t JTBase = MCE.getCurrentPCValue();
1300 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1301 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1304 // Now emit the jump table entries.
1305 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1306 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1308 // DestBB address - JT base.
1309 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1311 // Absolute DestBB address.
1312 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1317 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1318 const TargetInstrDesc &TID = MI.getDesc();
1320 // Handle jump tables.
1321 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1322 // First emit a ldr pc, [] instruction.
1323 emitDataProcessingInstruction(MI, ARM::PC);
1325 // Then emit the inline jump table.
1327 (TID.Opcode == ARM::BR_JTr)
1328 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1329 emitInlineJumpTable(JTIndex);
1331 } else if (TID.Opcode == ARM::BR_JTm) {
1332 // First emit a ldr pc, [] instruction.
1333 emitLoadStoreInstruction(MI, ARM::PC);
1335 // Then emit the inline jump table.
1336 emitInlineJumpTable(MI.getOperand(3).getIndex());
1340 // Part of binary is determined by TableGn.
1341 unsigned Binary = getBinaryCodeForInstr(MI);
1343 // Set the conditional execution predicate
1344 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1346 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1347 // The return register is LR.
1348 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1350 // otherwise, set the return register
1351 Binary |= getMachineOpValue(MI, 0);
1356 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1357 unsigned RegD = MI.getOperand(OpIdx).getReg();
1358 unsigned Binary = 0;
1359 bool isSPVFP = false;
1360 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1362 Binary |= RegD << ARMII::RegRdShift;
1364 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1365 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1370 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1371 unsigned RegN = MI.getOperand(OpIdx).getReg();
1372 unsigned Binary = 0;
1373 bool isSPVFP = false;
1374 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1376 Binary |= RegN << ARMII::RegRnShift;
1378 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1379 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1384 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1385 unsigned RegM = MI.getOperand(OpIdx).getReg();
1386 unsigned Binary = 0;
1387 bool isSPVFP = false;
1388 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1392 Binary |= ((RegM & 0x1E) >> 1);
1393 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1398 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1399 const TargetInstrDesc &TID = MI.getDesc();
1401 // Part of binary is determined by TableGn.
1402 unsigned Binary = getBinaryCodeForInstr(MI);
1404 // Set the conditional execution predicate
1405 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1408 assert((Binary & ARMII::D_BitShift) == 0 &&
1409 (Binary & ARMII::N_BitShift) == 0 &&
1410 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1413 Binary |= encodeVFPRd(MI, OpIdx++);
1415 // If this is a two-address operand, skip it, e.g. FMACD.
1416 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1420 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1421 Binary |= encodeVFPRn(MI, OpIdx++);
1423 if (OpIdx == TID.getNumOperands() ||
1424 TID.OpInfo[OpIdx].isPredicate() ||
1425 TID.OpInfo[OpIdx].isOptionalDef()) {
1426 // FCMPEZD etc. has only one operand.
1432 Binary |= encodeVFPRm(MI, OpIdx);
1437 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1438 const TargetInstrDesc &TID = MI.getDesc();
1439 unsigned Form = TID.TSFlags & ARMII::FormMask;
1441 // Part of binary is determined by TableGn.
1442 unsigned Binary = getBinaryCodeForInstr(MI);
1444 // Set the conditional execution predicate
1445 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1449 case ARMII::VFPConv1Frm:
1450 case ARMII::VFPConv2Frm:
1451 case ARMII::VFPConv3Frm:
1453 Binary |= encodeVFPRd(MI, 0);
1455 case ARMII::VFPConv4Frm:
1457 Binary |= encodeVFPRn(MI, 0);
1459 case ARMII::VFPConv5Frm:
1461 Binary |= encodeVFPRm(MI, 0);
1467 case ARMII::VFPConv1Frm:
1469 Binary |= encodeVFPRm(MI, 1);
1471 case ARMII::VFPConv2Frm:
1472 case ARMII::VFPConv3Frm:
1474 Binary |= encodeVFPRn(MI, 1);
1476 case ARMII::VFPConv4Frm:
1477 case ARMII::VFPConv5Frm:
1479 Binary |= encodeVFPRd(MI, 1);
1483 if (Form == ARMII::VFPConv5Frm)
1485 Binary |= encodeVFPRn(MI, 2);
1486 else if (Form == ARMII::VFPConv3Frm)
1488 Binary |= encodeVFPRm(MI, 2);
1493 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1494 // Part of binary is determined by TableGn.
1495 unsigned Binary = getBinaryCodeForInstr(MI);
1497 // Set the conditional execution predicate
1498 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1503 Binary |= encodeVFPRd(MI, OpIdx++);
1505 // Encode address base.
1506 const MachineOperand &Base = MI.getOperand(OpIdx++);
1507 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1509 // If there is a non-zero immediate offset, encode it.
1511 const MachineOperand &Offset = MI.getOperand(OpIdx);
1512 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1513 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1514 Binary |= 1 << ARMII::U_BitShift;
1521 // If immediate offset is omitted, default to +0.
1522 Binary |= 1 << ARMII::U_BitShift;
1528 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1529 const TargetInstrDesc &TID = MI.getDesc();
1530 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1532 // Part of binary is determined by TableGn.
1533 unsigned Binary = getBinaryCodeForInstr(MI);
1535 // Set the conditional execution predicate
1536 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1538 // Skip operand 0 of an instruction with base register update.
1543 // Set base address operand
1544 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1546 // Set addressing mode by modifying bits U(23) and P(24)
1547 const MachineOperand &MO = MI.getOperand(OpIdx++);
1548 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1552 Binary |= 0x1 << ARMII::W_BitShift;
1554 // First register is encoded in Dd.
1555 Binary |= encodeVFPRd(MI, OpIdx+2);
1557 // Count the number of registers.
1558 unsigned NumRegs = 1;
1559 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1560 const MachineOperand &MO = MI.getOperand(i);
1561 if (!MO.isReg() || MO.isImplicit())
1565 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1566 // Otherwise, it will be 0, in the case of 32-bit registers.
1568 Binary |= NumRegs * 2;
1575 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1576 unsigned Opcode = MI.getDesc().Opcode;
1577 // Part of binary is determined by TableGn.
1578 unsigned Binary = getBinaryCodeForInstr(MI);
1580 // Set the conditional execution predicate
1581 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1585 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1588 // No further encoding needed.
1593 const MachineOperand &MO0 = MI.getOperand(0);
1595 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1596 << ARMII::RegRdShift;
1601 case ARM::FCONSTS: {
1603 Binary |= encodeVFPRd(MI, 0);
1605 // Encode imm., Table A7-18 VFP modified immediate constants
1606 const MachineOperand &MO1 = MI.getOperand(1);
1607 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1608 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1609 unsigned ModifiedImm;
1611 if(Opcode == ARM::FCONSTS)
1612 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1613 (Imm & 0x03F80000) >> 19; // bcdefgh
1614 else // Opcode == ARM::FCONSTD
1615 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1616 (Imm & 0x007F0000) >> 16; // bcdefgh
1618 // Insts{19-16} = abcd, Insts{3-0} = efgh
1619 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1620 Binary |= (ModifiedImm & 0xF);
1628 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1629 unsigned RegD = MI.getOperand(OpIdx).getReg();
1630 unsigned Binary = 0;
1631 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1632 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1633 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1637 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1638 unsigned RegN = MI.getOperand(OpIdx).getReg();
1639 unsigned Binary = 0;
1640 RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1641 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1642 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1646 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1647 unsigned RegM = MI.getOperand(OpIdx).getReg();
1648 unsigned Binary = 0;
1649 RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1650 Binary |= (RegM & 0xf);
1651 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1655 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1656 /// data-processing instruction to the corresponding Thumb encoding.
1657 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1658 assert((Binary & 0xfe000000) == 0xf2000000 &&
1659 "not an ARM NEON data-processing instruction");
1660 unsigned UBit = (Binary >> 24) & 1;
1661 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1664 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1665 unsigned Binary = getBinaryCodeForInstr(MI);
1667 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1668 const TargetInstrDesc &TID = MI.getDesc();
1669 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1673 } else { // ARMII::NSetLnFrm
1679 // Set the conditional execution predicate
1680 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1682 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1683 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1684 Binary |= (RegT << ARMII::RegRdShift);
1685 Binary |= encodeNEONRn(MI, RegNOpIdx);
1688 if ((Binary & (1 << 22)) != 0)
1689 LaneShift = 0; // 8-bit elements
1690 else if ((Binary & (1 << 5)) != 0)
1691 LaneShift = 1; // 16-bit elements
1693 LaneShift = 2; // 32-bit elements
1695 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1696 unsigned Opc1 = Lane >> 2;
1697 unsigned Opc2 = Lane & 3;
1698 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1699 Binary |= (Opc1 << 21);
1700 Binary |= (Opc2 << 5);
1705 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1706 unsigned Binary = getBinaryCodeForInstr(MI);
1708 // Set the conditional execution predicate
1709 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1711 unsigned RegT = MI.getOperand(1).getReg();
1712 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1713 Binary |= (RegT << ARMII::RegRdShift);
1714 Binary |= encodeNEONRn(MI, 0);
1718 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1719 unsigned Binary = getBinaryCodeForInstr(MI);
1720 // Destination register is encoded in Dd.
1721 Binary |= encodeNEONRd(MI, 0);
1722 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1723 unsigned Imm = MI.getOperand(1).getImm();
1724 unsigned Op = (Imm >> 12) & 1;
1725 unsigned Cmode = (Imm >> 8) & 0xf;
1726 unsigned I = (Imm >> 7) & 1;
1727 unsigned Imm3 = (Imm >> 4) & 0x7;
1728 unsigned Imm4 = Imm & 0xf;
1729 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1731 Binary = convertNEONDataProcToThumb(Binary);
1735 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1736 const TargetInstrDesc &TID = MI.getDesc();
1737 unsigned Binary = getBinaryCodeForInstr(MI);
1738 // Destination register is encoded in Dd; source register in Dm.
1740 Binary |= encodeNEONRd(MI, OpIdx++);
1741 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1743 Binary |= encodeNEONRm(MI, OpIdx);
1745 Binary = convertNEONDataProcToThumb(Binary);
1746 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1750 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1751 const TargetInstrDesc &TID = MI.getDesc();
1752 unsigned Binary = getBinaryCodeForInstr(MI);
1753 // Destination register is encoded in Dd; source registers in Dn and Dm.
1755 Binary |= encodeNEONRd(MI, OpIdx++);
1756 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1758 Binary |= encodeNEONRn(MI, OpIdx++);
1759 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1761 Binary |= encodeNEONRm(MI, OpIdx);
1763 Binary = convertNEONDataProcToThumb(Binary);
1764 // FIXME: This does not handle VMOVDneon or VMOVQ.
1768 #include "ARMGenCodeEmitter.inc"