1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
210 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
212 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
216 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
220 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
226 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
227 unsigned Op) const { return 0; }
228 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
230 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
233 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
236 // {12} = (U)nsigned (add == '1', sub == '0')
238 const MachineOperand &MO = MI.getOperand(Op);
239 const MachineOperand &MO1 = MI.getOperand(Op + 1);
241 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
244 unsigned Reg = getARMRegisterNumbering(MO.getReg());
245 int32_t Imm12 = MO1.getImm();
247 Binary = Imm12 & 0xfff;
250 Binary |= (Reg << 13);
254 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
258 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
260 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
262 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
264 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
266 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
268 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
270 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
272 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
274 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
276 // {12} = (U)nsigned (add == '1', sub == '0')
278 const MachineOperand &MO = MI.getOperand(Op);
279 const MachineOperand &MO1 = MI.getOperand(Op + 1);
281 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
284 unsigned Reg = getARMRegisterNumbering(MO.getReg());
285 int32_t Imm12 = MO1.getImm();
287 // Special value for #-0
288 if (Imm12 == INT32_MIN)
291 // Immediate is always encoded as positive. The 'U' bit controls add vs
299 uint32_t Binary = Imm12 & 0xfff;
302 Binary |= (Reg << 13);
305 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
308 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
311 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
312 /// machine operand requires relocation, record the relocation and return
314 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
317 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
319 unsigned getShiftOp(unsigned Imm) const ;
321 /// Routines that handle operands which add machine relocations which are
322 /// fixed up by the relocation stage.
323 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
324 bool MayNeedFarStub, bool Indirect,
325 intptr_t ACPV = 0) const;
326 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
327 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
328 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
329 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
330 intptr_t JTBase = 0) const;
334 char ARMCodeEmitter::ID = 0;
336 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
337 /// code to the specified MCE object.
338 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
339 JITCodeEmitter &JCE) {
340 return new ARMCodeEmitter(TM, JCE);
343 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
344 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
345 MF.getTarget().getRelocationModel() != Reloc::Static) &&
346 "JIT relocation model must be set to static or default!");
347 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
348 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
349 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
350 Subtarget = &TM.getSubtarget<ARMSubtarget>();
351 MCPEs = &MF.getConstantPool()->getConstants();
353 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
354 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
355 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
356 JTI->Initialize(MF, IsPIC);
357 MMI = &getAnalysis<MachineModuleInfo>();
358 MCE.setModuleInfo(MMI);
361 DEBUG(errs() << "JITTing function '"
362 << MF.getFunction()->getName() << "'\n");
363 MCE.startFunction(MF);
364 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
366 MCE.StartMachineBasicBlock(MBB);
367 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
371 } while (MCE.finishFunction(MF));
376 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
378 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
379 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
380 default: llvm_unreachable("Unknown shift opc!");
381 case ARM_AM::asr: return 2;
382 case ARM_AM::lsl: return 0;
383 case ARM_AM::lsr: return 1;
385 case ARM_AM::rrx: return 3;
390 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
391 /// machine operand requires relocation, record the relocation and return zero.
392 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
393 const MachineOperand &MO,
395 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
396 && "Relocation to this function should be for movt or movw");
399 return static_cast<unsigned>(MO.getImm());
400 else if (MO.isGlobal())
401 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
402 else if (MO.isSymbol())
403 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
405 emitMachineBasicBlock(MO.getMBB(), Reloc);
410 llvm_unreachable("Unsupported operand type for movw/movt");
415 /// getMachineOpValue - Return binary encoding of operand. If the machine
416 /// operand requires relocation, record the relocation and return zero.
417 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
418 const MachineOperand &MO) const {
420 return getARMRegisterNumbering(MO.getReg());
422 return static_cast<unsigned>(MO.getImm());
423 else if (MO.isGlobal())
424 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
425 else if (MO.isSymbol())
426 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
427 else if (MO.isCPI()) {
428 const TargetInstrDesc &TID = MI.getDesc();
429 // For VFP load, the immediate offset is multiplied by 4.
430 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
431 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
432 emitConstPoolAddress(MO.getIndex(), Reloc);
433 } else if (MO.isJTI())
434 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
436 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
438 llvm_unreachable("Unable to encode MachineOperand!");
442 /// emitGlobalAddress - Emit the specified address to the code stream.
444 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
445 bool MayNeedFarStub, bool Indirect,
446 intptr_t ACPV) const {
447 MachineRelocation MR = Indirect
448 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
449 const_cast<GlobalValue *>(GV),
450 ACPV, MayNeedFarStub)
451 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
452 const_cast<GlobalValue *>(GV), ACPV,
454 MCE.addRelocation(MR);
457 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
458 /// be emitted to the current location in the function, and allow it to be PC
460 void ARMCodeEmitter::
461 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
462 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
466 /// emitConstPoolAddress - Arrange for the address of an constant pool
467 /// to be emitted to the current location in the function, and allow it to be PC
469 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
470 // Tell JIT emitter we'll resolve the address.
471 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
472 Reloc, CPI, 0, true));
475 /// emitJumpTableAddress - Arrange for the address of a jump table to
476 /// be emitted to the current location in the function, and allow it to be PC
478 void ARMCodeEmitter::
479 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
480 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
481 Reloc, JTIndex, 0, true));
484 /// emitMachineBasicBlock - Emit the specified address basic block.
485 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
487 intptr_t JTBase) const {
488 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
492 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
493 DEBUG(errs() << " 0x";
494 errs().write_hex(Binary) << "\n");
495 MCE.emitWordLE(Binary);
498 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
499 DEBUG(errs() << " 0x";
500 errs().write_hex(Binary) << "\n");
501 MCE.emitDWordLE(Binary);
504 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
505 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
507 MCE.processDebugLoc(MI.getDebugLoc(), true);
509 ++NumEmitted; // Keep track of the # of mi's emitted
510 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
512 llvm_unreachable("Unhandled instruction encoding format!");
516 if (MI.getOpcode() == ARM::LEApcrelJT) {
517 // Materialize jumptable address.
518 emitLEApcrelJTInstruction(MI);
521 llvm_unreachable("Unhandled instruction encoding!");
524 emitPseudoInstruction(MI);
527 case ARMII::DPSoRegFrm:
528 emitDataProcessingInstruction(MI);
532 emitLoadStoreInstruction(MI);
534 case ARMII::LdMiscFrm:
535 case ARMII::StMiscFrm:
536 emitMiscLoadStoreInstruction(MI);
538 case ARMII::LdStMulFrm:
539 emitLoadStoreMultipleInstruction(MI);
542 emitMulFrmInstruction(MI);
545 emitExtendInstruction(MI);
547 case ARMII::ArithMiscFrm:
548 emitMiscArithInstruction(MI);
551 emitSaturateInstruction(MI);
554 emitBranchInstruction(MI);
556 case ARMII::BrMiscFrm:
557 emitMiscBranchInstruction(MI);
560 case ARMII::VFPUnaryFrm:
561 case ARMII::VFPBinaryFrm:
562 emitVFPArithInstruction(MI);
564 case ARMII::VFPConv1Frm:
565 case ARMII::VFPConv2Frm:
566 case ARMII::VFPConv3Frm:
567 case ARMII::VFPConv4Frm:
568 case ARMII::VFPConv5Frm:
569 emitVFPConversionInstruction(MI);
571 case ARMII::VFPLdStFrm:
572 emitVFPLoadStoreInstruction(MI);
574 case ARMII::VFPLdStMulFrm:
575 emitVFPLoadStoreMultipleInstruction(MI);
578 // NEON instructions.
579 case ARMII::NGetLnFrm:
580 case ARMII::NSetLnFrm:
581 emitNEONLaneInstruction(MI);
584 emitNEONDupInstruction(MI);
586 case ARMII::N1RegModImmFrm:
587 emitNEON1RegModImmInstruction(MI);
589 case ARMII::N2RegFrm:
590 emitNEON2RegInstruction(MI);
592 case ARMII::N3RegFrm:
593 emitNEON3RegInstruction(MI);
596 MCE.processDebugLoc(MI.getDebugLoc(), false);
599 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
600 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
601 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
602 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
604 // Remember the CONSTPOOL_ENTRY address for later relocation.
605 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
607 // Emit constpool island entry. In most cases, the actual values will be
608 // resolved and relocated after code emission.
609 if (MCPE.isMachineConstantPoolEntry()) {
610 ARMConstantPoolValue *ACPV =
611 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
613 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
614 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
616 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
617 const GlobalValue *GV = ACPV->getGV();
619 Reloc::Model RelocM = TM.getRelocationModel();
620 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
622 Subtarget->GVIsIndirectSymbol(GV, RelocM),
625 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
629 const Constant *CV = MCPE.Val.ConstVal;
632 errs() << " ** Constant pool #" << CPI << " @ "
633 << (void*)MCE.getCurrentPCValue() << " ";
634 if (const Function *F = dyn_cast<Function>(CV))
635 errs() << F->getName();
641 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
642 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
644 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
645 uint32_t Val = uint32_t(*CI->getValue().getRawData());
647 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
648 if (CFP->getType()->isFloatTy())
649 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
650 else if (CFP->getType()->isDoubleTy())
651 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
653 llvm_unreachable("Unable to handle this constantpool entry!");
656 llvm_unreachable("Unable to handle this constantpool entry!");
661 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
662 const MachineOperand &MO0 = MI.getOperand(0);
663 const MachineOperand &MO1 = MI.getOperand(1);
665 // Emit the 'movw' instruction.
666 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
668 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
670 // Set the conditional execution predicate.
671 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
674 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
676 // Encode imm16 as imm4:imm12
677 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
678 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
681 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
682 // Emit the 'movt' instruction.
683 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
685 // Set the conditional execution predicate.
686 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
689 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
691 // Encode imm16 as imm4:imm1, same as movw above.
692 Binary |= Hi16 & 0xFFF;
693 Binary |= ((Hi16 >> 12) & 0xF) << 16;
697 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
698 const MachineOperand &MO0 = MI.getOperand(0);
699 const MachineOperand &MO1 = MI.getOperand(1);
700 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
701 "Not a valid so_imm value!");
702 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
703 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
705 // Emit the 'mov' instruction.
706 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
708 // Set the conditional execution predicate.
709 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
715 // Set bit I(25) to identify this is the immediate form of <shifter_op>
716 Binary |= 1 << ARMII::I_BitShift;
717 Binary |= getMachineSoImmOpValue(V1);
720 // Now the 'orr' instruction.
721 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
723 // Set the conditional execution predicate.
724 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
727 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
730 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
733 // Set bit I(25) to identify this is the immediate form of <shifter_op>
734 Binary |= 1 << ARMII::I_BitShift;
735 Binary |= getMachineSoImmOpValue(V2);
739 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
740 // It's basically add r, pc, (LJTI - $+8)
742 const TargetInstrDesc &TID = MI.getDesc();
744 // Emit the 'add' instruction.
745 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
747 // Set the conditional execution predicate
748 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
750 // Encode S bit if MI modifies CPSR.
751 Binary |= getAddrModeSBit(MI, TID);
754 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
756 // Encode Rn which is PC.
757 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
759 // Encode the displacement.
760 Binary |= 1 << ARMII::I_BitShift;
761 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
766 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
767 unsigned Opcode = MI.getDesc().Opcode;
769 // Part of binary is determined by TableGn.
770 unsigned Binary = getBinaryCodeForInstr(MI);
772 // Set the conditional execution predicate
773 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
775 // Encode S bit if MI modifies CPSR.
776 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
777 Binary |= 1 << ARMII::S_BitShift;
779 // Encode register def if there is one.
780 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
782 // Encode the shift operation.
789 case ARM::MOVsrl_flag:
791 Binary |= (0x2 << 4) | (1 << 7);
793 case ARM::MOVsra_flag:
795 Binary |= (0x4 << 4) | (1 << 7);
799 // Encode register Rm.
800 Binary |= getMachineOpValue(MI, 1);
805 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
806 DEBUG(errs() << " ** LPC" << LabelID << " @ "
807 << (void*)MCE.getCurrentPCValue() << '\n');
808 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
811 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
812 unsigned Opcode = MI.getDesc().Opcode;
815 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
817 case ARM::BMOVPCRX_CALL:
819 case ARM::BMOVPCRXr9_CALL: {
820 // First emit mov lr, pc
821 unsigned Binary = 0x01a0e00f;
822 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
825 // and then emit the branch.
826 emitMiscBranchInstruction(MI);
829 case TargetOpcode::INLINEASM: {
830 // We allow inline assembler nodes with empty bodies - they can
831 // implicitly define registers, which is ok for JIT.
832 if (MI.getOperand(0).getSymbolName()[0]) {
833 report_fatal_error("JIT does not support inline asm!");
837 case TargetOpcode::PROLOG_LABEL:
838 case TargetOpcode::EH_LABEL:
839 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
841 case TargetOpcode::IMPLICIT_DEF:
842 case TargetOpcode::KILL:
845 case ARM::CONSTPOOL_ENTRY:
846 emitConstPoolInstruction(MI);
849 // Remember of the address of the PC label for relocation later.
850 addPCLabel(MI.getOperand(2).getImm());
851 // PICADD is just an add instruction that implicitly read pc.
852 emitDataProcessingInstruction(MI, 0, ARM::PC);
859 // Remember of the address of the PC label for relocation later.
860 addPCLabel(MI.getOperand(2).getImm());
861 // These are just load / store instructions that implicitly read pc.
862 emitLoadStoreInstruction(MI, 0, ARM::PC);
869 // Remember of the address of the PC label for relocation later.
870 addPCLabel(MI.getOperand(2).getImm());
871 // These are just load / store instructions that implicitly read pc.
872 emitMiscLoadStoreInstruction(MI, ARM::PC);
877 // Two instructions to materialize a constant.
878 if (Subtarget->hasV6T2Ops())
879 emitMOVi32immInstruction(MI);
881 emitMOVi2piecesInstruction(MI);
884 case ARM::LEApcrelJT:
885 // Materialize jumptable address.
886 emitLEApcrelJTInstruction(MI);
889 case ARM::MOVsrl_flag:
890 case ARM::MOVsra_flag:
891 emitPseudoMoveInstruction(MI);
896 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
897 const TargetInstrDesc &TID,
898 const MachineOperand &MO,
900 unsigned Binary = getMachineOpValue(MI, MO);
902 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
903 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
904 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
906 // Encode the shift opcode.
908 unsigned Rs = MO1.getReg();
910 // Set shift operand (bit[7:4]).
915 // RRX - 0110 and bit[11:8] clear.
917 default: llvm_unreachable("Unknown shift opc!");
918 case ARM_AM::lsl: SBits = 0x1; break;
919 case ARM_AM::lsr: SBits = 0x3; break;
920 case ARM_AM::asr: SBits = 0x5; break;
921 case ARM_AM::ror: SBits = 0x7; break;
922 case ARM_AM::rrx: SBits = 0x6; break;
925 // Set shift operand (bit[6:4]).
931 default: llvm_unreachable("Unknown shift opc!");
932 case ARM_AM::lsl: SBits = 0x0; break;
933 case ARM_AM::lsr: SBits = 0x2; break;
934 case ARM_AM::asr: SBits = 0x4; break;
935 case ARM_AM::ror: SBits = 0x6; break;
938 Binary |= SBits << 4;
939 if (SOpc == ARM_AM::rrx)
942 // Encode the shift operation Rs or shift_imm (except rrx).
944 // Encode Rs bit[11:8].
945 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
946 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
949 // Encode shift_imm bit[11:7].
950 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
953 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
954 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
955 assert(SoImmVal != -1 && "Not a valid so_imm value!");
957 // Encode rotate_imm.
958 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
959 << ARMII::SoRotImmShift;
962 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
966 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
967 const TargetInstrDesc &TID) const {
968 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
969 const MachineOperand &MO = MI.getOperand(i-1);
970 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
971 return 1 << ARMII::S_BitShift;
976 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
978 unsigned ImplicitRn) {
979 const TargetInstrDesc &TID = MI.getDesc();
981 // Part of binary is determined by TableGn.
982 unsigned Binary = getBinaryCodeForInstr(MI);
984 // Set the conditional execution predicate
985 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
987 // Encode S bit if MI modifies CPSR.
988 Binary |= getAddrModeSBit(MI, TID);
990 // Encode register def if there is one.
991 unsigned NumDefs = TID.getNumDefs();
994 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
996 // Special handling for implicit use (e.g. PC).
997 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
999 if (TID.Opcode == ARM::MOVi16) {
1000 // Get immediate from MI.
1001 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1002 ARM::reloc_arm_movw);
1003 // Encode imm which is the same as in emitMOVi32immInstruction().
1004 Binary |= Lo16 & 0xFFF;
1005 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1008 } else if(TID.Opcode == ARM::MOVTi16) {
1009 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1010 ARM::reloc_arm_movt) >> 16);
1011 Binary |= Hi16 & 0xFFF;
1012 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1015 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
1016 uint32_t v = ~MI.getOperand(2).getImm();
1017 int32_t lsb = CountTrailingZeros_32(v);
1018 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1019 // Instr{20-16} = msb, Instr{11-7} = lsb
1020 Binary |= (msb & 0x1F) << 16;
1021 Binary |= (lsb & 0x1F) << 7;
1024 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
1025 // Encode Rn in Instr{0-3}
1026 Binary |= getMachineOpValue(MI, OpIdx++);
1028 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1029 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1031 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1032 Binary |= (widthm1 & 0x1F) << 16;
1033 Binary |= (lsb & 0x1F) << 7;
1038 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1039 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1042 // Encode first non-shifter register operand if there is one.
1043 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1046 // Special handling for implicit use (e.g. PC).
1047 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1049 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1054 // Encode shifter operand.
1055 const MachineOperand &MO = MI.getOperand(OpIdx);
1056 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1058 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1063 // Encode register Rm.
1064 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1069 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1074 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1075 unsigned ImplicitRd,
1076 unsigned ImplicitRn) {
1077 const TargetInstrDesc &TID = MI.getDesc();
1078 unsigned Form = TID.TSFlags & ARMII::FormMask;
1079 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1081 // Part of binary is determined by TableGn.
1082 unsigned Binary = getBinaryCodeForInstr(MI);
1084 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1085 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1086 MI.getOpcode() == ARM::STRi12) {
1091 // Set the conditional execution predicate
1092 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1096 // Operand 0 of a pre- and post-indexed store is the address base
1097 // writeback. Skip it.
1098 bool Skipped = false;
1099 if (IsPrePost && Form == ARMII::StFrm) {
1104 // Set first operand
1106 // Special handling for implicit use (e.g. PC).
1107 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1109 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1111 // Set second operand
1113 // Special handling for implicit use (e.g. PC).
1114 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1116 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1118 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1119 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1122 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1123 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1124 ? 0 : MI.getOperand(OpIdx+1).getImm();
1126 // Set bit U(23) according to sign of immed value (positive or negative).
1127 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1129 if (!MO2.getReg()) { // is immediate
1130 if (ARM_AM::getAM2Offset(AM2Opc))
1131 // Set the value of offset_12 field
1132 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1137 // Set bit I(25), because this is not in immediate encoding.
1138 Binary |= 1 << ARMII::I_BitShift;
1139 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1140 // Set bit[3:0] to the corresponding Rm register
1141 Binary |= getARMRegisterNumbering(MO2.getReg());
1143 // If this instr is in scaled register offset/index instruction, set
1144 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1145 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1146 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1147 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1153 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1154 unsigned ImplicitRn) {
1155 const TargetInstrDesc &TID = MI.getDesc();
1156 unsigned Form = TID.TSFlags & ARMII::FormMask;
1157 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1159 // Part of binary is determined by TableGn.
1160 unsigned Binary = getBinaryCodeForInstr(MI);
1162 // Set the conditional execution predicate
1163 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1167 // Operand 0 of a pre- and post-indexed store is the address base
1168 // writeback. Skip it.
1169 bool Skipped = false;
1170 if (IsPrePost && Form == ARMII::StMiscFrm) {
1175 // Set first operand
1176 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1178 // Skip LDRD and STRD's second operand.
1179 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1182 // Set second operand
1184 // Special handling for implicit use (e.g. PC).
1185 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1187 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1189 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1190 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1193 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1194 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1195 ? 0 : MI.getOperand(OpIdx+1).getImm();
1197 // Set bit U(23) according to sign of immed value (positive or negative)
1198 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1201 // If this instr is in register offset/index encoding, set bit[3:0]
1202 // to the corresponding Rm register.
1204 Binary |= getARMRegisterNumbering(MO2.getReg());
1209 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1210 Binary |= 1 << ARMII::AM3_I_BitShift;
1211 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1213 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1214 Binary |= (ImmOffs & 0xF); // immedL
1220 static unsigned getAddrModeUPBits(unsigned Mode) {
1221 unsigned Binary = 0;
1223 // Set addressing mode by modifying bits U(23) and P(24)
1224 // IA - Increment after - bit U = 1 and bit P = 0
1225 // IB - Increment before - bit U = 1 and bit P = 1
1226 // DA - Decrement after - bit U = 0 and bit P = 0
1227 // DB - Decrement before - bit U = 0 and bit P = 1
1229 default: llvm_unreachable("Unknown addressing sub-mode!");
1230 case ARM_AM::da: break;
1231 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1232 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1233 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1239 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1240 const TargetInstrDesc &TID = MI.getDesc();
1241 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1243 // Part of binary is determined by TableGn.
1244 unsigned Binary = getBinaryCodeForInstr(MI);
1246 // Set the conditional execution predicate
1247 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249 // Skip operand 0 of an instruction with base register update.
1254 // Set base address operand
1255 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1257 // Set addressing mode by modifying bits U(23) and P(24)
1258 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1259 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1263 Binary |= 0x1 << ARMII::W_BitShift;
1266 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1267 const MachineOperand &MO = MI.getOperand(i);
1268 if (!MO.isReg() || MO.isImplicit())
1270 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1271 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1273 Binary |= 0x1 << RegNum;
1279 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1280 const TargetInstrDesc &TID = MI.getDesc();
1282 // Part of binary is determined by TableGn.
1283 unsigned Binary = getBinaryCodeForInstr(MI);
1285 // Set the conditional execution predicate
1286 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1288 // Encode S bit if MI modifies CPSR.
1289 Binary |= getAddrModeSBit(MI, TID);
1291 // 32x32->64bit operations have two destination registers. The number
1292 // of register definitions will tell us if that's what we're dealing with.
1294 if (TID.getNumDefs() == 2)
1295 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1298 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1301 Binary |= getMachineOpValue(MI, OpIdx++);
1304 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1306 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1307 // it as Rn (for multiply, that's in the same offset as RdLo.
1308 if (TID.getNumOperands() > OpIdx &&
1309 !TID.OpInfo[OpIdx].isPredicate() &&
1310 !TID.OpInfo[OpIdx].isOptionalDef())
1311 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1316 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1317 const TargetInstrDesc &TID = MI.getDesc();
1319 // Part of binary is determined by TableGn.
1320 unsigned Binary = getBinaryCodeForInstr(MI);
1322 // Set the conditional execution predicate
1323 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1328 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1330 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1331 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1333 // Two register operand form.
1335 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1338 Binary |= getMachineOpValue(MI, MO2);
1341 Binary |= getMachineOpValue(MI, MO1);
1344 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1345 if (MI.getOperand(OpIdx).isImm() &&
1346 !TID.OpInfo[OpIdx].isPredicate() &&
1347 !TID.OpInfo[OpIdx].isOptionalDef())
1348 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1353 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1354 const TargetInstrDesc &TID = MI.getDesc();
1356 // Part of binary is determined by TableGn.
1357 unsigned Binary = getBinaryCodeForInstr(MI);
1359 // Set the conditional execution predicate
1360 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1365 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1367 const MachineOperand &MO = MI.getOperand(OpIdx++);
1368 if (OpIdx == TID.getNumOperands() ||
1369 TID.OpInfo[OpIdx].isPredicate() ||
1370 TID.OpInfo[OpIdx].isOptionalDef()) {
1371 // Encode Rm and it's done.
1372 Binary |= getMachineOpValue(MI, MO);
1378 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1381 Binary |= getMachineOpValue(MI, OpIdx++);
1383 // Encode shift_imm.
1384 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1385 if (TID.Opcode == ARM::PKHTB) {
1386 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1390 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1391 Binary |= ShiftAmt << ARMII::ShiftShift;
1396 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1397 const TargetInstrDesc &TID = MI.getDesc();
1399 // Part of binary is determined by TableGen.
1400 unsigned Binary = getBinaryCodeForInstr(MI);
1402 // Set the conditional execution predicate
1403 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1406 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1408 // Encode saturate bit position.
1409 unsigned Pos = MI.getOperand(1).getImm();
1410 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1412 assert((Pos < 16 || (Pos < 32 &&
1413 TID.Opcode != ARM::SSAT16 &&
1414 TID.Opcode != ARM::USAT16)) &&
1415 "saturate bit position out of range");
1416 Binary |= Pos << 16;
1419 Binary |= getMachineOpValue(MI, 2);
1421 // Encode shift_imm.
1422 if (TID.getNumOperands() == 4) {
1423 unsigned ShiftOp = MI.getOperand(3).getImm();
1424 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1425 if (Opc == ARM_AM::asr)
1427 unsigned ShiftAmt = MI.getOperand(3).getImm();
1428 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1430 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1431 Binary |= ShiftAmt << ARMII::ShiftShift;
1437 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1438 const TargetInstrDesc &TID = MI.getDesc();
1440 if (TID.Opcode == ARM::TPsoft) {
1441 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1444 // Part of binary is determined by TableGn.
1445 unsigned Binary = getBinaryCodeForInstr(MI);
1447 // Set the conditional execution predicate
1448 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1450 // Set signed_immed_24 field
1451 Binary |= getMachineOpValue(MI, 0);
1456 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1457 // Remember the base address of the inline jump table.
1458 uintptr_t JTBase = MCE.getCurrentPCValue();
1459 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1460 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1463 // Now emit the jump table entries.
1464 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1465 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1467 // DestBB address - JT base.
1468 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1470 // Absolute DestBB address.
1471 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1476 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1477 const TargetInstrDesc &TID = MI.getDesc();
1479 // Handle jump tables.
1480 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1481 // First emit a ldr pc, [] instruction.
1482 emitDataProcessingInstruction(MI, ARM::PC);
1484 // Then emit the inline jump table.
1486 (TID.Opcode == ARM::BR_JTr)
1487 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1488 emitInlineJumpTable(JTIndex);
1490 } else if (TID.Opcode == ARM::BR_JTm) {
1491 // First emit a ldr pc, [] instruction.
1492 emitLoadStoreInstruction(MI, ARM::PC);
1494 // Then emit the inline jump table.
1495 emitInlineJumpTable(MI.getOperand(3).getIndex());
1499 // Part of binary is determined by TableGn.
1500 unsigned Binary = getBinaryCodeForInstr(MI);
1502 // Set the conditional execution predicate
1503 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1505 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1506 // The return register is LR.
1507 Binary |= getARMRegisterNumbering(ARM::LR);
1509 // otherwise, set the return register
1510 Binary |= getMachineOpValue(MI, 0);
1515 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1516 unsigned RegD = MI.getOperand(OpIdx).getReg();
1517 unsigned Binary = 0;
1518 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1519 RegD = getARMRegisterNumbering(RegD);
1521 Binary |= RegD << ARMII::RegRdShift;
1523 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1524 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1529 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1530 unsigned RegN = MI.getOperand(OpIdx).getReg();
1531 unsigned Binary = 0;
1532 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1533 RegN = getARMRegisterNumbering(RegN);
1535 Binary |= RegN << ARMII::RegRnShift;
1537 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1538 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1543 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1544 unsigned RegM = MI.getOperand(OpIdx).getReg();
1545 unsigned Binary = 0;
1546 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1547 RegM = getARMRegisterNumbering(RegM);
1551 Binary |= ((RegM & 0x1E) >> 1);
1552 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1557 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1558 const TargetInstrDesc &TID = MI.getDesc();
1560 // Part of binary is determined by TableGn.
1561 unsigned Binary = getBinaryCodeForInstr(MI);
1563 // Set the conditional execution predicate
1564 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1567 assert((Binary & ARMII::D_BitShift) == 0 &&
1568 (Binary & ARMII::N_BitShift) == 0 &&
1569 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1572 Binary |= encodeVFPRd(MI, OpIdx++);
1574 // If this is a two-address operand, skip it, e.g. FMACD.
1575 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1579 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1580 Binary |= encodeVFPRn(MI, OpIdx++);
1582 if (OpIdx == TID.getNumOperands() ||
1583 TID.OpInfo[OpIdx].isPredicate() ||
1584 TID.OpInfo[OpIdx].isOptionalDef()) {
1585 // FCMPEZD etc. has only one operand.
1591 Binary |= encodeVFPRm(MI, OpIdx);
1596 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1597 const TargetInstrDesc &TID = MI.getDesc();
1598 unsigned Form = TID.TSFlags & ARMII::FormMask;
1600 // Part of binary is determined by TableGn.
1601 unsigned Binary = getBinaryCodeForInstr(MI);
1603 // Set the conditional execution predicate
1604 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1608 case ARMII::VFPConv1Frm:
1609 case ARMII::VFPConv2Frm:
1610 case ARMII::VFPConv3Frm:
1612 Binary |= encodeVFPRd(MI, 0);
1614 case ARMII::VFPConv4Frm:
1616 Binary |= encodeVFPRn(MI, 0);
1618 case ARMII::VFPConv5Frm:
1620 Binary |= encodeVFPRm(MI, 0);
1626 case ARMII::VFPConv1Frm:
1628 Binary |= encodeVFPRm(MI, 1);
1630 case ARMII::VFPConv2Frm:
1631 case ARMII::VFPConv3Frm:
1633 Binary |= encodeVFPRn(MI, 1);
1635 case ARMII::VFPConv4Frm:
1636 case ARMII::VFPConv5Frm:
1638 Binary |= encodeVFPRd(MI, 1);
1642 if (Form == ARMII::VFPConv5Frm)
1644 Binary |= encodeVFPRn(MI, 2);
1645 else if (Form == ARMII::VFPConv3Frm)
1647 Binary |= encodeVFPRm(MI, 2);
1652 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1653 // Part of binary is determined by TableGn.
1654 unsigned Binary = getBinaryCodeForInstr(MI);
1656 // Set the conditional execution predicate
1657 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1662 Binary |= encodeVFPRd(MI, OpIdx++);
1664 // Encode address base.
1665 const MachineOperand &Base = MI.getOperand(OpIdx++);
1666 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1668 // If there is a non-zero immediate offset, encode it.
1670 const MachineOperand &Offset = MI.getOperand(OpIdx);
1671 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1672 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1673 Binary |= 1 << ARMII::U_BitShift;
1680 // If immediate offset is omitted, default to +0.
1681 Binary |= 1 << ARMII::U_BitShift;
1687 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1688 const TargetInstrDesc &TID = MI.getDesc();
1689 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1691 // Part of binary is determined by TableGn.
1692 unsigned Binary = getBinaryCodeForInstr(MI);
1694 // Set the conditional execution predicate
1695 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1697 // Skip operand 0 of an instruction with base register update.
1702 // Set base address operand
1703 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1705 // Set addressing mode by modifying bits U(23) and P(24)
1706 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1707 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1711 Binary |= 0x1 << ARMII::W_BitShift;
1713 // First register is encoded in Dd.
1714 Binary |= encodeVFPRd(MI, OpIdx+2);
1716 // Count the number of registers.
1717 unsigned NumRegs = 1;
1718 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1719 const MachineOperand &MO = MI.getOperand(i);
1720 if (!MO.isReg() || MO.isImplicit())
1724 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1725 // Otherwise, it will be 0, in the case of 32-bit registers.
1727 Binary |= NumRegs * 2;
1734 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1735 unsigned RegD = MI.getOperand(OpIdx).getReg();
1736 unsigned Binary = 0;
1737 RegD = getARMRegisterNumbering(RegD);
1738 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1739 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1743 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1744 unsigned RegN = MI.getOperand(OpIdx).getReg();
1745 unsigned Binary = 0;
1746 RegN = getARMRegisterNumbering(RegN);
1747 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1748 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1752 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1753 unsigned RegM = MI.getOperand(OpIdx).getReg();
1754 unsigned Binary = 0;
1755 RegM = getARMRegisterNumbering(RegM);
1756 Binary |= (RegM & 0xf);
1757 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1761 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1762 /// data-processing instruction to the corresponding Thumb encoding.
1763 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1764 assert((Binary & 0xfe000000) == 0xf2000000 &&
1765 "not an ARM NEON data-processing instruction");
1766 unsigned UBit = (Binary >> 24) & 1;
1767 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1770 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1771 unsigned Binary = getBinaryCodeForInstr(MI);
1773 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1774 const TargetInstrDesc &TID = MI.getDesc();
1775 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1779 } else { // ARMII::NSetLnFrm
1785 // Set the conditional execution predicate
1786 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1788 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1789 RegT = getARMRegisterNumbering(RegT);
1790 Binary |= (RegT << ARMII::RegRdShift);
1791 Binary |= encodeNEONRn(MI, RegNOpIdx);
1794 if ((Binary & (1 << 22)) != 0)
1795 LaneShift = 0; // 8-bit elements
1796 else if ((Binary & (1 << 5)) != 0)
1797 LaneShift = 1; // 16-bit elements
1799 LaneShift = 2; // 32-bit elements
1801 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1802 unsigned Opc1 = Lane >> 2;
1803 unsigned Opc2 = Lane & 3;
1804 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1805 Binary |= (Opc1 << 21);
1806 Binary |= (Opc2 << 5);
1811 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1812 unsigned Binary = getBinaryCodeForInstr(MI);
1814 // Set the conditional execution predicate
1815 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1817 unsigned RegT = MI.getOperand(1).getReg();
1818 RegT = getARMRegisterNumbering(RegT);
1819 Binary |= (RegT << ARMII::RegRdShift);
1820 Binary |= encodeNEONRn(MI, 0);
1824 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1825 unsigned Binary = getBinaryCodeForInstr(MI);
1826 // Destination register is encoded in Dd.
1827 Binary |= encodeNEONRd(MI, 0);
1828 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1829 unsigned Imm = MI.getOperand(1).getImm();
1830 unsigned Op = (Imm >> 12) & 1;
1831 unsigned Cmode = (Imm >> 8) & 0xf;
1832 unsigned I = (Imm >> 7) & 1;
1833 unsigned Imm3 = (Imm >> 4) & 0x7;
1834 unsigned Imm4 = Imm & 0xf;
1835 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1837 Binary = convertNEONDataProcToThumb(Binary);
1841 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1842 const TargetInstrDesc &TID = MI.getDesc();
1843 unsigned Binary = getBinaryCodeForInstr(MI);
1844 // Destination register is encoded in Dd; source register in Dm.
1846 Binary |= encodeNEONRd(MI, OpIdx++);
1847 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1849 Binary |= encodeNEONRm(MI, OpIdx);
1851 Binary = convertNEONDataProcToThumb(Binary);
1852 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1856 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1857 const TargetInstrDesc &TID = MI.getDesc();
1858 unsigned Binary = getBinaryCodeForInstr(MI);
1859 // Destination register is encoded in Dd; source registers in Dn and Dm.
1861 Binary |= encodeNEONRd(MI, OpIdx++);
1862 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1864 Binary |= encodeNEONRn(MI, OpIdx++);
1865 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1867 Binary |= encodeNEONRm(MI, OpIdx);
1869 Binary = convertNEONDataProcToThumb(Binary);
1870 // FIXME: This does not handle VMOVDneon or VMOVQ.
1874 #include "ARMGenCodeEmitter.inc"