1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitMiscInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,
154 const MachineOperand &MO) const;
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
160 // TableGen'erated getBinaryCodeForInstr() function to encode any
161 // operand values, instead querying getMachineOpValue() directly for
162 // each operand it needs to encode. Thus, any of the new encoder
163 // helper functions can simply return 0 as the values the return
164 // are already handled elsewhere. They are placeholders to allow this
165 // encoder to continue to function until the MC encoder is sufficiently
166 // far along that this one can be eliminated entirely.
167 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
169 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
171 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
173 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
176 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
177 /// machine operand requires relocation, record the relocation and return
179 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
182 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
184 unsigned getShiftOp(unsigned Imm) const ;
186 /// Routines that handle operands which add machine relocations which are
187 /// fixed up by the relocation stage.
188 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
189 bool MayNeedFarStub, bool Indirect,
190 intptr_t ACPV = 0) const;
191 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
192 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
193 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
194 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
195 intptr_t JTBase = 0) const;
199 char ARMCodeEmitter::ID = 0;
201 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
202 /// code to the specified MCE object.
203 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
204 JITCodeEmitter &JCE) {
205 return new ARMCodeEmitter(TM, JCE);
208 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
209 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
210 MF.getTarget().getRelocationModel() != Reloc::Static) &&
211 "JIT relocation model must be set to static or default!");
212 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
213 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
214 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
215 Subtarget = &TM.getSubtarget<ARMSubtarget>();
216 MCPEs = &MF.getConstantPool()->getConstants();
218 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
219 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
220 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
221 JTI->Initialize(MF, IsPIC);
222 MMI = &getAnalysis<MachineModuleInfo>();
223 MCE.setModuleInfo(MMI);
226 DEBUG(errs() << "JITTing function '"
227 << MF.getFunction()->getName() << "'\n");
228 MCE.startFunction(MF);
229 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
231 MCE.StartMachineBasicBlock(MBB);
232 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
236 } while (MCE.finishFunction(MF));
241 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
243 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
244 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
245 default: llvm_unreachable("Unknown shift opc!");
246 case ARM_AM::asr: return 2;
247 case ARM_AM::lsl: return 0;
248 case ARM_AM::lsr: return 1;
250 case ARM_AM::rrx: return 3;
255 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
256 /// machine operand requires relocation, record the relocation and return zero.
257 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
258 const MachineOperand &MO,
260 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
261 && "Relocation to this function should be for movt or movw");
264 return static_cast<unsigned>(MO.getImm());
265 else if (MO.isGlobal())
266 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
267 else if (MO.isSymbol())
268 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
270 emitMachineBasicBlock(MO.getMBB(), Reloc);
275 llvm_unreachable("Unsupported operand type for movw/movt");
280 /// getMachineOpValue - Return binary encoding of operand. If the machine
281 /// operand requires relocation, record the relocation and return zero.
282 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
283 const MachineOperand &MO) const {
285 return getARMRegisterNumbering(MO.getReg());
287 return static_cast<unsigned>(MO.getImm());
288 else if (MO.isGlobal())
289 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
290 else if (MO.isSymbol())
291 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
292 else if (MO.isCPI()) {
293 const TargetInstrDesc &TID = MI.getDesc();
294 // For VFP load, the immediate offset is multiplied by 4.
295 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
296 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
297 emitConstPoolAddress(MO.getIndex(), Reloc);
298 } else if (MO.isJTI())
299 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
301 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
311 /// emitGlobalAddress - Emit the specified address to the code stream.
313 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
314 bool MayNeedFarStub, bool Indirect,
315 intptr_t ACPV) const {
316 MachineRelocation MR = Indirect
317 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
318 const_cast<GlobalValue *>(GV),
319 ACPV, MayNeedFarStub)
320 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
321 const_cast<GlobalValue *>(GV), ACPV,
323 MCE.addRelocation(MR);
326 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
327 /// be emitted to the current location in the function, and allow it to be PC
329 void ARMCodeEmitter::
330 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
331 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
335 /// emitConstPoolAddress - Arrange for the address of an constant pool
336 /// to be emitted to the current location in the function, and allow it to be PC
338 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
339 // Tell JIT emitter we'll resolve the address.
340 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
341 Reloc, CPI, 0, true));
344 /// emitJumpTableAddress - Arrange for the address of a jump table to
345 /// be emitted to the current location in the function, and allow it to be PC
347 void ARMCodeEmitter::
348 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
349 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
350 Reloc, JTIndex, 0, true));
353 /// emitMachineBasicBlock - Emit the specified address basic block.
354 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
356 intptr_t JTBase) const {
357 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
361 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
362 DEBUG(errs() << " 0x";
363 errs().write_hex(Binary) << "\n");
364 MCE.emitWordLE(Binary);
367 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
368 DEBUG(errs() << " 0x";
369 errs().write_hex(Binary) << "\n");
370 MCE.emitDWordLE(Binary);
373 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
374 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
376 MCE.processDebugLoc(MI.getDebugLoc(), true);
378 ++NumEmitted; // Keep track of the # of mi's emitted
379 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
381 llvm_unreachable("Unhandled instruction encoding format!");
385 emitPseudoInstruction(MI);
388 case ARMII::DPSoRegFrm:
389 emitDataProcessingInstruction(MI);
393 emitLoadStoreInstruction(MI);
395 case ARMII::LdMiscFrm:
396 case ARMII::StMiscFrm:
397 emitMiscLoadStoreInstruction(MI);
399 case ARMII::LdStMulFrm:
400 emitLoadStoreMultipleInstruction(MI);
403 emitMulFrmInstruction(MI);
406 emitExtendInstruction(MI);
408 case ARMII::ArithMiscFrm:
409 emitMiscArithInstruction(MI);
412 emitSaturateInstruction(MI);
415 emitBranchInstruction(MI);
417 case ARMII::BrMiscFrm:
418 emitMiscBranchInstruction(MI);
421 case ARMII::VFPUnaryFrm:
422 case ARMII::VFPBinaryFrm:
423 emitVFPArithInstruction(MI);
425 case ARMII::VFPConv1Frm:
426 case ARMII::VFPConv2Frm:
427 case ARMII::VFPConv3Frm:
428 case ARMII::VFPConv4Frm:
429 case ARMII::VFPConv5Frm:
430 emitVFPConversionInstruction(MI);
432 case ARMII::VFPLdStFrm:
433 emitVFPLoadStoreInstruction(MI);
435 case ARMII::VFPLdStMulFrm:
436 emitVFPLoadStoreMultipleInstruction(MI);
438 case ARMII::VFPMiscFrm:
439 emitMiscInstruction(MI);
441 // NEON instructions.
442 case ARMII::NGetLnFrm:
443 case ARMII::NSetLnFrm:
444 emitNEONLaneInstruction(MI);
447 emitNEONDupInstruction(MI);
449 case ARMII::N1RegModImmFrm:
450 emitNEON1RegModImmInstruction(MI);
452 case ARMII::N2RegFrm:
453 emitNEON2RegInstruction(MI);
455 case ARMII::N3RegFrm:
456 emitNEON3RegInstruction(MI);
459 MCE.processDebugLoc(MI.getDebugLoc(), false);
462 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
463 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
464 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
465 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
467 // Remember the CONSTPOOL_ENTRY address for later relocation.
468 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
470 // Emit constpool island entry. In most cases, the actual values will be
471 // resolved and relocated after code emission.
472 if (MCPE.isMachineConstantPoolEntry()) {
473 ARMConstantPoolValue *ACPV =
474 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
476 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
477 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
479 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
480 const GlobalValue *GV = ACPV->getGV();
482 Reloc::Model RelocM = TM.getRelocationModel();
483 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
485 Subtarget->GVIsIndirectSymbol(GV, RelocM),
488 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
492 const Constant *CV = MCPE.Val.ConstVal;
495 errs() << " ** Constant pool #" << CPI << " @ "
496 << (void*)MCE.getCurrentPCValue() << " ";
497 if (const Function *F = dyn_cast<Function>(CV))
498 errs() << F->getName();
504 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
505 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
507 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
508 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
510 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
511 if (CFP->getType()->isFloatTy())
512 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
513 else if (CFP->getType()->isDoubleTy())
514 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
516 llvm_unreachable("Unable to handle this constantpool entry!");
519 llvm_unreachable("Unable to handle this constantpool entry!");
524 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
525 const MachineOperand &MO0 = MI.getOperand(0);
526 const MachineOperand &MO1 = MI.getOperand(1);
528 // Emit the 'movw' instruction.
529 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
531 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
533 // Set the conditional execution predicate.
534 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
537 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
539 // Encode imm16 as imm4:imm12
540 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
541 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
544 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
545 // Emit the 'movt' instruction.
546 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
548 // Set the conditional execution predicate.
549 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
552 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
554 // Encode imm16 as imm4:imm1, same as movw above.
555 Binary |= Hi16 & 0xFFF;
556 Binary |= ((Hi16 >> 12) & 0xF) << 16;
560 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
561 const MachineOperand &MO0 = MI.getOperand(0);
562 const MachineOperand &MO1 = MI.getOperand(1);
563 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
564 "Not a valid so_imm value!");
565 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
566 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
568 // Emit the 'mov' instruction.
569 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
571 // Set the conditional execution predicate.
572 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
575 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
578 // Set bit I(25) to identify this is the immediate form of <shifter_op>
579 Binary |= 1 << ARMII::I_BitShift;
580 Binary |= getMachineSoImmOpValue(V1);
583 // Now the 'orr' instruction.
584 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
586 // Set the conditional execution predicate.
587 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
590 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
593 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
596 // Set bit I(25) to identify this is the immediate form of <shifter_op>
597 Binary |= 1 << ARMII::I_BitShift;
598 Binary |= getMachineSoImmOpValue(V2);
602 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
603 // It's basically add r, pc, (LJTI - $+8)
605 const TargetInstrDesc &TID = MI.getDesc();
607 // Emit the 'add' instruction.
608 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
610 // Set the conditional execution predicate
611 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
613 // Encode S bit if MI modifies CPSR.
614 Binary |= getAddrModeSBit(MI, TID);
617 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
619 // Encode Rn which is PC.
620 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
622 // Encode the displacement.
623 Binary |= 1 << ARMII::I_BitShift;
624 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
629 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
630 unsigned Opcode = MI.getDesc().Opcode;
632 // Part of binary is determined by TableGn.
633 unsigned Binary = getBinaryCodeForInstr(MI);
635 // Set the conditional execution predicate
636 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
638 // Encode S bit if MI modifies CPSR.
639 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
640 Binary |= 1 << ARMII::S_BitShift;
642 // Encode register def if there is one.
643 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
645 // Encode the shift operation.
652 case ARM::MOVsrl_flag:
654 Binary |= (0x2 << 4) | (1 << 7);
656 case ARM::MOVsra_flag:
658 Binary |= (0x4 << 4) | (1 << 7);
662 // Encode register Rm.
663 Binary |= getMachineOpValue(MI, 1);
668 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
669 DEBUG(errs() << " ** LPC" << LabelID << " @ "
670 << (void*)MCE.getCurrentPCValue() << '\n');
671 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
674 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
675 unsigned Opcode = MI.getDesc().Opcode;
678 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
682 case ARM::BMOVPCRXr9: {
683 // First emit mov lr, pc
684 unsigned Binary = 0x01a0e00f;
685 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
688 // and then emit the branch.
689 emitMiscBranchInstruction(MI);
692 case TargetOpcode::INLINEASM: {
693 // We allow inline assembler nodes with empty bodies - they can
694 // implicitly define registers, which is ok for JIT.
695 if (MI.getOperand(0).getSymbolName()[0]) {
696 report_fatal_error("JIT does not support inline asm!");
700 case TargetOpcode::PROLOG_LABEL:
701 case TargetOpcode::EH_LABEL:
702 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
704 case TargetOpcode::IMPLICIT_DEF:
705 case TargetOpcode::KILL:
708 case ARM::CONSTPOOL_ENTRY:
709 emitConstPoolInstruction(MI);
712 // Remember of the address of the PC label for relocation later.
713 addPCLabel(MI.getOperand(2).getImm());
714 // PICADD is just an add instruction that implicitly read pc.
715 emitDataProcessingInstruction(MI, 0, ARM::PC);
722 // Remember of the address of the PC label for relocation later.
723 addPCLabel(MI.getOperand(2).getImm());
724 // These are just load / store instructions that implicitly read pc.
725 emitLoadStoreInstruction(MI, 0, ARM::PC);
732 // Remember of the address of the PC label for relocation later.
733 addPCLabel(MI.getOperand(2).getImm());
734 // These are just load / store instructions that implicitly read pc.
735 emitMiscLoadStoreInstruction(MI, ARM::PC);
740 emitMOVi32immInstruction(MI);
743 case ARM::MOVi2pieces:
744 // Two instructions to materialize a constant.
745 emitMOVi2piecesInstruction(MI);
747 case ARM::LEApcrelJT:
748 // Materialize jumptable address.
749 emitLEApcrelJTInstruction(MI);
752 case ARM::MOVsrl_flag:
753 case ARM::MOVsra_flag:
754 emitPseudoMoveInstruction(MI);
759 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
760 const TargetInstrDesc &TID,
761 const MachineOperand &MO,
763 unsigned Binary = getMachineOpValue(MI, MO);
765 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
766 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
767 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
769 // Encode the shift opcode.
771 unsigned Rs = MO1.getReg();
773 // Set shift operand (bit[7:4]).
778 // RRX - 0110 and bit[11:8] clear.
780 default: llvm_unreachable("Unknown shift opc!");
781 case ARM_AM::lsl: SBits = 0x1; break;
782 case ARM_AM::lsr: SBits = 0x3; break;
783 case ARM_AM::asr: SBits = 0x5; break;
784 case ARM_AM::ror: SBits = 0x7; break;
785 case ARM_AM::rrx: SBits = 0x6; break;
788 // Set shift operand (bit[6:4]).
794 default: llvm_unreachable("Unknown shift opc!");
795 case ARM_AM::lsl: SBits = 0x0; break;
796 case ARM_AM::lsr: SBits = 0x2; break;
797 case ARM_AM::asr: SBits = 0x4; break;
798 case ARM_AM::ror: SBits = 0x6; break;
801 Binary |= SBits << 4;
802 if (SOpc == ARM_AM::rrx)
805 // Encode the shift operation Rs or shift_imm (except rrx).
807 // Encode Rs bit[11:8].
808 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
809 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
812 // Encode shift_imm bit[11:7].
813 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
816 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
817 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
818 assert(SoImmVal != -1 && "Not a valid so_imm value!");
820 // Encode rotate_imm.
821 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
822 << ARMII::SoRotImmShift;
825 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
829 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
830 const TargetInstrDesc &TID) const {
831 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
832 const MachineOperand &MO = MI.getOperand(i-1);
833 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
834 return 1 << ARMII::S_BitShift;
839 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
841 unsigned ImplicitRn) {
842 const TargetInstrDesc &TID = MI.getDesc();
844 // Part of binary is determined by TableGn.
845 unsigned Binary = getBinaryCodeForInstr(MI);
847 // Set the conditional execution predicate
848 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
850 // Encode S bit if MI modifies CPSR.
851 Binary |= getAddrModeSBit(MI, TID);
853 // Encode register def if there is one.
854 unsigned NumDefs = TID.getNumDefs();
857 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
859 // Special handling for implicit use (e.g. PC).
860 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
862 if (TID.Opcode == ARM::MOVi16) {
863 // Get immediate from MI.
864 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
865 ARM::reloc_arm_movw);
866 // Encode imm which is the same as in emitMOVi32immInstruction().
867 Binary |= Lo16 & 0xFFF;
868 Binary |= ((Lo16 >> 12) & 0xF) << 16;
871 } else if(TID.Opcode == ARM::MOVTi16) {
872 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
873 ARM::reloc_arm_movt) >> 16);
874 Binary |= Hi16 & 0xFFF;
875 Binary |= ((Hi16 >> 12) & 0xF) << 16;
878 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
879 uint32_t v = ~MI.getOperand(2).getImm();
880 int32_t lsb = CountTrailingZeros_32(v);
881 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
882 // Instr{20-16} = msb, Instr{11-7} = lsb
883 Binary |= (msb & 0x1F) << 16;
884 Binary |= (lsb & 0x1F) << 7;
887 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
888 // Encode Rn in Instr{0-3}
889 Binary |= getMachineOpValue(MI, OpIdx++);
891 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
892 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
894 // Instr{20-16} = widthm1, Instr{11-7} = lsb
895 Binary |= (widthm1 & 0x1F) << 16;
896 Binary |= (lsb & 0x1F) << 7;
901 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
902 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
905 // Encode first non-shifter register operand if there is one.
906 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
909 // Special handling for implicit use (e.g. PC).
910 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
912 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
917 // Encode shifter operand.
918 const MachineOperand &MO = MI.getOperand(OpIdx);
919 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
921 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
926 // Encode register Rm.
927 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
932 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
937 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
939 unsigned ImplicitRn) {
940 const TargetInstrDesc &TID = MI.getDesc();
941 unsigned Form = TID.TSFlags & ARMII::FormMask;
942 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
944 // Part of binary is determined by TableGn.
945 unsigned Binary = getBinaryCodeForInstr(MI);
947 // Set the conditional execution predicate
948 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
952 // Operand 0 of a pre- and post-indexed store is the address base
953 // writeback. Skip it.
954 bool Skipped = false;
955 if (IsPrePost && Form == ARMII::StFrm) {
962 // Special handling for implicit use (e.g. PC).
963 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
965 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
967 // Set second operand
969 // Special handling for implicit use (e.g. PC).
970 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
972 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
974 // If this is a two-address operand, skip it. e.g. LDR_PRE.
975 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
978 const MachineOperand &MO2 = MI.getOperand(OpIdx);
979 unsigned AM2Opc = (ImplicitRn == ARM::PC)
980 ? 0 : MI.getOperand(OpIdx+1).getImm();
982 // Set bit U(23) according to sign of immed value (positive or negative).
983 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
985 if (!MO2.getReg()) { // is immediate
986 if (ARM_AM::getAM2Offset(AM2Opc))
987 // Set the value of offset_12 field
988 Binary |= ARM_AM::getAM2Offset(AM2Opc);
993 // Set bit I(25), because this is not in immediate enconding.
994 Binary |= 1 << ARMII::I_BitShift;
995 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
996 // Set bit[3:0] to the corresponding Rm register
997 Binary |= getARMRegisterNumbering(MO2.getReg());
999 // If this instr is in scaled register offset/index instruction, set
1000 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1001 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1002 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1003 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1009 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1010 unsigned ImplicitRn) {
1011 const TargetInstrDesc &TID = MI.getDesc();
1012 unsigned Form = TID.TSFlags & ARMII::FormMask;
1013 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1015 // Part of binary is determined by TableGn.
1016 unsigned Binary = getBinaryCodeForInstr(MI);
1018 // Set the conditional execution predicate
1019 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1023 // Operand 0 of a pre- and post-indexed store is the address base
1024 // writeback. Skip it.
1025 bool Skipped = false;
1026 if (IsPrePost && Form == ARMII::StMiscFrm) {
1031 // Set first operand
1032 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1034 // Skip LDRD and STRD's second operand.
1035 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1038 // Set second operand
1040 // Special handling for implicit use (e.g. PC).
1041 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1043 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1045 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1046 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1049 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1050 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1051 ? 0 : MI.getOperand(OpIdx+1).getImm();
1053 // Set bit U(23) according to sign of immed value (positive or negative)
1054 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1057 // If this instr is in register offset/index encoding, set bit[3:0]
1058 // to the corresponding Rm register.
1060 Binary |= getARMRegisterNumbering(MO2.getReg());
1065 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1066 Binary |= 1 << ARMII::AM3_I_BitShift;
1067 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1069 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1070 Binary |= (ImmOffs & 0xF); // immedL
1076 static unsigned getAddrModeUPBits(unsigned Mode) {
1077 unsigned Binary = 0;
1079 // Set addressing mode by modifying bits U(23) and P(24)
1080 // IA - Increment after - bit U = 1 and bit P = 0
1081 // IB - Increment before - bit U = 1 and bit P = 1
1082 // DA - Decrement after - bit U = 0 and bit P = 0
1083 // DB - Decrement before - bit U = 0 and bit P = 1
1085 default: llvm_unreachable("Unknown addressing sub-mode!");
1086 case ARM_AM::da: break;
1087 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1088 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1089 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1095 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1096 const TargetInstrDesc &TID = MI.getDesc();
1097 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1099 // Part of binary is determined by TableGn.
1100 unsigned Binary = getBinaryCodeForInstr(MI);
1102 // Set the conditional execution predicate
1103 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1105 // Skip operand 0 of an instruction with base register update.
1110 // Set base address operand
1111 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1113 // Set addressing mode by modifying bits U(23) and P(24)
1114 const MachineOperand &MO = MI.getOperand(OpIdx++);
1115 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1119 Binary |= 0x1 << ARMII::W_BitShift;
1122 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1123 const MachineOperand &MO = MI.getOperand(i);
1124 if (!MO.isReg() || MO.isImplicit())
1126 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1127 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1129 Binary |= 0x1 << RegNum;
1135 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1136 const TargetInstrDesc &TID = MI.getDesc();
1138 // Part of binary is determined by TableGn.
1139 unsigned Binary = getBinaryCodeForInstr(MI);
1141 // Set the conditional execution predicate
1142 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1144 // Encode S bit if MI modifies CPSR.
1145 Binary |= getAddrModeSBit(MI, TID);
1147 // 32x32->64bit operations have two destination registers. The number
1148 // of register definitions will tell us if that's what we're dealing with.
1150 if (TID.getNumDefs() == 2)
1151 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1154 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1157 Binary |= getMachineOpValue(MI, OpIdx++);
1160 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1162 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1163 // it as Rn (for multiply, that's in the same offset as RdLo.
1164 if (TID.getNumOperands() > OpIdx &&
1165 !TID.OpInfo[OpIdx].isPredicate() &&
1166 !TID.OpInfo[OpIdx].isOptionalDef())
1167 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1172 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1173 const TargetInstrDesc &TID = MI.getDesc();
1175 // Part of binary is determined by TableGn.
1176 unsigned Binary = getBinaryCodeForInstr(MI);
1178 // Set the conditional execution predicate
1179 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1184 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1186 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1187 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1189 // Two register operand form.
1191 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1194 Binary |= getMachineOpValue(MI, MO2);
1197 Binary |= getMachineOpValue(MI, MO1);
1200 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1201 if (MI.getOperand(OpIdx).isImm() &&
1202 !TID.OpInfo[OpIdx].isPredicate() &&
1203 !TID.OpInfo[OpIdx].isOptionalDef())
1204 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1209 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1210 const TargetInstrDesc &TID = MI.getDesc();
1212 // Part of binary is determined by TableGn.
1213 unsigned Binary = getBinaryCodeForInstr(MI);
1215 // Set the conditional execution predicate
1216 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1221 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1223 const MachineOperand &MO = MI.getOperand(OpIdx++);
1224 if (OpIdx == TID.getNumOperands() ||
1225 TID.OpInfo[OpIdx].isPredicate() ||
1226 TID.OpInfo[OpIdx].isOptionalDef()) {
1227 // Encode Rm and it's done.
1228 Binary |= getMachineOpValue(MI, MO);
1234 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1237 Binary |= getMachineOpValue(MI, OpIdx++);
1239 // Encode shift_imm.
1240 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1241 if (TID.Opcode == ARM::PKHTB) {
1242 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1246 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1247 Binary |= ShiftAmt << ARMII::ShiftShift;
1252 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1253 const TargetInstrDesc &TID = MI.getDesc();
1255 // Part of binary is determined by TableGen.
1256 unsigned Binary = getBinaryCodeForInstr(MI);
1258 // Set the conditional execution predicate
1259 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1262 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1264 // Encode saturate bit position.
1265 unsigned Pos = MI.getOperand(1).getImm();
1266 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1268 assert((Pos < 16 || (Pos < 32 &&
1269 TID.Opcode != ARM::SSAT16 &&
1270 TID.Opcode != ARM::USAT16)) &&
1271 "saturate bit position out of range");
1272 Binary |= Pos << 16;
1275 Binary |= getMachineOpValue(MI, 2);
1277 // Encode shift_imm.
1278 if (TID.getNumOperands() == 4) {
1279 unsigned ShiftOp = MI.getOperand(3).getImm();
1280 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1281 if (Opc == ARM_AM::asr)
1283 unsigned ShiftAmt = MI.getOperand(3).getImm();
1284 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1286 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1287 Binary |= ShiftAmt << ARMII::ShiftShift;
1293 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1294 const TargetInstrDesc &TID = MI.getDesc();
1296 if (TID.Opcode == ARM::TPsoft) {
1297 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1300 // Part of binary is determined by TableGn.
1301 unsigned Binary = getBinaryCodeForInstr(MI);
1303 // Set the conditional execution predicate
1304 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1306 // Set signed_immed_24 field
1307 Binary |= getMachineOpValue(MI, 0);
1312 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1313 // Remember the base address of the inline jump table.
1314 uintptr_t JTBase = MCE.getCurrentPCValue();
1315 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1316 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1319 // Now emit the jump table entries.
1320 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1321 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1323 // DestBB address - JT base.
1324 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1326 // Absolute DestBB address.
1327 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1332 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1333 const TargetInstrDesc &TID = MI.getDesc();
1335 // Handle jump tables.
1336 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1337 // First emit a ldr pc, [] instruction.
1338 emitDataProcessingInstruction(MI, ARM::PC);
1340 // Then emit the inline jump table.
1342 (TID.Opcode == ARM::BR_JTr)
1343 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1344 emitInlineJumpTable(JTIndex);
1346 } else if (TID.Opcode == ARM::BR_JTm) {
1347 // First emit a ldr pc, [] instruction.
1348 emitLoadStoreInstruction(MI, ARM::PC);
1350 // Then emit the inline jump table.
1351 emitInlineJumpTable(MI.getOperand(3).getIndex());
1355 // Part of binary is determined by TableGn.
1356 unsigned Binary = getBinaryCodeForInstr(MI);
1358 // Set the conditional execution predicate
1359 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1361 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1362 // The return register is LR.
1363 Binary |= getARMRegisterNumbering(ARM::LR);
1365 // otherwise, set the return register
1366 Binary |= getMachineOpValue(MI, 0);
1371 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1372 unsigned RegD = MI.getOperand(OpIdx).getReg();
1373 unsigned Binary = 0;
1374 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1375 RegD = getARMRegisterNumbering(RegD);
1377 Binary |= RegD << ARMII::RegRdShift;
1379 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1380 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1385 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1386 unsigned RegN = MI.getOperand(OpIdx).getReg();
1387 unsigned Binary = 0;
1388 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1389 RegN = getARMRegisterNumbering(RegN);
1391 Binary |= RegN << ARMII::RegRnShift;
1393 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1394 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1399 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1400 unsigned RegM = MI.getOperand(OpIdx).getReg();
1401 unsigned Binary = 0;
1402 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1403 RegM = getARMRegisterNumbering(RegM);
1407 Binary |= ((RegM & 0x1E) >> 1);
1408 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1413 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1414 const TargetInstrDesc &TID = MI.getDesc();
1416 // Part of binary is determined by TableGn.
1417 unsigned Binary = getBinaryCodeForInstr(MI);
1419 // Set the conditional execution predicate
1420 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1423 assert((Binary & ARMII::D_BitShift) == 0 &&
1424 (Binary & ARMII::N_BitShift) == 0 &&
1425 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1428 Binary |= encodeVFPRd(MI, OpIdx++);
1430 // If this is a two-address operand, skip it, e.g. FMACD.
1431 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1435 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1436 Binary |= encodeVFPRn(MI, OpIdx++);
1438 if (OpIdx == TID.getNumOperands() ||
1439 TID.OpInfo[OpIdx].isPredicate() ||
1440 TID.OpInfo[OpIdx].isOptionalDef()) {
1441 // FCMPEZD etc. has only one operand.
1447 Binary |= encodeVFPRm(MI, OpIdx);
1452 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1453 const TargetInstrDesc &TID = MI.getDesc();
1454 unsigned Form = TID.TSFlags & ARMII::FormMask;
1456 // Part of binary is determined by TableGn.
1457 unsigned Binary = getBinaryCodeForInstr(MI);
1459 // Set the conditional execution predicate
1460 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1464 case ARMII::VFPConv1Frm:
1465 case ARMII::VFPConv2Frm:
1466 case ARMII::VFPConv3Frm:
1468 Binary |= encodeVFPRd(MI, 0);
1470 case ARMII::VFPConv4Frm:
1472 Binary |= encodeVFPRn(MI, 0);
1474 case ARMII::VFPConv5Frm:
1476 Binary |= encodeVFPRm(MI, 0);
1482 case ARMII::VFPConv1Frm:
1484 Binary |= encodeVFPRm(MI, 1);
1486 case ARMII::VFPConv2Frm:
1487 case ARMII::VFPConv3Frm:
1489 Binary |= encodeVFPRn(MI, 1);
1491 case ARMII::VFPConv4Frm:
1492 case ARMII::VFPConv5Frm:
1494 Binary |= encodeVFPRd(MI, 1);
1498 if (Form == ARMII::VFPConv5Frm)
1500 Binary |= encodeVFPRn(MI, 2);
1501 else if (Form == ARMII::VFPConv3Frm)
1503 Binary |= encodeVFPRm(MI, 2);
1508 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1509 // Part of binary is determined by TableGn.
1510 unsigned Binary = getBinaryCodeForInstr(MI);
1512 // Set the conditional execution predicate
1513 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1518 Binary |= encodeVFPRd(MI, OpIdx++);
1520 // Encode address base.
1521 const MachineOperand &Base = MI.getOperand(OpIdx++);
1522 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1524 // If there is a non-zero immediate offset, encode it.
1526 const MachineOperand &Offset = MI.getOperand(OpIdx);
1527 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1528 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1529 Binary |= 1 << ARMII::U_BitShift;
1536 // If immediate offset is omitted, default to +0.
1537 Binary |= 1 << ARMII::U_BitShift;
1543 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1544 const TargetInstrDesc &TID = MI.getDesc();
1545 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1547 // Part of binary is determined by TableGn.
1548 unsigned Binary = getBinaryCodeForInstr(MI);
1550 // Set the conditional execution predicate
1551 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1553 // Skip operand 0 of an instruction with base register update.
1558 // Set base address operand
1559 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1561 // Set addressing mode by modifying bits U(23) and P(24)
1562 const MachineOperand &MO = MI.getOperand(OpIdx++);
1563 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1567 Binary |= 0x1 << ARMII::W_BitShift;
1569 // First register is encoded in Dd.
1570 Binary |= encodeVFPRd(MI, OpIdx+2);
1572 // Count the number of registers.
1573 unsigned NumRegs = 1;
1574 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1575 const MachineOperand &MO = MI.getOperand(i);
1576 if (!MO.isReg() || MO.isImplicit())
1580 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1581 // Otherwise, it will be 0, in the case of 32-bit registers.
1583 Binary |= NumRegs * 2;
1590 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1591 unsigned Opcode = MI.getDesc().Opcode;
1592 // Part of binary is determined by TableGn.
1593 unsigned Binary = getBinaryCodeForInstr(MI);
1595 // Set the conditional execution predicate
1596 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1600 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1603 // No further encoding needed.
1607 case ARM::FCONSTS: {
1609 Binary |= encodeVFPRd(MI, 0);
1611 // Encode imm., Table A7-18 VFP modified immediate constants
1612 const MachineOperand &MO1 = MI.getOperand(1);
1613 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1614 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1615 unsigned ModifiedImm;
1617 if(Opcode == ARM::FCONSTS)
1618 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1619 (Imm & 0x03F80000) >> 19; // bcdefgh
1620 else // Opcode == ARM::FCONSTD
1621 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1622 (Imm & 0x007F0000) >> 16; // bcdefgh
1624 // Insts{19-16} = abcd, Insts{3-0} = efgh
1625 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1626 Binary |= (ModifiedImm & 0xF);
1634 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1635 unsigned RegD = MI.getOperand(OpIdx).getReg();
1636 unsigned Binary = 0;
1637 RegD = getARMRegisterNumbering(RegD);
1638 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1639 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1643 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1644 unsigned RegN = MI.getOperand(OpIdx).getReg();
1645 unsigned Binary = 0;
1646 RegN = getARMRegisterNumbering(RegN);
1647 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1648 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1652 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1653 unsigned RegM = MI.getOperand(OpIdx).getReg();
1654 unsigned Binary = 0;
1655 RegM = getARMRegisterNumbering(RegM);
1656 Binary |= (RegM & 0xf);
1657 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1661 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1662 /// data-processing instruction to the corresponding Thumb encoding.
1663 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1664 assert((Binary & 0xfe000000) == 0xf2000000 &&
1665 "not an ARM NEON data-processing instruction");
1666 unsigned UBit = (Binary >> 24) & 1;
1667 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1670 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1671 unsigned Binary = getBinaryCodeForInstr(MI);
1673 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1674 const TargetInstrDesc &TID = MI.getDesc();
1675 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1679 } else { // ARMII::NSetLnFrm
1685 // Set the conditional execution predicate
1686 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1688 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1689 RegT = getARMRegisterNumbering(RegT);
1690 Binary |= (RegT << ARMII::RegRdShift);
1691 Binary |= encodeNEONRn(MI, RegNOpIdx);
1694 if ((Binary & (1 << 22)) != 0)
1695 LaneShift = 0; // 8-bit elements
1696 else if ((Binary & (1 << 5)) != 0)
1697 LaneShift = 1; // 16-bit elements
1699 LaneShift = 2; // 32-bit elements
1701 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1702 unsigned Opc1 = Lane >> 2;
1703 unsigned Opc2 = Lane & 3;
1704 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1705 Binary |= (Opc1 << 21);
1706 Binary |= (Opc2 << 5);
1711 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1712 unsigned Binary = getBinaryCodeForInstr(MI);
1714 // Set the conditional execution predicate
1715 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1717 unsigned RegT = MI.getOperand(1).getReg();
1718 RegT = getARMRegisterNumbering(RegT);
1719 Binary |= (RegT << ARMII::RegRdShift);
1720 Binary |= encodeNEONRn(MI, 0);
1724 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1725 unsigned Binary = getBinaryCodeForInstr(MI);
1726 // Destination register is encoded in Dd.
1727 Binary |= encodeNEONRd(MI, 0);
1728 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1729 unsigned Imm = MI.getOperand(1).getImm();
1730 unsigned Op = (Imm >> 12) & 1;
1731 unsigned Cmode = (Imm >> 8) & 0xf;
1732 unsigned I = (Imm >> 7) & 1;
1733 unsigned Imm3 = (Imm >> 4) & 0x7;
1734 unsigned Imm4 = Imm & 0xf;
1735 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1737 Binary = convertNEONDataProcToThumb(Binary);
1741 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1742 const TargetInstrDesc &TID = MI.getDesc();
1743 unsigned Binary = getBinaryCodeForInstr(MI);
1744 // Destination register is encoded in Dd; source register in Dm.
1746 Binary |= encodeNEONRd(MI, OpIdx++);
1747 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1749 Binary |= encodeNEONRm(MI, OpIdx);
1751 Binary = convertNEONDataProcToThumb(Binary);
1752 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1756 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1757 const TargetInstrDesc &TID = MI.getDesc();
1758 unsigned Binary = getBinaryCodeForInstr(MI);
1759 // Destination register is encoded in Dd; source registers in Dn and Dm.
1761 Binary |= encodeNEONRd(MI, OpIdx++);
1762 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1764 Binary |= encodeNEONRn(MI, OpIdx++);
1765 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1767 Binary |= encodeNEONRm(MI, OpIdx);
1769 Binary = convertNEONDataProcToThumb(Binary);
1770 // FIXME: This does not handle VMOVDneon or VMOVQ.
1774 #include "ARMGenCodeEmitter.inc"