1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const MCInstrDesc &MCID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const MCInstrDesc &MCID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
202 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
204 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
206 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
208 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
210 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
212 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
214 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
216 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
218 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
220 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
222 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
224 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
226 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
228 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
231 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
233 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
235 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
236 unsigned Op) const { return 0; }
237 unsigned getMsbOpValue(const MachineInstr &MI,
238 unsigned Op) const { return 0; }
239 unsigned getSsatBitPosValue(const MachineInstr &MI,
240 unsigned Op) const { return 0; }
241 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
243 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
246 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
249 // {12} = (U)nsigned (add == '1', sub == '0')
251 const MachineOperand &MO = MI.getOperand(Op);
252 const MachineOperand &MO1 = MI.getOperand(Op + 1);
254 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
257 unsigned Reg = getARMRegisterNumbering(MO.getReg());
258 int32_t Imm12 = MO1.getImm();
260 Binary = Imm12 & 0xfff;
263 Binary |= (Reg << 13);
267 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
271 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
273 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
275 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
277 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
279 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
281 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
283 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
285 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
287 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
289 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
291 // {12} = (U)nsigned (add == '1', sub == '0')
293 const MachineOperand &MO = MI.getOperand(Op);
294 const MachineOperand &MO1 = MI.getOperand(Op + 1);
296 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
299 unsigned Reg = getARMRegisterNumbering(MO.getReg());
300 int32_t Imm12 = MO1.getImm();
302 // Special value for #-0
303 if (Imm12 == INT32_MIN)
306 // Immediate is always encoded as positive. The 'U' bit controls add vs
314 uint32_t Binary = Imm12 & 0xfff;
317 Binary |= (Reg << 13);
320 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
323 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
326 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
328 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
330 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
332 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
335 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
336 /// machine operand requires relocation, record the relocation and return
338 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
341 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
343 unsigned getShiftOp(unsigned Imm) const ;
345 /// Routines that handle operands which add machine relocations which are
346 /// fixed up by the relocation stage.
347 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
348 bool MayNeedFarStub, bool Indirect,
349 intptr_t ACPV = 0) const;
350 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
351 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
352 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
353 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
354 intptr_t JTBase = 0) const;
358 char ARMCodeEmitter::ID = 0;
360 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
361 /// code to the specified MCE object.
362 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
363 JITCodeEmitter &JCE) {
364 return new ARMCodeEmitter(TM, JCE);
367 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
368 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
369 MF.getTarget().getRelocationModel() != Reloc::Static) &&
370 "JIT relocation model must be set to static or default!");
371 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
372 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
373 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
374 Subtarget = &TM.getSubtarget<ARMSubtarget>();
375 MCPEs = &MF.getConstantPool()->getConstants();
377 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
378 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
379 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
380 JTI->Initialize(MF, IsPIC);
381 MMI = &getAnalysis<MachineModuleInfo>();
382 MCE.setModuleInfo(MMI);
385 DEBUG(errs() << "JITTing function '"
386 << MF.getFunction()->getName() << "'\n");
387 MCE.startFunction(MF);
388 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
390 MCE.StartMachineBasicBlock(MBB);
391 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
395 } while (MCE.finishFunction(MF));
400 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
402 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
403 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
404 default: llvm_unreachable("Unknown shift opc!");
405 case ARM_AM::asr: return 2;
406 case ARM_AM::lsl: return 0;
407 case ARM_AM::lsr: return 1;
409 case ARM_AM::rrx: return 3;
414 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
415 /// machine operand requires relocation, record the relocation and return zero.
416 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
417 const MachineOperand &MO,
419 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
420 && "Relocation to this function should be for movt or movw");
423 return static_cast<unsigned>(MO.getImm());
424 else if (MO.isGlobal())
425 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
426 else if (MO.isSymbol())
427 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
429 emitMachineBasicBlock(MO.getMBB(), Reloc);
434 llvm_unreachable("Unsupported operand type for movw/movt");
439 /// getMachineOpValue - Return binary encoding of operand. If the machine
440 /// operand requires relocation, record the relocation and return zero.
441 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
442 const MachineOperand &MO) const {
444 return getARMRegisterNumbering(MO.getReg());
446 return static_cast<unsigned>(MO.getImm());
447 else if (MO.isGlobal())
448 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
449 else if (MO.isSymbol())
450 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
451 else if (MO.isCPI()) {
452 const MCInstrDesc &MCID = MI.getDesc();
453 // For VFP load, the immediate offset is multiplied by 4.
454 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
455 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
456 emitConstPoolAddress(MO.getIndex(), Reloc);
457 } else if (MO.isJTI())
458 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
460 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
462 llvm_unreachable("Unable to encode MachineOperand!");
466 /// emitGlobalAddress - Emit the specified address to the code stream.
468 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
469 bool MayNeedFarStub, bool Indirect,
470 intptr_t ACPV) const {
471 MachineRelocation MR = Indirect
472 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
473 const_cast<GlobalValue *>(GV),
474 ACPV, MayNeedFarStub)
475 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
476 const_cast<GlobalValue *>(GV), ACPV,
478 MCE.addRelocation(MR);
481 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
482 /// be emitted to the current location in the function, and allow it to be PC
484 void ARMCodeEmitter::
485 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
486 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
490 /// emitConstPoolAddress - Arrange for the address of an constant pool
491 /// to be emitted to the current location in the function, and allow it to be PC
493 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
494 // Tell JIT emitter we'll resolve the address.
495 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
496 Reloc, CPI, 0, true));
499 /// emitJumpTableAddress - Arrange for the address of a jump table to
500 /// be emitted to the current location in the function, and allow it to be PC
502 void ARMCodeEmitter::
503 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
504 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
505 Reloc, JTIndex, 0, true));
508 /// emitMachineBasicBlock - Emit the specified address basic block.
509 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
511 intptr_t JTBase) const {
512 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
516 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
517 DEBUG(errs() << " 0x";
518 errs().write_hex(Binary) << "\n");
519 MCE.emitWordLE(Binary);
522 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
523 DEBUG(errs() << " 0x";
524 errs().write_hex(Binary) << "\n");
525 MCE.emitDWordLE(Binary);
528 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
529 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
531 MCE.processDebugLoc(MI.getDebugLoc(), true);
533 ++NumEmitted; // Keep track of the # of mi's emitted
534 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
536 llvm_unreachable("Unhandled instruction encoding format!");
540 if (MI.getOpcode() == ARM::LEApcrelJT) {
541 // Materialize jumptable address.
542 emitLEApcrelJTInstruction(MI);
545 llvm_unreachable("Unhandled instruction encoding!");
548 emitPseudoInstruction(MI);
551 case ARMII::DPSoRegFrm:
552 emitDataProcessingInstruction(MI);
556 emitLoadStoreInstruction(MI);
558 case ARMII::LdMiscFrm:
559 case ARMII::StMiscFrm:
560 emitMiscLoadStoreInstruction(MI);
562 case ARMII::LdStMulFrm:
563 emitLoadStoreMultipleInstruction(MI);
566 emitMulFrmInstruction(MI);
569 emitExtendInstruction(MI);
571 case ARMII::ArithMiscFrm:
572 emitMiscArithInstruction(MI);
575 emitSaturateInstruction(MI);
578 emitBranchInstruction(MI);
580 case ARMII::BrMiscFrm:
581 emitMiscBranchInstruction(MI);
584 case ARMII::VFPUnaryFrm:
585 case ARMII::VFPBinaryFrm:
586 emitVFPArithInstruction(MI);
588 case ARMII::VFPConv1Frm:
589 case ARMII::VFPConv2Frm:
590 case ARMII::VFPConv3Frm:
591 case ARMII::VFPConv4Frm:
592 case ARMII::VFPConv5Frm:
593 emitVFPConversionInstruction(MI);
595 case ARMII::VFPLdStFrm:
596 emitVFPLoadStoreInstruction(MI);
598 case ARMII::VFPLdStMulFrm:
599 emitVFPLoadStoreMultipleInstruction(MI);
602 // NEON instructions.
603 case ARMII::NGetLnFrm:
604 case ARMII::NSetLnFrm:
605 emitNEONLaneInstruction(MI);
608 emitNEONDupInstruction(MI);
610 case ARMII::N1RegModImmFrm:
611 emitNEON1RegModImmInstruction(MI);
613 case ARMII::N2RegFrm:
614 emitNEON2RegInstruction(MI);
616 case ARMII::N3RegFrm:
617 emitNEON3RegInstruction(MI);
620 MCE.processDebugLoc(MI.getDebugLoc(), false);
623 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
624 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
625 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
626 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
628 // Remember the CONSTPOOL_ENTRY address for later relocation.
629 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
631 // Emit constpool island entry. In most cases, the actual values will be
632 // resolved and relocated after code emission.
633 if (MCPE.isMachineConstantPoolEntry()) {
634 ARMConstantPoolValue *ACPV =
635 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
637 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
638 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
640 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
641 const GlobalValue *GV = ACPV->getGV();
643 Reloc::Model RelocM = TM.getRelocationModel();
644 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
646 Subtarget->GVIsIndirectSymbol(GV, RelocM),
649 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
653 const Constant *CV = MCPE.Val.ConstVal;
656 errs() << " ** Constant pool #" << CPI << " @ "
657 << (void*)MCE.getCurrentPCValue() << " ";
658 if (const Function *F = dyn_cast<Function>(CV))
659 errs() << F->getName();
665 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
666 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
668 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
669 uint32_t Val = uint32_t(*CI->getValue().getRawData());
671 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
672 if (CFP->getType()->isFloatTy())
673 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
674 else if (CFP->getType()->isDoubleTy())
675 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
677 llvm_unreachable("Unable to handle this constantpool entry!");
680 llvm_unreachable("Unable to handle this constantpool entry!");
685 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
686 const MachineOperand &MO0 = MI.getOperand(0);
687 const MachineOperand &MO1 = MI.getOperand(1);
689 // Emit the 'movw' instruction.
690 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
692 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
694 // Set the conditional execution predicate.
695 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
698 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
700 // Encode imm16 as imm4:imm12
701 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
702 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
705 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
706 // Emit the 'movt' instruction.
707 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
709 // Set the conditional execution predicate.
710 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
713 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
715 // Encode imm16 as imm4:imm1, same as movw above.
716 Binary |= Hi16 & 0xFFF;
717 Binary |= ((Hi16 >> 12) & 0xF) << 16;
721 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
722 const MachineOperand &MO0 = MI.getOperand(0);
723 const MachineOperand &MO1 = MI.getOperand(1);
724 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
725 "Not a valid so_imm value!");
726 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
727 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
729 // Emit the 'mov' instruction.
730 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
732 // Set the conditional execution predicate.
733 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
736 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
739 // Set bit I(25) to identify this is the immediate form of <shifter_op>
740 Binary |= 1 << ARMII::I_BitShift;
741 Binary |= getMachineSoImmOpValue(V1);
744 // Now the 'orr' instruction.
745 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
747 // Set the conditional execution predicate.
748 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
751 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
754 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
757 // Set bit I(25) to identify this is the immediate form of <shifter_op>
758 Binary |= 1 << ARMII::I_BitShift;
759 Binary |= getMachineSoImmOpValue(V2);
763 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
764 // It's basically add r, pc, (LJTI - $+8)
766 const MCInstrDesc &MCID = MI.getDesc();
768 // Emit the 'add' instruction.
769 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
771 // Set the conditional execution predicate
772 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
774 // Encode S bit if MI modifies CPSR.
775 Binary |= getAddrModeSBit(MI, MCID);
778 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
780 // Encode Rn which is PC.
781 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
783 // Encode the displacement.
784 Binary |= 1 << ARMII::I_BitShift;
785 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
790 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
791 unsigned Opcode = MI.getDesc().Opcode;
793 // Part of binary is determined by TableGn.
794 unsigned Binary = getBinaryCodeForInstr(MI);
796 // Set the conditional execution predicate
797 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
799 // Encode S bit if MI modifies CPSR.
800 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
801 Binary |= 1 << ARMII::S_BitShift;
803 // Encode register def if there is one.
804 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
806 // Encode the shift operation.
813 case ARM::MOVsrl_flag:
815 Binary |= (0x2 << 4) | (1 << 7);
817 case ARM::MOVsra_flag:
819 Binary |= (0x4 << 4) | (1 << 7);
823 // Encode register Rm.
824 Binary |= getMachineOpValue(MI, 1);
829 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
830 DEBUG(errs() << " ** LPC" << LabelID << " @ "
831 << (void*)MCE.getCurrentPCValue() << '\n');
832 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
835 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
836 unsigned Opcode = MI.getDesc().Opcode;
839 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
841 case ARM::BMOVPCRX_CALL:
843 case ARM::BMOVPCRXr9_CALL: {
844 // First emit mov lr, pc
845 unsigned Binary = 0x01a0e00f;
846 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
849 // and then emit the branch.
850 emitMiscBranchInstruction(MI);
853 case TargetOpcode::INLINEASM: {
854 // We allow inline assembler nodes with empty bodies - they can
855 // implicitly define registers, which is ok for JIT.
856 if (MI.getOperand(0).getSymbolName()[0]) {
857 report_fatal_error("JIT does not support inline asm!");
861 case TargetOpcode::PROLOG_LABEL:
862 case TargetOpcode::EH_LABEL:
863 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
865 case TargetOpcode::IMPLICIT_DEF:
866 case TargetOpcode::KILL:
869 case ARM::CONSTPOOL_ENTRY:
870 emitConstPoolInstruction(MI);
873 // Remember of the address of the PC label for relocation later.
874 addPCLabel(MI.getOperand(2).getImm());
875 // PICADD is just an add instruction that implicitly read pc.
876 emitDataProcessingInstruction(MI, 0, ARM::PC);
883 // Remember of the address of the PC label for relocation later.
884 addPCLabel(MI.getOperand(2).getImm());
885 // These are just load / store instructions that implicitly read pc.
886 emitLoadStoreInstruction(MI, 0, ARM::PC);
893 // Remember of the address of the PC label for relocation later.
894 addPCLabel(MI.getOperand(2).getImm());
895 // These are just load / store instructions that implicitly read pc.
896 emitMiscLoadStoreInstruction(MI, ARM::PC);
901 // Two instructions to materialize a constant.
902 if (Subtarget->hasV6T2Ops())
903 emitMOVi32immInstruction(MI);
905 emitMOVi2piecesInstruction(MI);
908 case ARM::LEApcrelJT:
909 // Materialize jumptable address.
910 emitLEApcrelJTInstruction(MI);
913 case ARM::MOVsrl_flag:
914 case ARM::MOVsra_flag:
915 emitPseudoMoveInstruction(MI);
920 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
921 const MCInstrDesc &MCID,
922 const MachineOperand &MO,
924 unsigned Binary = getMachineOpValue(MI, MO);
926 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
927 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
928 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
930 // Encode the shift opcode.
932 unsigned Rs = MO1.getReg();
934 // Set shift operand (bit[7:4]).
939 // RRX - 0110 and bit[11:8] clear.
941 default: llvm_unreachable("Unknown shift opc!");
942 case ARM_AM::lsl: SBits = 0x1; break;
943 case ARM_AM::lsr: SBits = 0x3; break;
944 case ARM_AM::asr: SBits = 0x5; break;
945 case ARM_AM::ror: SBits = 0x7; break;
946 case ARM_AM::rrx: SBits = 0x6; break;
949 // Set shift operand (bit[6:4]).
955 default: llvm_unreachable("Unknown shift opc!");
956 case ARM_AM::lsl: SBits = 0x0; break;
957 case ARM_AM::lsr: SBits = 0x2; break;
958 case ARM_AM::asr: SBits = 0x4; break;
959 case ARM_AM::ror: SBits = 0x6; break;
962 Binary |= SBits << 4;
963 if (SOpc == ARM_AM::rrx)
966 // Encode the shift operation Rs or shift_imm (except rrx).
968 // Encode Rs bit[11:8].
969 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
970 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
973 // Encode shift_imm bit[11:7].
974 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
977 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
978 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
979 assert(SoImmVal != -1 && "Not a valid so_imm value!");
981 // Encode rotate_imm.
982 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
983 << ARMII::SoRotImmShift;
986 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
990 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
991 const MCInstrDesc &MCID) const {
992 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
993 const MachineOperand &MO = MI.getOperand(i-1);
994 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
995 return 1 << ARMII::S_BitShift;
1000 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1001 unsigned ImplicitRd,
1002 unsigned ImplicitRn) {
1003 const MCInstrDesc &MCID = MI.getDesc();
1005 // Part of binary is determined by TableGn.
1006 unsigned Binary = getBinaryCodeForInstr(MI);
1008 // Set the conditional execution predicate
1009 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1011 // Encode S bit if MI modifies CPSR.
1012 Binary |= getAddrModeSBit(MI, MCID);
1014 // Encode register def if there is one.
1015 unsigned NumDefs = MCID.getNumDefs();
1018 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1019 else if (ImplicitRd)
1020 // Special handling for implicit use (e.g. PC).
1021 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1023 if (MCID.Opcode == ARM::MOVi16) {
1024 // Get immediate from MI.
1025 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1026 ARM::reloc_arm_movw);
1027 // Encode imm which is the same as in emitMOVi32immInstruction().
1028 Binary |= Lo16 & 0xFFF;
1029 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1032 } else if(MCID.Opcode == ARM::MOVTi16) {
1033 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1034 ARM::reloc_arm_movt) >> 16);
1035 Binary |= Hi16 & 0xFFF;
1036 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1039 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1040 uint32_t v = ~MI.getOperand(2).getImm();
1041 int32_t lsb = CountTrailingZeros_32(v);
1042 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1043 // Instr{20-16} = msb, Instr{11-7} = lsb
1044 Binary |= (msb & 0x1F) << 16;
1045 Binary |= (lsb & 0x1F) << 7;
1048 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1049 // Encode Rn in Instr{0-3}
1050 Binary |= getMachineOpValue(MI, OpIdx++);
1052 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1053 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1055 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1056 Binary |= (widthm1 & 0x1F) << 16;
1057 Binary |= (lsb & 0x1F) << 7;
1062 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1063 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1066 // Encode first non-shifter register operand if there is one.
1067 bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1070 // Special handling for implicit use (e.g. PC).
1071 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1073 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1078 // Encode shifter operand.
1079 const MachineOperand &MO = MI.getOperand(OpIdx);
1080 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1082 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1087 // Encode register Rm.
1088 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1093 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1098 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1099 unsigned ImplicitRd,
1100 unsigned ImplicitRn) {
1101 const MCInstrDesc &MCID = MI.getDesc();
1102 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1103 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1105 // Part of binary is determined by TableGn.
1106 unsigned Binary = getBinaryCodeForInstr(MI);
1108 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1109 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1110 MI.getOpcode() == ARM::STRi12) {
1115 // Set the conditional execution predicate
1116 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1120 // Operand 0 of a pre- and post-indexed store is the address base
1121 // writeback. Skip it.
1122 bool Skipped = false;
1123 if (IsPrePost && Form == ARMII::StFrm) {
1128 // Set first operand
1130 // Special handling for implicit use (e.g. PC).
1131 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1133 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1135 // Set second operand
1137 // Special handling for implicit use (e.g. PC).
1138 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1140 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1142 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1143 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1146 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1147 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1148 ? 0 : MI.getOperand(OpIdx+1).getImm();
1150 // Set bit U(23) according to sign of immed value (positive or negative).
1151 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1153 if (!MO2.getReg()) { // is immediate
1154 if (ARM_AM::getAM2Offset(AM2Opc))
1155 // Set the value of offset_12 field
1156 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1161 // Set bit I(25), because this is not in immediate encoding.
1162 Binary |= 1 << ARMII::I_BitShift;
1163 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1164 // Set bit[3:0] to the corresponding Rm register
1165 Binary |= getARMRegisterNumbering(MO2.getReg());
1167 // If this instr is in scaled register offset/index instruction, set
1168 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1169 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1170 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1171 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1177 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1178 unsigned ImplicitRn) {
1179 const MCInstrDesc &MCID = MI.getDesc();
1180 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1181 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1183 // Part of binary is determined by TableGn.
1184 unsigned Binary = getBinaryCodeForInstr(MI);
1186 // Set the conditional execution predicate
1187 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1191 // Operand 0 of a pre- and post-indexed store is the address base
1192 // writeback. Skip it.
1193 bool Skipped = false;
1194 if (IsPrePost && Form == ARMII::StMiscFrm) {
1199 // Set first operand
1200 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1202 // Skip LDRD and STRD's second operand.
1203 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1206 // Set second operand
1208 // Special handling for implicit use (e.g. PC).
1209 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1211 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1213 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1214 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1217 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1218 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1219 ? 0 : MI.getOperand(OpIdx+1).getImm();
1221 // Set bit U(23) according to sign of immed value (positive or negative)
1222 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1225 // If this instr is in register offset/index encoding, set bit[3:0]
1226 // to the corresponding Rm register.
1228 Binary |= getARMRegisterNumbering(MO2.getReg());
1233 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1234 Binary |= 1 << ARMII::AM3_I_BitShift;
1235 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1237 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1238 Binary |= (ImmOffs & 0xF); // immedL
1244 static unsigned getAddrModeUPBits(unsigned Mode) {
1245 unsigned Binary = 0;
1247 // Set addressing mode by modifying bits U(23) and P(24)
1248 // IA - Increment after - bit U = 1 and bit P = 0
1249 // IB - Increment before - bit U = 1 and bit P = 1
1250 // DA - Decrement after - bit U = 0 and bit P = 0
1251 // DB - Decrement before - bit U = 0 and bit P = 1
1253 default: llvm_unreachable("Unknown addressing sub-mode!");
1254 case ARM_AM::da: break;
1255 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1256 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1257 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1263 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1264 const MCInstrDesc &MCID = MI.getDesc();
1265 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1267 // Part of binary is determined by TableGn.
1268 unsigned Binary = getBinaryCodeForInstr(MI);
1270 // Set the conditional execution predicate
1271 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1273 // Skip operand 0 of an instruction with base register update.
1278 // Set base address operand
1279 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1281 // Set addressing mode by modifying bits U(23) and P(24)
1282 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1283 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1287 Binary |= 0x1 << ARMII::W_BitShift;
1290 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1291 const MachineOperand &MO = MI.getOperand(i);
1292 if (!MO.isReg() || MO.isImplicit())
1294 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1295 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1297 Binary |= 0x1 << RegNum;
1303 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1304 const MCInstrDesc &MCID = MI.getDesc();
1306 // Part of binary is determined by TableGn.
1307 unsigned Binary = getBinaryCodeForInstr(MI);
1309 // Set the conditional execution predicate
1310 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1312 // Encode S bit if MI modifies CPSR.
1313 Binary |= getAddrModeSBit(MI, MCID);
1315 // 32x32->64bit operations have two destination registers. The number
1316 // of register definitions will tell us if that's what we're dealing with.
1318 if (MCID.getNumDefs() == 2)
1319 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1322 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1325 Binary |= getMachineOpValue(MI, OpIdx++);
1328 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1330 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1331 // it as Rn (for multiply, that's in the same offset as RdLo.
1332 if (MCID.getNumOperands() > OpIdx &&
1333 !MCID.OpInfo[OpIdx].isPredicate() &&
1334 !MCID.OpInfo[OpIdx].isOptionalDef())
1335 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1340 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1341 const MCInstrDesc &MCID = MI.getDesc();
1343 // Part of binary is determined by TableGn.
1344 unsigned Binary = getBinaryCodeForInstr(MI);
1346 // Set the conditional execution predicate
1347 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1352 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1354 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1355 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1357 // Two register operand form.
1359 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1362 Binary |= getMachineOpValue(MI, MO2);
1365 Binary |= getMachineOpValue(MI, MO1);
1368 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1369 if (MI.getOperand(OpIdx).isImm() &&
1370 !MCID.OpInfo[OpIdx].isPredicate() &&
1371 !MCID.OpInfo[OpIdx].isOptionalDef())
1372 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1377 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1378 const MCInstrDesc &MCID = MI.getDesc();
1380 // Part of binary is determined by TableGn.
1381 unsigned Binary = getBinaryCodeForInstr(MI);
1383 // Set the conditional execution predicate
1384 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1386 // PKH instructions are finished at this point
1387 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1395 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1397 const MachineOperand &MO = MI.getOperand(OpIdx++);
1398 if (OpIdx == MCID.getNumOperands() ||
1399 MCID.OpInfo[OpIdx].isPredicate() ||
1400 MCID.OpInfo[OpIdx].isOptionalDef()) {
1401 // Encode Rm and it's done.
1402 Binary |= getMachineOpValue(MI, MO);
1408 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1411 Binary |= getMachineOpValue(MI, OpIdx++);
1413 // Encode shift_imm.
1414 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1415 if (MCID.Opcode == ARM::PKHTB) {
1416 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1420 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1421 Binary |= ShiftAmt << ARMII::ShiftShift;
1426 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1427 const MCInstrDesc &MCID = MI.getDesc();
1429 // Part of binary is determined by TableGen.
1430 unsigned Binary = getBinaryCodeForInstr(MI);
1432 // Set the conditional execution predicate
1433 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1436 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1438 // Encode saturate bit position.
1439 unsigned Pos = MI.getOperand(1).getImm();
1440 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1442 assert((Pos < 16 || (Pos < 32 &&
1443 MCID.Opcode != ARM::SSAT16 &&
1444 MCID.Opcode != ARM::USAT16)) &&
1445 "saturate bit position out of range");
1446 Binary |= Pos << 16;
1449 Binary |= getMachineOpValue(MI, 2);
1451 // Encode shift_imm.
1452 if (MCID.getNumOperands() == 4) {
1453 unsigned ShiftOp = MI.getOperand(3).getImm();
1454 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1455 if (Opc == ARM_AM::asr)
1457 unsigned ShiftAmt = MI.getOperand(3).getImm();
1458 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1460 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1461 Binary |= ShiftAmt << ARMII::ShiftShift;
1467 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1468 const MCInstrDesc &MCID = MI.getDesc();
1470 if (MCID.Opcode == ARM::TPsoft) {
1471 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1474 // Part of binary is determined by TableGn.
1475 unsigned Binary = getBinaryCodeForInstr(MI);
1477 // Set the conditional execution predicate
1478 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1480 // Set signed_immed_24 field
1481 Binary |= getMachineOpValue(MI, 0);
1486 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1487 // Remember the base address of the inline jump table.
1488 uintptr_t JTBase = MCE.getCurrentPCValue();
1489 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1490 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1493 // Now emit the jump table entries.
1494 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1495 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1497 // DestBB address - JT base.
1498 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1500 // Absolute DestBB address.
1501 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1506 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1507 const MCInstrDesc &MCID = MI.getDesc();
1509 // Handle jump tables.
1510 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1511 // First emit a ldr pc, [] instruction.
1512 emitDataProcessingInstruction(MI, ARM::PC);
1514 // Then emit the inline jump table.
1516 (MCID.Opcode == ARM::BR_JTr)
1517 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1518 emitInlineJumpTable(JTIndex);
1520 } else if (MCID.Opcode == ARM::BR_JTm) {
1521 // First emit a ldr pc, [] instruction.
1522 emitLoadStoreInstruction(MI, ARM::PC);
1524 // Then emit the inline jump table.
1525 emitInlineJumpTable(MI.getOperand(3).getIndex());
1529 // Part of binary is determined by TableGn.
1530 unsigned Binary = getBinaryCodeForInstr(MI);
1532 // Set the conditional execution predicate
1533 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1535 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1536 // The return register is LR.
1537 Binary |= getARMRegisterNumbering(ARM::LR);
1539 // otherwise, set the return register
1540 Binary |= getMachineOpValue(MI, 0);
1545 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1546 unsigned RegD = MI.getOperand(OpIdx).getReg();
1547 unsigned Binary = 0;
1548 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1549 RegD = getARMRegisterNumbering(RegD);
1551 Binary |= RegD << ARMII::RegRdShift;
1553 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1554 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1559 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1560 unsigned RegN = MI.getOperand(OpIdx).getReg();
1561 unsigned Binary = 0;
1562 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1563 RegN = getARMRegisterNumbering(RegN);
1565 Binary |= RegN << ARMII::RegRnShift;
1567 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1568 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1573 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1574 unsigned RegM = MI.getOperand(OpIdx).getReg();
1575 unsigned Binary = 0;
1576 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1577 RegM = getARMRegisterNumbering(RegM);
1581 Binary |= ((RegM & 0x1E) >> 1);
1582 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1587 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1588 const MCInstrDesc &MCID = MI.getDesc();
1590 // Part of binary is determined by TableGn.
1591 unsigned Binary = getBinaryCodeForInstr(MI);
1593 // Set the conditional execution predicate
1594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1597 assert((Binary & ARMII::D_BitShift) == 0 &&
1598 (Binary & ARMII::N_BitShift) == 0 &&
1599 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1602 Binary |= encodeVFPRd(MI, OpIdx++);
1604 // If this is a two-address operand, skip it, e.g. FMACD.
1605 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1609 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1610 Binary |= encodeVFPRn(MI, OpIdx++);
1612 if (OpIdx == MCID.getNumOperands() ||
1613 MCID.OpInfo[OpIdx].isPredicate() ||
1614 MCID.OpInfo[OpIdx].isOptionalDef()) {
1615 // FCMPEZD etc. has only one operand.
1621 Binary |= encodeVFPRm(MI, OpIdx);
1626 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1627 const MCInstrDesc &MCID = MI.getDesc();
1628 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1630 // Part of binary is determined by TableGn.
1631 unsigned Binary = getBinaryCodeForInstr(MI);
1633 // Set the conditional execution predicate
1634 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1638 case ARMII::VFPConv1Frm:
1639 case ARMII::VFPConv2Frm:
1640 case ARMII::VFPConv3Frm:
1642 Binary |= encodeVFPRd(MI, 0);
1644 case ARMII::VFPConv4Frm:
1646 Binary |= encodeVFPRn(MI, 0);
1648 case ARMII::VFPConv5Frm:
1650 Binary |= encodeVFPRm(MI, 0);
1656 case ARMII::VFPConv1Frm:
1658 Binary |= encodeVFPRm(MI, 1);
1660 case ARMII::VFPConv2Frm:
1661 case ARMII::VFPConv3Frm:
1663 Binary |= encodeVFPRn(MI, 1);
1665 case ARMII::VFPConv4Frm:
1666 case ARMII::VFPConv5Frm:
1668 Binary |= encodeVFPRd(MI, 1);
1672 if (Form == ARMII::VFPConv5Frm)
1674 Binary |= encodeVFPRn(MI, 2);
1675 else if (Form == ARMII::VFPConv3Frm)
1677 Binary |= encodeVFPRm(MI, 2);
1682 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1683 // Part of binary is determined by TableGn.
1684 unsigned Binary = getBinaryCodeForInstr(MI);
1686 // Set the conditional execution predicate
1687 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1692 Binary |= encodeVFPRd(MI, OpIdx++);
1694 // Encode address base.
1695 const MachineOperand &Base = MI.getOperand(OpIdx++);
1696 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1698 // If there is a non-zero immediate offset, encode it.
1700 const MachineOperand &Offset = MI.getOperand(OpIdx);
1701 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1702 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1703 Binary |= 1 << ARMII::U_BitShift;
1710 // If immediate offset is omitted, default to +0.
1711 Binary |= 1 << ARMII::U_BitShift;
1717 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1718 const MCInstrDesc &MCID = MI.getDesc();
1719 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1721 // Part of binary is determined by TableGn.
1722 unsigned Binary = getBinaryCodeForInstr(MI);
1724 // Set the conditional execution predicate
1725 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1727 // Skip operand 0 of an instruction with base register update.
1732 // Set base address operand
1733 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1735 // Set addressing mode by modifying bits U(23) and P(24)
1736 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1737 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1741 Binary |= 0x1 << ARMII::W_BitShift;
1743 // First register is encoded in Dd.
1744 Binary |= encodeVFPRd(MI, OpIdx+2);
1746 // Count the number of registers.
1747 unsigned NumRegs = 1;
1748 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1749 const MachineOperand &MO = MI.getOperand(i);
1750 if (!MO.isReg() || MO.isImplicit())
1754 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1755 // Otherwise, it will be 0, in the case of 32-bit registers.
1757 Binary |= NumRegs * 2;
1764 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1765 unsigned RegD = MI.getOperand(OpIdx).getReg();
1766 unsigned Binary = 0;
1767 RegD = getARMRegisterNumbering(RegD);
1768 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1769 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1773 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1774 unsigned RegN = MI.getOperand(OpIdx).getReg();
1775 unsigned Binary = 0;
1776 RegN = getARMRegisterNumbering(RegN);
1777 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1778 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1782 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1783 unsigned RegM = MI.getOperand(OpIdx).getReg();
1784 unsigned Binary = 0;
1785 RegM = getARMRegisterNumbering(RegM);
1786 Binary |= (RegM & 0xf);
1787 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1791 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1792 /// data-processing instruction to the corresponding Thumb encoding.
1793 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1794 assert((Binary & 0xfe000000) == 0xf2000000 &&
1795 "not an ARM NEON data-processing instruction");
1796 unsigned UBit = (Binary >> 24) & 1;
1797 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1800 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1801 unsigned Binary = getBinaryCodeForInstr(MI);
1803 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1804 const MCInstrDesc &MCID = MI.getDesc();
1805 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1809 } else { // ARMII::NSetLnFrm
1815 // Set the conditional execution predicate
1816 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1818 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1819 RegT = getARMRegisterNumbering(RegT);
1820 Binary |= (RegT << ARMII::RegRdShift);
1821 Binary |= encodeNEONRn(MI, RegNOpIdx);
1824 if ((Binary & (1 << 22)) != 0)
1825 LaneShift = 0; // 8-bit elements
1826 else if ((Binary & (1 << 5)) != 0)
1827 LaneShift = 1; // 16-bit elements
1829 LaneShift = 2; // 32-bit elements
1831 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1832 unsigned Opc1 = Lane >> 2;
1833 unsigned Opc2 = Lane & 3;
1834 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1835 Binary |= (Opc1 << 21);
1836 Binary |= (Opc2 << 5);
1841 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1842 unsigned Binary = getBinaryCodeForInstr(MI);
1844 // Set the conditional execution predicate
1845 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1847 unsigned RegT = MI.getOperand(1).getReg();
1848 RegT = getARMRegisterNumbering(RegT);
1849 Binary |= (RegT << ARMII::RegRdShift);
1850 Binary |= encodeNEONRn(MI, 0);
1854 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1855 unsigned Binary = getBinaryCodeForInstr(MI);
1856 // Destination register is encoded in Dd.
1857 Binary |= encodeNEONRd(MI, 0);
1858 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1859 unsigned Imm = MI.getOperand(1).getImm();
1860 unsigned Op = (Imm >> 12) & 1;
1861 unsigned Cmode = (Imm >> 8) & 0xf;
1862 unsigned I = (Imm >> 7) & 1;
1863 unsigned Imm3 = (Imm >> 4) & 0x7;
1864 unsigned Imm4 = Imm & 0xf;
1865 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1867 Binary = convertNEONDataProcToThumb(Binary);
1871 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1872 const MCInstrDesc &MCID = MI.getDesc();
1873 unsigned Binary = getBinaryCodeForInstr(MI);
1874 // Destination register is encoded in Dd; source register in Dm.
1876 Binary |= encodeNEONRd(MI, OpIdx++);
1877 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1879 Binary |= encodeNEONRm(MI, OpIdx);
1881 Binary = convertNEONDataProcToThumb(Binary);
1882 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1886 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1887 const MCInstrDesc &MCID = MI.getDesc();
1888 unsigned Binary = getBinaryCodeForInstr(MI);
1889 // Destination register is encoded in Dd; source registers in Dn and Dm.
1891 Binary |= encodeNEONRd(MI, OpIdx++);
1892 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1894 Binary |= encodeNEONRn(MI, OpIdx++);
1895 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1897 Binary |= encodeNEONRm(MI, OpIdx);
1899 Binary = convertNEONDataProcToThumb(Binary);
1900 // FIXME: This does not handle VMOVDneon or VMOVQ.
1904 #include "ARMGenCodeEmitter.inc"