1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-emitter"
17 #include "ARMAddressingModes.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Compiler.h"
31 STATISTIC(NumEmitted, "Number of machine instructions emitted");
34 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
35 const ARMInstrInfo *II;
38 MachineCodeEmitter &MCE;
41 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
42 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
44 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
45 const ARMInstrInfo &ii, const TargetData &td)
46 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
49 bool runOnMachineFunction(MachineFunction &MF);
51 virtual const char *getPassName() const {
52 return "ARM Machine Code Emitter";
55 void emitInstruction(const MachineInstr &MI);
58 unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
59 const TargetInstrDesc &TID,
62 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
63 const TargetInstrDesc &TID,
66 unsigned getAddrMode1SBit(const MachineInstr &MI,
67 const TargetInstrDesc &TID) const;
69 unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
70 const TargetInstrDesc &TID,
72 unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
73 const TargetInstrDesc &TID,
75 unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
76 const TargetInstrDesc &TID,
78 unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
79 const TargetInstrDesc &TID,
82 /// getInstrBinary - Return binary encoding for the specified
83 /// machine instruction.
84 unsigned getInstrBinary(const MachineInstr &MI);
86 /// getBinaryCodeForInstr - This function, generated by the
87 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
88 /// machine instructions.
90 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
92 /// getMachineOpValue - Return binary encoding of operand. If the machine
93 /// operand requires relocation, record the relocation and return zero.
94 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
95 return getMachineOpValue(MI, MI.getOperand(OpIdx));
97 unsigned getMachineOpValue(const MachineInstr &MI,
98 const MachineOperand &MO);
100 /// getBaseOpcodeFor - Return the opcode value.
102 unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
103 return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
106 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
108 unsigned getShiftOp(const MachineOperand &MO) const ;
110 /// Routines that handle operands which add machine relocations which are
111 /// fixed up by the JIT fixup stage.
112 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
113 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
114 void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
115 int Disp = 0, unsigned PCAdj = 0 );
116 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
118 void emitGlobalConstant(const Constant *CV);
119 void emitMachineBasicBlock(MachineBasicBlock *BB);
121 char ARMCodeEmitter::ID = 0;
124 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
125 /// to the specified MCE object.
126 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
127 MachineCodeEmitter &MCE) {
128 return new ARMCodeEmitter(TM, MCE);
131 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
132 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
133 MF.getTarget().getRelocationModel() != Reloc::Static) &&
134 "JIT relocation model must be set to static or default!");
135 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
136 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
139 MCE.startFunction(MF);
140 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
142 MCE.StartMachineBasicBlock(MBB);
143 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
147 } while (MCE.finishFunction(MF));
152 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
154 unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
155 switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
156 default: assert(0 && "Unknown shift opc!");
157 case ARM_AM::asr: return 2;
158 case ARM_AM::lsl: return 0;
159 case ARM_AM::lsr: return 1;
161 case ARM_AM::rrx: return 3;
166 /// getMachineOpValue - Return binary encoding of operand. If the machine
167 /// operand requires relocation, record the relocation and return zero.
168 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
169 const MachineOperand &MO) {
171 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
172 else if (MO.isImmediate())
173 return static_cast<unsigned>(MO.getImm());
174 else if (MO.isGlobalAddress())
175 emitGlobalAddressForCall(MO.getGlobal(), false);
176 else if (MO.isExternalSymbol())
177 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
178 else if (MO.isConstantPoolIndex())
179 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
180 else if (MO.isJumpTableIndex())
181 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
182 else if (MO.isMachineBasicBlock())
183 emitMachineBasicBlock(MO.getMBB());
189 /// emitGlobalAddressForCall - Emit the specified address to the code stream
190 /// assuming this is part of a function call, which is PC relative.
192 void ARMCodeEmitter::emitGlobalAddressForCall(GlobalValue *GV,
193 bool DoesntNeedStub) {
194 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
195 ARM::reloc_arm_branch, GV, 0,
199 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
200 /// be emitted to the current location in the function, and allow it to be PC
202 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
203 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
207 /// emitConstPoolAddress - Arrange for the address of an constant pool
208 /// to be emitted to the current location in the function, and allow it to be PC
210 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
212 unsigned PCAdj /* = 0 */) {
213 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
217 /// emitJumpTableAddress - Arrange for the address of a jump table to
218 /// be emitted to the current location in the function, and allow it to be PC
220 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
221 unsigned PCAdj /* = 0 */) {
222 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
226 /// emitMachineBasicBlock - Emit the specified address basic block.
227 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
228 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
229 ARM::reloc_arm_branch, BB));
232 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
233 NumEmitted++; // Keep track of the # of mi's emitted
234 MCE.emitWordLE(getInstrBinary(MI));
237 unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
238 const TargetInstrDesc &TID,
240 switch (TID.TSFlags & ARMII::FormMask) {
242 assert(0 && "Unknown instruction subtype!");
244 case ARMII::Branch: {
245 // Set signed_immed_24 field
246 Binary |= getMachineOpValue(MI, 0);
248 // if it is a conditional branch, set cond field
249 if (TID.Opcode == ARM::Bcc) {
250 Binary &= 0x0FFFFFFF; // clear conditional field
251 Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
255 case ARMII::BranchMisc: {
256 // Set bit[19:8] to 0xFFF
257 Binary |= 0xfff << 8;
258 if (TID.Opcode == ARM::BX_RET)
259 Binary |= 0xe; // the return register is LR
261 // otherwise, set the return register
262 Binary |= getMachineOpValue(MI, 0);
270 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
271 const TargetInstrDesc &TID,
273 // Set last operand (register Rm)
274 unsigned Binary = getMachineOpValue(MI, OpIdx);
276 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
277 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
278 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
280 // Encode the shift opcode.
282 unsigned Rs = MO1.getReg();
284 // Set shift operand (bit[7:4]).
289 // RRX - 0110 and bit[11:8] clear.
291 default: assert(0 && "Unknown shift opc!");
292 case ARM_AM::lsl: SBits = 0x1; break;
293 case ARM_AM::lsr: SBits = 0x3; break;
294 case ARM_AM::asr: SBits = 0x5; break;
295 case ARM_AM::ror: SBits = 0x7; break;
296 case ARM_AM::rrx: SBits = 0x6; break;
299 // Set shift operand (bit[6:4]).
305 default: assert(0 && "Unknown shift opc!");
306 case ARM_AM::lsl: SBits = 0x0; break;
307 case ARM_AM::lsr: SBits = 0x2; break;
308 case ARM_AM::asr: SBits = 0x4; break;
309 case ARM_AM::ror: SBits = 0x6; break;
312 Binary |= SBits << 4;
313 if (SOpc == ARM_AM::rrx)
316 // Encode the shift operation Rs or shift_imm (except rrx).
318 // Encode Rs bit[11:8].
319 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
321 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
324 // Encode shift_imm bit[11:7].
325 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
328 unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
329 const TargetInstrDesc &TID) const {
330 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
331 const MachineOperand &MO = MI.getOperand(i-1);
332 if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
333 return 1 << ARMII::S_BitShift;
338 unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
339 const TargetInstrDesc &TID,
341 if (MI.getOpcode() == ARM::MOVi2pieces)
345 // Encode S bit if MI modifies CPSR.
346 Binary |= getAddrMode1SBit(MI, TID);
348 unsigned Format = TID.TSFlags & ARMII::FormMask;
349 // FIXME: Consolidate into a single bit.
350 bool isUnary = (Format == ARMII::DPRdMisc ||
351 Format == ARMII::DPRdIm ||
352 Format == ARMII::DPRdReg ||
353 Format == ARMII::DPRdSoReg ||
354 Format == ARMII::DPRnIm ||
355 Format == ARMII::DPRnReg ||
356 Format == ARMII::DPRnSoReg);
360 // Encode register def if there is one.
361 unsigned NumDefs = TID.getNumDefs();
363 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
367 // Encode first non-shifter register operand if ther is one.
369 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
373 // Encode shifter operand.
374 if (TID.getNumOperands() - OpIdx > 1)
376 return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
378 const MachineOperand &MO = MI.getOperand(OpIdx);
380 // Encode register Rm.
381 return Binary | getMachineOpValue(MI, NumDefs + 1);
384 // Set bit I(25) to identify this is the immediate form of <shifter_op>
385 Binary |= 1 << ARMII::I_BitShift;
386 unsigned SoImm = MO.getImm();
387 // Encode rotate_imm.
388 Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
390 Binary |= ARM_AM::getSOImmVal(SoImm);
394 unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
395 const TargetInstrDesc &TID,
398 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
400 // Set second operand
401 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
403 const MachineOperand &MO2 = MI.getOperand(2);
404 const MachineOperand &MO3 = MI.getOperand(3);
406 // Set bit U(23) according to signal of immed value (positive or negative).
407 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
409 if (!MO2.getReg()) { // is immediate
410 if (ARM_AM::getAM2Offset(MO3.getImm()))
411 // Set the value of offset_12 field
412 Binary |= ARM_AM::getAM2Offset(MO3.getImm());
416 // Set bit I(25), because this is not in immediate enconding.
417 Binary |= 1 << ARMII::I_BitShift;
418 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
419 // Set bit[3:0] to the corresponding Rm register
420 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
422 // if this instr is in scaled register offset/index instruction, set
423 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
424 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
425 Binary |= getShiftOp(MO3) << 5; // shift
426 Binary |= ShImm << 7; // shift_immed
432 unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
433 const TargetInstrDesc &TID,
436 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
438 // Set second operand
439 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
441 const MachineOperand &MO2 = MI.getOperand(2);
442 const MachineOperand &MO3 = MI.getOperand(3);
444 // Set bit U(23) according to signal of immed value (positive or negative)
445 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
448 // If this instr is in register offset/index encoding, set bit[3:0]
449 // to the corresponding Rm register.
451 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
455 // if this instr is in immediate offset/index encoding, set bit 22 to 1
456 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
459 Binary |= (ImmOffs >> 4) << 8; // immedH
460 Binary |= (ImmOffs & ~0xF); // immedL
466 unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
467 const TargetInstrDesc &TID,
470 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
472 // Set addressing mode by modifying bits U(23) and P(24)
473 // IA - Increment after - bit U = 1 and bit P = 0
474 // IB - Increment before - bit U = 1 and bit P = 1
475 // DA - Decrement after - bit U = 0 and bit P = 0
476 // DB - Decrement before - bit U = 0 and bit P = 1
477 const MachineOperand &MO = MI.getOperand(1);
478 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
480 default: assert(0 && "Unknown addressing sub-mode!");
481 case ARM_AM::da: break;
482 case ARM_AM::db: Binary |= 0x1 << 24; break;
483 case ARM_AM::ia: Binary |= 0x1 << 23; break;
484 case ARM_AM::ib: Binary |= 0x3 << 23; break;
488 if (ARM_AM::getAM4WBFlag(MO.getImm()))
492 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
493 const MachineOperand &MO = MI.getOperand(i);
494 if (MO.isRegister() && MO.isImplicit())
496 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
497 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
499 Binary |= 0x1 << RegNum;
505 /// getInstrBinary - Return binary encoding for the specified
506 /// machine instruction.
507 unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
508 // Part of binary is determined by TableGn.
509 unsigned Binary = getBinaryCodeForInstr(MI);
511 const TargetInstrDesc &TID = MI.getDesc();
512 switch (TID.TSFlags & ARMII::AddrModeMask) {
513 case ARMII::AddrModeNone:
514 return getAddrModeNoneInstrBinary(MI, TID, Binary);
515 case ARMII::AddrMode1:
516 return getAddrMode1InstrBinary(MI, TID, Binary);
517 case ARMII::AddrMode2:
518 return getAddrMode2InstrBinary(MI, TID, Binary);
519 case ARMII::AddrMode3:
520 return getAddrMode3InstrBinary(MI, TID, Binary);
521 case ARMII::AddrMode4:
522 return getAddrMode4InstrBinary(MI, TID, Binary);
529 #include "ARMGenCodeEmitter.inc"