1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitMiscInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
155 return getMachineOpValue(MI, MI.getOperand(OpIdx));
158 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
159 /// machine operand requires relocation, record the relocation and return
161 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
163 unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
165 return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
168 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
170 unsigned getShiftOp(unsigned Imm) const ;
172 /// Routines that handle operands which add machine relocations which are
173 /// fixed up by the relocation stage.
174 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
175 bool MayNeedFarStub, bool Indirect,
177 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
178 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
179 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
180 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
181 intptr_t JTBase = 0);
185 char ARMCodeEmitter::ID = 0;
187 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
188 /// code to the specified MCE object.
189 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
190 JITCodeEmitter &JCE) {
191 return new ARMCodeEmitter(TM, JCE);
194 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
195 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196 MF.getTarget().getRelocationModel() != Reloc::Static) &&
197 "JIT relocation model must be set to static or default!");
198 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
199 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
200 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
201 Subtarget = &TM.getSubtarget<ARMSubtarget>();
202 MCPEs = &MF.getConstantPool()->getConstants();
204 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
205 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
206 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
207 JTI->Initialize(MF, IsPIC);
208 MMI = &getAnalysis<MachineModuleInfo>();
209 MCE.setModuleInfo(MMI);
212 DEBUG(errs() << "JITTing function '"
213 << MF.getFunction()->getName() << "'\n");
214 MCE.startFunction(MF);
215 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
217 MCE.StartMachineBasicBlock(MBB);
218 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
222 } while (MCE.finishFunction(MF));
227 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
229 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
230 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
231 default: llvm_unreachable("Unknown shift opc!");
232 case ARM_AM::asr: return 2;
233 case ARM_AM::lsl: return 0;
234 case ARM_AM::lsr: return 1;
236 case ARM_AM::rrx: return 3;
241 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
242 /// machine operand requires relocation, record the relocation and return zero.
243 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
244 const MachineOperand &MO,
246 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
247 && "Relocation to this function should be for movt or movw");
250 return static_cast<unsigned>(MO.getImm());
251 else if (MO.isGlobal())
252 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
253 else if (MO.isSymbol())
254 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
256 emitMachineBasicBlock(MO.getMBB(), Reloc);
261 llvm_unreachable("Unsupported operand type for movw/movt");
266 /// getMachineOpValue - Return binary encoding of operand. If the machine
267 /// operand requires relocation, record the relocation and return zero.
268 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
269 const MachineOperand &MO) {
271 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
273 return static_cast<unsigned>(MO.getImm());
274 else if (MO.isGlobal())
275 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
276 else if (MO.isSymbol())
277 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
278 else if (MO.isCPI()) {
279 const TargetInstrDesc &TID = MI.getDesc();
280 // For VFP load, the immediate offset is multiplied by 4.
281 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
282 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
283 emitConstPoolAddress(MO.getIndex(), Reloc);
284 } else if (MO.isJTI())
285 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
287 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
297 /// emitGlobalAddress - Emit the specified address to the code stream.
299 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
300 bool MayNeedFarStub, bool Indirect,
302 MachineRelocation MR = Indirect
303 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
304 const_cast<GlobalValue *>(GV),
305 ACPV, MayNeedFarStub)
306 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
307 const_cast<GlobalValue *>(GV), ACPV,
309 MCE.addRelocation(MR);
312 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
313 /// be emitted to the current location in the function, and allow it to be PC
315 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
316 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
320 /// emitConstPoolAddress - Arrange for the address of an constant pool
321 /// to be emitted to the current location in the function, and allow it to be PC
323 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
324 // Tell JIT emitter we'll resolve the address.
325 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
326 Reloc, CPI, 0, true));
329 /// emitJumpTableAddress - Arrange for the address of a jump table to
330 /// be emitted to the current location in the function, and allow it to be PC
332 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
333 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
334 Reloc, JTIndex, 0, true));
337 /// emitMachineBasicBlock - Emit the specified address basic block.
338 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
339 unsigned Reloc, intptr_t JTBase) {
340 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
344 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
345 DEBUG(errs() << " 0x";
346 errs().write_hex(Binary) << "\n");
347 MCE.emitWordLE(Binary);
350 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
351 DEBUG(errs() << " 0x";
352 errs().write_hex(Binary) << "\n");
353 MCE.emitDWordLE(Binary);
356 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
357 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
359 MCE.processDebugLoc(MI.getDebugLoc(), true);
361 ++NumEmitted; // Keep track of the # of mi's emitted
362 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
364 llvm_unreachable("Unhandled instruction encoding format!");
368 emitPseudoInstruction(MI);
371 case ARMII::DPSoRegFrm:
372 emitDataProcessingInstruction(MI);
376 emitLoadStoreInstruction(MI);
378 case ARMII::LdMiscFrm:
379 case ARMII::StMiscFrm:
380 emitMiscLoadStoreInstruction(MI);
382 case ARMII::LdStMulFrm:
383 emitLoadStoreMultipleInstruction(MI);
386 emitMulFrmInstruction(MI);
389 emitExtendInstruction(MI);
391 case ARMII::ArithMiscFrm:
392 emitMiscArithInstruction(MI);
395 emitSaturateInstruction(MI);
398 emitBranchInstruction(MI);
400 case ARMII::BrMiscFrm:
401 emitMiscBranchInstruction(MI);
404 case ARMII::VFPUnaryFrm:
405 case ARMII::VFPBinaryFrm:
406 emitVFPArithInstruction(MI);
408 case ARMII::VFPConv1Frm:
409 case ARMII::VFPConv2Frm:
410 case ARMII::VFPConv3Frm:
411 case ARMII::VFPConv4Frm:
412 case ARMII::VFPConv5Frm:
413 emitVFPConversionInstruction(MI);
415 case ARMII::VFPLdStFrm:
416 emitVFPLoadStoreInstruction(MI);
418 case ARMII::VFPLdStMulFrm:
419 emitVFPLoadStoreMultipleInstruction(MI);
421 case ARMII::VFPMiscFrm:
422 emitMiscInstruction(MI);
424 // NEON instructions.
425 case ARMII::NGetLnFrm:
426 case ARMII::NSetLnFrm:
427 emitNEONLaneInstruction(MI);
430 emitNEONDupInstruction(MI);
432 case ARMII::N1RegModImmFrm:
433 emitNEON1RegModImmInstruction(MI);
435 case ARMII::N2RegFrm:
436 emitNEON2RegInstruction(MI);
438 case ARMII::N3RegFrm:
439 emitNEON3RegInstruction(MI);
442 MCE.processDebugLoc(MI.getDebugLoc(), false);
445 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
446 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
447 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
448 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
450 // Remember the CONSTPOOL_ENTRY address for later relocation.
451 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
453 // Emit constpool island entry. In most cases, the actual values will be
454 // resolved and relocated after code emission.
455 if (MCPE.isMachineConstantPoolEntry()) {
456 ARMConstantPoolValue *ACPV =
457 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
459 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
460 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
462 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
463 const GlobalValue *GV = ACPV->getGV();
465 Reloc::Model RelocM = TM.getRelocationModel();
466 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
468 Subtarget->GVIsIndirectSymbol(GV, RelocM),
471 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
475 const Constant *CV = MCPE.Val.ConstVal;
478 errs() << " ** Constant pool #" << CPI << " @ "
479 << (void*)MCE.getCurrentPCValue() << " ";
480 if (const Function *F = dyn_cast<Function>(CV))
481 errs() << F->getName();
487 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
488 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
490 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
491 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
493 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
494 if (CFP->getType()->isFloatTy())
495 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
496 else if (CFP->getType()->isDoubleTy())
497 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
499 llvm_unreachable("Unable to handle this constantpool entry!");
502 llvm_unreachable("Unable to handle this constantpool entry!");
507 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
508 const MachineOperand &MO0 = MI.getOperand(0);
509 const MachineOperand &MO1 = MI.getOperand(1);
511 // Emit the 'movw' instruction.
512 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
514 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
516 // Set the conditional execution predicate.
517 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
522 // Encode imm16 as imm4:imm12
523 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
524 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
527 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
528 // Emit the 'movt' instruction.
529 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
531 // Set the conditional execution predicate.
532 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
535 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
537 // Encode imm16 as imm4:imm1, same as movw above.
538 Binary |= Hi16 & 0xFFF;
539 Binary |= ((Hi16 >> 12) & 0xF) << 16;
543 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
544 const MachineOperand &MO0 = MI.getOperand(0);
545 const MachineOperand &MO1 = MI.getOperand(1);
546 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
547 "Not a valid so_imm value!");
548 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
549 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
551 // Emit the 'mov' instruction.
552 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
554 // Set the conditional execution predicate.
555 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
558 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
561 // Set bit I(25) to identify this is the immediate form of <shifter_op>
562 Binary |= 1 << ARMII::I_BitShift;
563 Binary |= getMachineSoImmOpValue(V1);
566 // Now the 'orr' instruction.
567 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
569 // Set the conditional execution predicate.
570 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
573 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
576 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
579 // Set bit I(25) to identify this is the immediate form of <shifter_op>
580 Binary |= 1 << ARMII::I_BitShift;
581 Binary |= getMachineSoImmOpValue(V2);
585 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
586 // It's basically add r, pc, (LJTI - $+8)
588 const TargetInstrDesc &TID = MI.getDesc();
590 // Emit the 'add' instruction.
591 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
593 // Set the conditional execution predicate
594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
596 // Encode S bit if MI modifies CPSR.
597 Binary |= getAddrModeSBit(MI, TID);
600 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
602 // Encode Rn which is PC.
603 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
605 // Encode the displacement.
606 Binary |= 1 << ARMII::I_BitShift;
607 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
612 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
613 unsigned Opcode = MI.getDesc().Opcode;
615 // Part of binary is determined by TableGn.
616 unsigned Binary = getBinaryCodeForInstr(MI);
618 // Set the conditional execution predicate
619 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
621 // Encode S bit if MI modifies CPSR.
622 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
623 Binary |= 1 << ARMII::S_BitShift;
625 // Encode register def if there is one.
626 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
628 // Encode the shift operation.
635 case ARM::MOVsrl_flag:
637 Binary |= (0x2 << 4) | (1 << 7);
639 case ARM::MOVsra_flag:
641 Binary |= (0x4 << 4) | (1 << 7);
645 // Encode register Rm.
646 Binary |= getMachineOpValue(MI, 1);
651 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
652 DEBUG(errs() << " ** LPC" << LabelID << " @ "
653 << (void*)MCE.getCurrentPCValue() << '\n');
654 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
657 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
658 unsigned Opcode = MI.getDesc().Opcode;
661 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
665 case ARM::BMOVPCRXr9: {
666 // First emit mov lr, pc
667 unsigned Binary = 0x01a0e00f;
668 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
671 // and then emit the branch.
672 emitMiscBranchInstruction(MI);
675 case TargetOpcode::INLINEASM: {
676 // We allow inline assembler nodes with empty bodies - they can
677 // implicitly define registers, which is ok for JIT.
678 if (MI.getOperand(0).getSymbolName()[0]) {
679 report_fatal_error("JIT does not support inline asm!");
683 case TargetOpcode::PROLOG_LABEL:
684 case TargetOpcode::EH_LABEL:
685 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
687 case TargetOpcode::IMPLICIT_DEF:
688 case TargetOpcode::KILL:
691 case ARM::CONSTPOOL_ENTRY:
692 emitConstPoolInstruction(MI);
695 // Remember of the address of the PC label for relocation later.
696 addPCLabel(MI.getOperand(2).getImm());
697 // PICADD is just an add instruction that implicitly read pc.
698 emitDataProcessingInstruction(MI, 0, ARM::PC);
705 // Remember of the address of the PC label for relocation later.
706 addPCLabel(MI.getOperand(2).getImm());
707 // These are just load / store instructions that implicitly read pc.
708 emitLoadStoreInstruction(MI, 0, ARM::PC);
715 // Remember of the address of the PC label for relocation later.
716 addPCLabel(MI.getOperand(2).getImm());
717 // These are just load / store instructions that implicitly read pc.
718 emitMiscLoadStoreInstruction(MI, ARM::PC);
723 emitMOVi32immInstruction(MI);
726 case ARM::MOVi2pieces:
727 // Two instructions to materialize a constant.
728 emitMOVi2piecesInstruction(MI);
730 case ARM::LEApcrelJT:
731 // Materialize jumptable address.
732 emitLEApcrelJTInstruction(MI);
735 case ARM::MOVsrl_flag:
736 case ARM::MOVsra_flag:
737 emitPseudoMoveInstruction(MI);
742 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
743 const TargetInstrDesc &TID,
744 const MachineOperand &MO,
746 unsigned Binary = getMachineOpValue(MI, MO);
748 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
749 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
750 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
752 // Encode the shift opcode.
754 unsigned Rs = MO1.getReg();
756 // Set shift operand (bit[7:4]).
761 // RRX - 0110 and bit[11:8] clear.
763 default: llvm_unreachable("Unknown shift opc!");
764 case ARM_AM::lsl: SBits = 0x1; break;
765 case ARM_AM::lsr: SBits = 0x3; break;
766 case ARM_AM::asr: SBits = 0x5; break;
767 case ARM_AM::ror: SBits = 0x7; break;
768 case ARM_AM::rrx: SBits = 0x6; break;
771 // Set shift operand (bit[6:4]).
777 default: llvm_unreachable("Unknown shift opc!");
778 case ARM_AM::lsl: SBits = 0x0; break;
779 case ARM_AM::lsr: SBits = 0x2; break;
780 case ARM_AM::asr: SBits = 0x4; break;
781 case ARM_AM::ror: SBits = 0x6; break;
784 Binary |= SBits << 4;
785 if (SOpc == ARM_AM::rrx)
788 // Encode the shift operation Rs or shift_imm (except rrx).
790 // Encode Rs bit[11:8].
791 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
793 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
796 // Encode shift_imm bit[11:7].
797 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
800 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
801 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
802 assert(SoImmVal != -1 && "Not a valid so_imm value!");
804 // Encode rotate_imm.
805 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
806 << ARMII::SoRotImmShift;
809 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
813 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
814 const TargetInstrDesc &TID) const {
815 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
816 const MachineOperand &MO = MI.getOperand(i-1);
817 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
818 return 1 << ARMII::S_BitShift;
823 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
825 unsigned ImplicitRn) {
826 const TargetInstrDesc &TID = MI.getDesc();
828 // Part of binary is determined by TableGn.
829 unsigned Binary = getBinaryCodeForInstr(MI);
831 // Set the conditional execution predicate
832 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
834 // Encode S bit if MI modifies CPSR.
835 Binary |= getAddrModeSBit(MI, TID);
837 // Encode register def if there is one.
838 unsigned NumDefs = TID.getNumDefs();
841 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
843 // Special handling for implicit use (e.g. PC).
844 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
845 << ARMII::RegRdShift);
847 if (TID.Opcode == ARM::MOVi16) {
848 // Get immediate from MI.
849 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
850 ARM::reloc_arm_movw);
851 // Encode imm which is the same as in emitMOVi32immInstruction().
852 Binary |= Lo16 & 0xFFF;
853 Binary |= ((Lo16 >> 12) & 0xF) << 16;
856 } else if(TID.Opcode == ARM::MOVTi16) {
857 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
858 ARM::reloc_arm_movt) >> 16);
859 Binary |= Hi16 & 0xFFF;
860 Binary |= ((Hi16 >> 12) & 0xF) << 16;
863 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
864 uint32_t v = ~MI.getOperand(2).getImm();
865 int32_t lsb = CountTrailingZeros_32(v);
866 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
867 // Instr{20-16} = msb, Instr{11-7} = lsb
868 Binary |= (msb & 0x1F) << 16;
869 Binary |= (lsb & 0x1F) << 7;
872 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
873 // Encode Rn in Instr{0-3}
874 Binary |= getMachineOpValue(MI, OpIdx++);
876 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
877 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
879 // Instr{20-16} = widthm1, Instr{11-7} = lsb
880 Binary |= (widthm1 & 0x1F) << 16;
881 Binary |= (lsb & 0x1F) << 7;
886 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
887 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
890 // Encode first non-shifter register operand if there is one.
891 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
894 // Special handling for implicit use (e.g. PC).
895 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
896 << ARMII::RegRnShift);
898 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
903 // Encode shifter operand.
904 const MachineOperand &MO = MI.getOperand(OpIdx);
905 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
907 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
912 // Encode register Rm.
913 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
918 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
923 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
925 unsigned ImplicitRn) {
926 const TargetInstrDesc &TID = MI.getDesc();
927 unsigned Form = TID.TSFlags & ARMII::FormMask;
928 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
930 // Part of binary is determined by TableGn.
931 unsigned Binary = getBinaryCodeForInstr(MI);
933 // Set the conditional execution predicate
934 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
938 // Operand 0 of a pre- and post-indexed store is the address base
939 // writeback. Skip it.
940 bool Skipped = false;
941 if (IsPrePost && Form == ARMII::StFrm) {
948 // Special handling for implicit use (e.g. PC).
949 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
950 << ARMII::RegRdShift);
952 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
954 // Set second operand
956 // Special handling for implicit use (e.g. PC).
957 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
958 << ARMII::RegRnShift);
960 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
962 // If this is a two-address operand, skip it. e.g. LDR_PRE.
963 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
966 const MachineOperand &MO2 = MI.getOperand(OpIdx);
967 unsigned AM2Opc = (ImplicitRn == ARM::PC)
968 ? 0 : MI.getOperand(OpIdx+1).getImm();
970 // Set bit U(23) according to sign of immed value (positive or negative).
971 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
973 if (!MO2.getReg()) { // is immediate
974 if (ARM_AM::getAM2Offset(AM2Opc))
975 // Set the value of offset_12 field
976 Binary |= ARM_AM::getAM2Offset(AM2Opc);
981 // Set bit I(25), because this is not in immediate enconding.
982 Binary |= 1 << ARMII::I_BitShift;
983 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
984 // Set bit[3:0] to the corresponding Rm register
985 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
987 // If this instr is in scaled register offset/index instruction, set
988 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
989 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
990 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
991 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
997 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
998 unsigned ImplicitRn) {
999 const TargetInstrDesc &TID = MI.getDesc();
1000 unsigned Form = TID.TSFlags & ARMII::FormMask;
1001 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1003 // Part of binary is determined by TableGn.
1004 unsigned Binary = getBinaryCodeForInstr(MI);
1006 // Set the conditional execution predicate
1007 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1011 // Operand 0 of a pre- and post-indexed store is the address base
1012 // writeback. Skip it.
1013 bool Skipped = false;
1014 if (IsPrePost && Form == ARMII::StMiscFrm) {
1019 // Set first operand
1020 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1022 // Skip LDRD and STRD's second operand.
1023 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1026 // Set second operand
1028 // Special handling for implicit use (e.g. PC).
1029 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1030 << ARMII::RegRnShift);
1032 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1034 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1035 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1038 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1039 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1040 ? 0 : MI.getOperand(OpIdx+1).getImm();
1042 // Set bit U(23) according to sign of immed value (positive or negative)
1043 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1046 // If this instr is in register offset/index encoding, set bit[3:0]
1047 // to the corresponding Rm register.
1049 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1054 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1055 Binary |= 1 << ARMII::AM3_I_BitShift;
1056 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1058 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1059 Binary |= (ImmOffs & 0xF); // immedL
1065 static unsigned getAddrModeUPBits(unsigned Mode) {
1066 unsigned Binary = 0;
1068 // Set addressing mode by modifying bits U(23) and P(24)
1069 // IA - Increment after - bit U = 1 and bit P = 0
1070 // IB - Increment before - bit U = 1 and bit P = 1
1071 // DA - Decrement after - bit U = 0 and bit P = 0
1072 // DB - Decrement before - bit U = 0 and bit P = 1
1074 default: llvm_unreachable("Unknown addressing sub-mode!");
1075 case ARM_AM::da: break;
1076 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1077 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1078 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1084 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1085 const TargetInstrDesc &TID = MI.getDesc();
1086 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1088 // Part of binary is determined by TableGn.
1089 unsigned Binary = getBinaryCodeForInstr(MI);
1091 // Set the conditional execution predicate
1092 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1094 // Skip operand 0 of an instruction with base register update.
1099 // Set base address operand
1100 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1102 // Set addressing mode by modifying bits U(23) and P(24)
1103 const MachineOperand &MO = MI.getOperand(OpIdx++);
1104 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1108 Binary |= 0x1 << ARMII::W_BitShift;
1111 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1112 const MachineOperand &MO = MI.getOperand(i);
1113 if (!MO.isReg() || MO.isImplicit())
1115 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1116 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1118 Binary |= 0x1 << RegNum;
1124 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1125 const TargetInstrDesc &TID = MI.getDesc();
1127 // Part of binary is determined by TableGn.
1128 unsigned Binary = getBinaryCodeForInstr(MI);
1130 // Set the conditional execution predicate
1131 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1133 // Encode S bit if MI modifies CPSR.
1134 Binary |= getAddrModeSBit(MI, TID);
1136 // 32x32->64bit operations have two destination registers. The number
1137 // of register definitions will tell us if that's what we're dealing with.
1139 if (TID.getNumDefs() == 2)
1140 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1143 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1146 Binary |= getMachineOpValue(MI, OpIdx++);
1149 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1151 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1152 // it as Rn (for multiply, that's in the same offset as RdLo.
1153 if (TID.getNumOperands() > OpIdx &&
1154 !TID.OpInfo[OpIdx].isPredicate() &&
1155 !TID.OpInfo[OpIdx].isOptionalDef())
1156 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1161 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1162 const TargetInstrDesc &TID = MI.getDesc();
1164 // Part of binary is determined by TableGn.
1165 unsigned Binary = getBinaryCodeForInstr(MI);
1167 // Set the conditional execution predicate
1168 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1173 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1175 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1176 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1178 // Two register operand form.
1180 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1183 Binary |= getMachineOpValue(MI, MO2);
1186 Binary |= getMachineOpValue(MI, MO1);
1189 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1190 if (MI.getOperand(OpIdx).isImm() &&
1191 !TID.OpInfo[OpIdx].isPredicate() &&
1192 !TID.OpInfo[OpIdx].isOptionalDef())
1193 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1198 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1199 const TargetInstrDesc &TID = MI.getDesc();
1201 // Part of binary is determined by TableGn.
1202 unsigned Binary = getBinaryCodeForInstr(MI);
1204 // Set the conditional execution predicate
1205 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1210 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1212 const MachineOperand &MO = MI.getOperand(OpIdx++);
1213 if (OpIdx == TID.getNumOperands() ||
1214 TID.OpInfo[OpIdx].isPredicate() ||
1215 TID.OpInfo[OpIdx].isOptionalDef()) {
1216 // Encode Rm and it's done.
1217 Binary |= getMachineOpValue(MI, MO);
1223 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1226 Binary |= getMachineOpValue(MI, OpIdx++);
1228 // Encode shift_imm.
1229 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1230 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1231 Binary |= ShiftAmt << ARMII::ShiftShift;
1236 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1237 const TargetInstrDesc &TID = MI.getDesc();
1239 // Part of binary is determined by TableGen.
1240 unsigned Binary = getBinaryCodeForInstr(MI);
1242 // Set the conditional execution predicate
1243 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1246 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1248 // Encode saturate bit position.
1249 unsigned Pos = MI.getOperand(1).getImm();
1250 if (TID.Opcode == ARM::SSATlsl ||
1251 TID.Opcode == ARM::SSATasr ||
1252 TID.Opcode == ARM::SSAT16)
1254 assert((Pos < 16 || (Pos < 32 &&
1255 TID.Opcode != ARM::SSAT16 &&
1256 TID.Opcode != ARM::USAT16)) &&
1257 "saturate bit position out of range");
1258 Binary |= Pos << 16;
1261 Binary |= getMachineOpValue(MI, 2);
1263 // Encode shift_imm.
1264 if (TID.getNumOperands() == 4) {
1265 unsigned ShiftAmt = MI.getOperand(3).getImm();
1266 if (ShiftAmt == 32 &&
1267 (TID.Opcode == ARM::SSATasr || TID.Opcode == ARM::USATasr))
1269 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1270 Binary |= ShiftAmt << ARMII::ShiftShift;
1276 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1277 const TargetInstrDesc &TID = MI.getDesc();
1279 if (TID.Opcode == ARM::TPsoft) {
1280 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1283 // Part of binary is determined by TableGn.
1284 unsigned Binary = getBinaryCodeForInstr(MI);
1286 // Set the conditional execution predicate
1287 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1289 // Set signed_immed_24 field
1290 Binary |= getMachineOpValue(MI, 0);
1295 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1296 // Remember the base address of the inline jump table.
1297 uintptr_t JTBase = MCE.getCurrentPCValue();
1298 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1299 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1302 // Now emit the jump table entries.
1303 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1304 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1306 // DestBB address - JT base.
1307 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1309 // Absolute DestBB address.
1310 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1315 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1316 const TargetInstrDesc &TID = MI.getDesc();
1318 // Handle jump tables.
1319 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1320 // First emit a ldr pc, [] instruction.
1321 emitDataProcessingInstruction(MI, ARM::PC);
1323 // Then emit the inline jump table.
1325 (TID.Opcode == ARM::BR_JTr)
1326 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1327 emitInlineJumpTable(JTIndex);
1329 } else if (TID.Opcode == ARM::BR_JTm) {
1330 // First emit a ldr pc, [] instruction.
1331 emitLoadStoreInstruction(MI, ARM::PC);
1333 // Then emit the inline jump table.
1334 emitInlineJumpTable(MI.getOperand(3).getIndex());
1338 // Part of binary is determined by TableGn.
1339 unsigned Binary = getBinaryCodeForInstr(MI);
1341 // Set the conditional execution predicate
1342 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1345 // The return register is LR.
1346 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1348 // otherwise, set the return register
1349 Binary |= getMachineOpValue(MI, 0);
1354 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1355 unsigned RegD = MI.getOperand(OpIdx).getReg();
1356 unsigned Binary = 0;
1357 bool isSPVFP = false;
1358 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1360 Binary |= RegD << ARMII::RegRdShift;
1362 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1363 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1368 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1369 unsigned RegN = MI.getOperand(OpIdx).getReg();
1370 unsigned Binary = 0;
1371 bool isSPVFP = false;
1372 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1374 Binary |= RegN << ARMII::RegRnShift;
1376 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1377 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1382 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1383 unsigned RegM = MI.getOperand(OpIdx).getReg();
1384 unsigned Binary = 0;
1385 bool isSPVFP = false;
1386 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1390 Binary |= ((RegM & 0x1E) >> 1);
1391 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1396 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1397 const TargetInstrDesc &TID = MI.getDesc();
1399 // Part of binary is determined by TableGn.
1400 unsigned Binary = getBinaryCodeForInstr(MI);
1402 // Set the conditional execution predicate
1403 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1406 assert((Binary & ARMII::D_BitShift) == 0 &&
1407 (Binary & ARMII::N_BitShift) == 0 &&
1408 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1411 Binary |= encodeVFPRd(MI, OpIdx++);
1413 // If this is a two-address operand, skip it, e.g. FMACD.
1414 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1418 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1419 Binary |= encodeVFPRn(MI, OpIdx++);
1421 if (OpIdx == TID.getNumOperands() ||
1422 TID.OpInfo[OpIdx].isPredicate() ||
1423 TID.OpInfo[OpIdx].isOptionalDef()) {
1424 // FCMPEZD etc. has only one operand.
1430 Binary |= encodeVFPRm(MI, OpIdx);
1435 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1436 const TargetInstrDesc &TID = MI.getDesc();
1437 unsigned Form = TID.TSFlags & ARMII::FormMask;
1439 // Part of binary is determined by TableGn.
1440 unsigned Binary = getBinaryCodeForInstr(MI);
1442 // Set the conditional execution predicate
1443 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1447 case ARMII::VFPConv1Frm:
1448 case ARMII::VFPConv2Frm:
1449 case ARMII::VFPConv3Frm:
1451 Binary |= encodeVFPRd(MI, 0);
1453 case ARMII::VFPConv4Frm:
1455 Binary |= encodeVFPRn(MI, 0);
1457 case ARMII::VFPConv5Frm:
1459 Binary |= encodeVFPRm(MI, 0);
1465 case ARMII::VFPConv1Frm:
1467 Binary |= encodeVFPRm(MI, 1);
1469 case ARMII::VFPConv2Frm:
1470 case ARMII::VFPConv3Frm:
1472 Binary |= encodeVFPRn(MI, 1);
1474 case ARMII::VFPConv4Frm:
1475 case ARMII::VFPConv5Frm:
1477 Binary |= encodeVFPRd(MI, 1);
1481 if (Form == ARMII::VFPConv5Frm)
1483 Binary |= encodeVFPRn(MI, 2);
1484 else if (Form == ARMII::VFPConv3Frm)
1486 Binary |= encodeVFPRm(MI, 2);
1491 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1492 // Part of binary is determined by TableGn.
1493 unsigned Binary = getBinaryCodeForInstr(MI);
1495 // Set the conditional execution predicate
1496 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1501 Binary |= encodeVFPRd(MI, OpIdx++);
1503 // Encode address base.
1504 const MachineOperand &Base = MI.getOperand(OpIdx++);
1505 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1507 // If there is a non-zero immediate offset, encode it.
1509 const MachineOperand &Offset = MI.getOperand(OpIdx);
1510 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1511 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1512 Binary |= 1 << ARMII::U_BitShift;
1519 // If immediate offset is omitted, default to +0.
1520 Binary |= 1 << ARMII::U_BitShift;
1526 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1527 const TargetInstrDesc &TID = MI.getDesc();
1528 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1530 // Part of binary is determined by TableGn.
1531 unsigned Binary = getBinaryCodeForInstr(MI);
1533 // Set the conditional execution predicate
1534 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1536 // Skip operand 0 of an instruction with base register update.
1541 // Set base address operand
1542 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1544 // Set addressing mode by modifying bits U(23) and P(24)
1545 const MachineOperand &MO = MI.getOperand(OpIdx++);
1546 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1550 Binary |= 0x1 << ARMII::W_BitShift;
1552 // First register is encoded in Dd.
1553 Binary |= encodeVFPRd(MI, OpIdx+2);
1555 // Number of registers are encoded in offset field.
1556 unsigned NumRegs = 1;
1557 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1558 const MachineOperand &MO = MI.getOperand(i);
1559 if (!MO.isReg() || MO.isImplicit())
1563 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1564 // Otherwise, it will be 0, in the case of 32-bit registers.
1566 Binary |= NumRegs * 2;
1573 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1574 unsigned Opcode = MI.getDesc().Opcode;
1575 // Part of binary is determined by TableGn.
1576 unsigned Binary = getBinaryCodeForInstr(MI);
1578 // Set the conditional execution predicate
1579 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1583 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1586 // No further encoding needed.
1591 const MachineOperand &MO0 = MI.getOperand(0);
1593 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1594 << ARMII::RegRdShift;
1599 case ARM::FCONSTS: {
1601 Binary |= encodeVFPRd(MI, 0);
1603 // Encode imm., Table A7-18 VFP modified immediate constants
1604 const MachineOperand &MO1 = MI.getOperand(1);
1605 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1606 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1607 unsigned ModifiedImm;
1609 if(Opcode == ARM::FCONSTS)
1610 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1611 (Imm & 0x03F80000) >> 19; // bcdefgh
1612 else // Opcode == ARM::FCONSTD
1613 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1614 (Imm & 0x007F0000) >> 16; // bcdefgh
1616 // Insts{19-16} = abcd, Insts{3-0} = efgh
1617 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1618 Binary |= (ModifiedImm & 0xF);
1626 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1627 unsigned RegD = MI.getOperand(OpIdx).getReg();
1628 unsigned Binary = 0;
1629 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1630 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1631 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1635 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1636 unsigned RegN = MI.getOperand(OpIdx).getReg();
1637 unsigned Binary = 0;
1638 RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1639 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1640 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1644 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1645 unsigned RegM = MI.getOperand(OpIdx).getReg();
1646 unsigned Binary = 0;
1647 RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1648 Binary |= (RegM & 0xf);
1649 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1653 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1654 /// data-processing instruction to the corresponding Thumb encoding.
1655 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1656 assert((Binary & 0xfe000000) == 0xf2000000 &&
1657 "not an ARM NEON data-processing instruction");
1658 unsigned UBit = (Binary >> 24) & 1;
1659 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1662 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1663 unsigned Binary = getBinaryCodeForInstr(MI);
1665 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1666 const TargetInstrDesc &TID = MI.getDesc();
1667 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1671 } else { // ARMII::NSetLnFrm
1677 // Set the conditional execution predicate
1678 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1680 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1681 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1682 Binary |= (RegT << ARMII::RegRdShift);
1683 Binary |= encodeNEONRn(MI, RegNOpIdx);
1686 if ((Binary & (1 << 22)) != 0)
1687 LaneShift = 0; // 8-bit elements
1688 else if ((Binary & (1 << 5)) != 0)
1689 LaneShift = 1; // 16-bit elements
1691 LaneShift = 2; // 32-bit elements
1693 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1694 unsigned Opc1 = Lane >> 2;
1695 unsigned Opc2 = Lane & 3;
1696 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1697 Binary |= (Opc1 << 21);
1698 Binary |= (Opc2 << 5);
1703 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1704 unsigned Binary = getBinaryCodeForInstr(MI);
1706 // Set the conditional execution predicate
1707 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1709 unsigned RegT = MI.getOperand(1).getReg();
1710 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1711 Binary |= (RegT << ARMII::RegRdShift);
1712 Binary |= encodeNEONRn(MI, 0);
1716 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1717 unsigned Binary = getBinaryCodeForInstr(MI);
1718 // Destination register is encoded in Dd.
1719 Binary |= encodeNEONRd(MI, 0);
1720 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1721 unsigned Imm = MI.getOperand(1).getImm();
1722 unsigned Op = (Imm >> 12) & 1;
1723 unsigned Cmode = (Imm >> 8) & 0xf;
1724 unsigned I = (Imm >> 7) & 1;
1725 unsigned Imm3 = (Imm >> 4) & 0x7;
1726 unsigned Imm4 = Imm & 0xf;
1727 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1729 Binary = convertNEONDataProcToThumb(Binary);
1733 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1734 const TargetInstrDesc &TID = MI.getDesc();
1735 unsigned Binary = getBinaryCodeForInstr(MI);
1736 // Destination register is encoded in Dd; source register in Dm.
1738 Binary |= encodeNEONRd(MI, OpIdx++);
1739 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1741 Binary |= encodeNEONRm(MI, OpIdx);
1743 Binary = convertNEONDataProcToThumb(Binary);
1744 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1748 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1749 const TargetInstrDesc &TID = MI.getDesc();
1750 unsigned Binary = getBinaryCodeForInstr(MI);
1751 // Destination register is encoded in Dd; source registers in Dn and Dm.
1753 Binary |= encodeNEONRd(MI, OpIdx++);
1754 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1756 Binary |= encodeNEONRn(MI, OpIdx++);
1757 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1759 Binary |= encodeNEONRm(MI, OpIdx);
1761 Binary = convertNEONDataProcToThumb(Binary);
1762 // FIXME: This does not handle VMOVDneon or VMOVQ.
1766 #include "ARMGenCodeEmitter.inc"