1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(&ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitBranchInstruction(const MachineInstr &MI);
129 void emitInlineJumpTable(unsigned JTIndex);
131 void emitMiscBranchInstruction(const MachineInstr &MI);
133 void emitVFPArithInstruction(const MachineInstr &MI);
135 void emitVFPConversionInstruction(const MachineInstr &MI);
137 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141 void emitMiscInstruction(const MachineInstr &MI);
143 void emitNEONLaneInstruction(const MachineInstr &MI);
144 void emitNEONDupInstruction(const MachineInstr &MI);
145 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146 void emitNEON2RegInstruction(const MachineInstr &MI);
147 void emitNEON3RegInstruction(const MachineInstr &MI);
149 /// getMachineOpValue - Return binary encoding of operand. If the machine
150 /// operand requires relocation, record the relocation and return zero.
151 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
157 /// machine operand requires relocation, record the relocation and return
159 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
161 unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
163 return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
166 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
168 unsigned getShiftOp(unsigned Imm) const ;
170 /// Routines that handle operands which add machine relocations which are
171 /// fixed up by the relocation stage.
172 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
173 bool MayNeedFarStub, bool Indirect,
175 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
176 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
177 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
178 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
179 intptr_t JTBase = 0);
183 char ARMCodeEmitter::ID = 0;
185 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
186 /// code to the specified MCE object.
187 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
188 JITCodeEmitter &JCE) {
189 return new ARMCodeEmitter(TM, JCE);
192 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
193 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194 MF.getTarget().getRelocationModel() != Reloc::Static) &&
195 "JIT relocation model must be set to static or default!");
196 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
197 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
198 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
199 Subtarget = &TM.getSubtarget<ARMSubtarget>();
200 MCPEs = &MF.getConstantPool()->getConstants();
202 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
205 JTI->Initialize(MF, IsPIC);
206 MMI = &getAnalysis<MachineModuleInfo>();
207 MCE.setModuleInfo(MMI);
210 DEBUG(errs() << "JITTing function '"
211 << MF.getFunction()->getName() << "'\n");
212 MCE.startFunction(MF);
213 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
215 MCE.StartMachineBasicBlock(MBB);
216 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
220 } while (MCE.finishFunction(MF));
225 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
227 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
228 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
229 default: llvm_unreachable("Unknown shift opc!");
230 case ARM_AM::asr: return 2;
231 case ARM_AM::lsl: return 0;
232 case ARM_AM::lsr: return 1;
234 case ARM_AM::rrx: return 3;
239 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
240 /// machine operand requires relocation, record the relocation and return zero.
241 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
242 const MachineOperand &MO,
244 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
245 && "Relocation to this function should be for movt or movw");
248 return static_cast<unsigned>(MO.getImm());
249 else if (MO.isGlobal())
250 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
251 else if (MO.isSymbol())
252 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
254 emitMachineBasicBlock(MO.getMBB(), Reloc);
259 llvm_unreachable("Unsupported operand type for movw/movt");
264 /// getMachineOpValue - Return binary encoding of operand. If the machine
265 /// operand requires relocation, record the relocation and return zero.
266 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
267 const MachineOperand &MO) {
269 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
271 return static_cast<unsigned>(MO.getImm());
272 else if (MO.isGlobal())
273 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
274 else if (MO.isSymbol())
275 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
276 else if (MO.isCPI()) {
277 const TargetInstrDesc &TID = MI.getDesc();
278 // For VFP load, the immediate offset is multiplied by 4.
279 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
280 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
281 emitConstPoolAddress(MO.getIndex(), Reloc);
282 } else if (MO.isJTI())
283 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
285 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
295 /// emitGlobalAddress - Emit the specified address to the code stream.
297 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
298 bool MayNeedFarStub, bool Indirect,
300 MachineRelocation MR = Indirect
301 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
302 const_cast<GlobalValue *>(GV),
303 ACPV, MayNeedFarStub)
304 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
305 const_cast<GlobalValue *>(GV), ACPV,
307 MCE.addRelocation(MR);
310 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
311 /// be emitted to the current location in the function, and allow it to be PC
313 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
314 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
318 /// emitConstPoolAddress - Arrange for the address of an constant pool
319 /// to be emitted to the current location in the function, and allow it to be PC
321 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
322 // Tell JIT emitter we'll resolve the address.
323 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
324 Reloc, CPI, 0, true));
327 /// emitJumpTableAddress - Arrange for the address of a jump table to
328 /// be emitted to the current location in the function, and allow it to be PC
330 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
331 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
332 Reloc, JTIndex, 0, true));
335 /// emitMachineBasicBlock - Emit the specified address basic block.
336 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
337 unsigned Reloc, intptr_t JTBase) {
338 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
342 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
343 DEBUG(errs() << " 0x";
344 errs().write_hex(Binary) << "\n");
345 MCE.emitWordLE(Binary);
348 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
349 DEBUG(errs() << " 0x";
350 errs().write_hex(Binary) << "\n");
351 MCE.emitDWordLE(Binary);
354 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
355 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
357 MCE.processDebugLoc(MI.getDebugLoc(), true);
359 ++NumEmitted; // Keep track of the # of mi's emitted
360 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
362 llvm_unreachable("Unhandled instruction encoding format!");
366 emitPseudoInstruction(MI);
369 case ARMII::DPSoRegFrm:
370 emitDataProcessingInstruction(MI);
374 emitLoadStoreInstruction(MI);
376 case ARMII::LdMiscFrm:
377 case ARMII::StMiscFrm:
378 emitMiscLoadStoreInstruction(MI);
380 case ARMII::LdStMulFrm:
381 emitLoadStoreMultipleInstruction(MI);
384 emitMulFrmInstruction(MI);
387 emitExtendInstruction(MI);
389 case ARMII::ArithMiscFrm:
390 emitMiscArithInstruction(MI);
393 emitBranchInstruction(MI);
395 case ARMII::BrMiscFrm:
396 emitMiscBranchInstruction(MI);
399 case ARMII::VFPUnaryFrm:
400 case ARMII::VFPBinaryFrm:
401 emitVFPArithInstruction(MI);
403 case ARMII::VFPConv1Frm:
404 case ARMII::VFPConv2Frm:
405 case ARMII::VFPConv3Frm:
406 case ARMII::VFPConv4Frm:
407 case ARMII::VFPConv5Frm:
408 emitVFPConversionInstruction(MI);
410 case ARMII::VFPLdStFrm:
411 emitVFPLoadStoreInstruction(MI);
413 case ARMII::VFPLdStMulFrm:
414 emitVFPLoadStoreMultipleInstruction(MI);
416 case ARMII::VFPMiscFrm:
417 emitMiscInstruction(MI);
419 // NEON instructions.
420 case ARMII::NGetLnFrm:
421 case ARMII::NSetLnFrm:
422 emitNEONLaneInstruction(MI);
425 emitNEONDupInstruction(MI);
427 case ARMII::N1RegModImmFrm:
428 emitNEON1RegModImmInstruction(MI);
430 case ARMII::N2RegFrm:
431 emitNEON2RegInstruction(MI);
433 case ARMII::N3RegFrm:
434 emitNEON3RegInstruction(MI);
437 MCE.processDebugLoc(MI.getDebugLoc(), false);
440 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
441 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
442 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
443 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
445 // Remember the CONSTPOOL_ENTRY address for later relocation.
446 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
448 // Emit constpool island entry. In most cases, the actual values will be
449 // resolved and relocated after code emission.
450 if (MCPE.isMachineConstantPoolEntry()) {
451 ARMConstantPoolValue *ACPV =
452 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
454 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
455 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
457 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
458 const GlobalValue *GV = ACPV->getGV();
460 Reloc::Model RelocM = TM.getRelocationModel();
461 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
463 Subtarget->GVIsIndirectSymbol(GV, RelocM),
466 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
470 const Constant *CV = MCPE.Val.ConstVal;
473 errs() << " ** Constant pool #" << CPI << " @ "
474 << (void*)MCE.getCurrentPCValue() << " ";
475 if (const Function *F = dyn_cast<Function>(CV))
476 errs() << F->getName();
482 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
483 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
485 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
486 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
488 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
489 if (CFP->getType()->isFloatTy())
490 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
491 else if (CFP->getType()->isDoubleTy())
492 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
494 llvm_unreachable("Unable to handle this constantpool entry!");
497 llvm_unreachable("Unable to handle this constantpool entry!");
502 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
503 const MachineOperand &MO0 = MI.getOperand(0);
504 const MachineOperand &MO1 = MI.getOperand(1);
506 // Emit the 'movw' instruction.
507 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
509 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
511 // Set the conditional execution predicate.
512 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
515 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
517 // Encode imm16 as imm4:imm12
518 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
519 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
522 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
523 // Emit the 'movt' instruction.
524 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
526 // Set the conditional execution predicate.
527 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
530 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
532 // Encode imm16 as imm4:imm1, same as movw above.
533 Binary |= Hi16 & 0xFFF;
534 Binary |= ((Hi16 >> 12) & 0xF) << 16;
538 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
539 const MachineOperand &MO0 = MI.getOperand(0);
540 const MachineOperand &MO1 = MI.getOperand(1);
541 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
542 "Not a valid so_imm value!");
543 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
544 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
546 // Emit the 'mov' instruction.
547 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
549 // Set the conditional execution predicate.
550 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
553 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
556 // Set bit I(25) to identify this is the immediate form of <shifter_op>
557 Binary |= 1 << ARMII::I_BitShift;
558 Binary |= getMachineSoImmOpValue(V1);
561 // Now the 'orr' instruction.
562 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
564 // Set the conditional execution predicate.
565 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
568 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
571 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
574 // Set bit I(25) to identify this is the immediate form of <shifter_op>
575 Binary |= 1 << ARMII::I_BitShift;
576 Binary |= getMachineSoImmOpValue(V2);
580 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
581 // It's basically add r, pc, (LJTI - $+8)
583 const TargetInstrDesc &TID = MI.getDesc();
585 // Emit the 'add' instruction.
586 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
588 // Set the conditional execution predicate
589 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
591 // Encode S bit if MI modifies CPSR.
592 Binary |= getAddrModeSBit(MI, TID);
595 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
597 // Encode Rn which is PC.
598 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
600 // Encode the displacement.
601 Binary |= 1 << ARMII::I_BitShift;
602 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
607 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
608 unsigned Opcode = MI.getDesc().Opcode;
610 // Part of binary is determined by TableGn.
611 unsigned Binary = getBinaryCodeForInstr(MI);
613 // Set the conditional execution predicate
614 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
616 // Encode S bit if MI modifies CPSR.
617 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
618 Binary |= 1 << ARMII::S_BitShift;
620 // Encode register def if there is one.
621 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
623 // Encode the shift operation.
630 case ARM::MOVsrl_flag:
632 Binary |= (0x2 << 4) | (1 << 7);
634 case ARM::MOVsra_flag:
636 Binary |= (0x4 << 4) | (1 << 7);
640 // Encode register Rm.
641 Binary |= getMachineOpValue(MI, 1);
646 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
647 DEBUG(errs() << " ** LPC" << LabelID << " @ "
648 << (void*)MCE.getCurrentPCValue() << '\n');
649 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
652 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
653 unsigned Opcode = MI.getDesc().Opcode;
656 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
657 case TargetOpcode::INLINEASM: {
658 // We allow inline assembler nodes with empty bodies - they can
659 // implicitly define registers, which is ok for JIT.
660 if (MI.getOperand(0).getSymbolName()[0]) {
661 report_fatal_error("JIT does not support inline asm!");
665 case TargetOpcode::PROLOG_LABEL:
666 case TargetOpcode::EH_LABEL:
667 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
669 case TargetOpcode::IMPLICIT_DEF:
670 case TargetOpcode::KILL:
673 case ARM::CONSTPOOL_ENTRY:
674 emitConstPoolInstruction(MI);
677 // Remember of the address of the PC label for relocation later.
678 addPCLabel(MI.getOperand(2).getImm());
679 // PICADD is just an add instruction that implicitly read pc.
680 emitDataProcessingInstruction(MI, 0, ARM::PC);
687 // Remember of the address of the PC label for relocation later.
688 addPCLabel(MI.getOperand(2).getImm());
689 // These are just load / store instructions that implicitly read pc.
690 emitLoadStoreInstruction(MI, 0, ARM::PC);
697 // Remember of the address of the PC label for relocation later.
698 addPCLabel(MI.getOperand(2).getImm());
699 // These are just load / store instructions that implicitly read pc.
700 emitMiscLoadStoreInstruction(MI, ARM::PC);
705 emitMOVi32immInstruction(MI);
708 case ARM::MOVi2pieces:
709 // Two instructions to materialize a constant.
710 emitMOVi2piecesInstruction(MI);
712 case ARM::LEApcrelJT:
713 // Materialize jumptable address.
714 emitLEApcrelJTInstruction(MI);
717 case ARM::MOVsrl_flag:
718 case ARM::MOVsra_flag:
719 emitPseudoMoveInstruction(MI);
724 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
725 const TargetInstrDesc &TID,
726 const MachineOperand &MO,
728 unsigned Binary = getMachineOpValue(MI, MO);
730 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
731 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
732 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
734 // Encode the shift opcode.
736 unsigned Rs = MO1.getReg();
738 // Set shift operand (bit[7:4]).
743 // RRX - 0110 and bit[11:8] clear.
745 default: llvm_unreachable("Unknown shift opc!");
746 case ARM_AM::lsl: SBits = 0x1; break;
747 case ARM_AM::lsr: SBits = 0x3; break;
748 case ARM_AM::asr: SBits = 0x5; break;
749 case ARM_AM::ror: SBits = 0x7; break;
750 case ARM_AM::rrx: SBits = 0x6; break;
753 // Set shift operand (bit[6:4]).
759 default: llvm_unreachable("Unknown shift opc!");
760 case ARM_AM::lsl: SBits = 0x0; break;
761 case ARM_AM::lsr: SBits = 0x2; break;
762 case ARM_AM::asr: SBits = 0x4; break;
763 case ARM_AM::ror: SBits = 0x6; break;
766 Binary |= SBits << 4;
767 if (SOpc == ARM_AM::rrx)
770 // Encode the shift operation Rs or shift_imm (except rrx).
772 // Encode Rs bit[11:8].
773 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
775 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
778 // Encode shift_imm bit[11:7].
779 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
782 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
783 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
784 assert(SoImmVal != -1 && "Not a valid so_imm value!");
786 // Encode rotate_imm.
787 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
788 << ARMII::SoRotImmShift;
791 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
795 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
796 const TargetInstrDesc &TID) const {
797 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
798 const MachineOperand &MO = MI.getOperand(i-1);
799 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
800 return 1 << ARMII::S_BitShift;
805 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
807 unsigned ImplicitRn) {
808 const TargetInstrDesc &TID = MI.getDesc();
810 // Part of binary is determined by TableGn.
811 unsigned Binary = getBinaryCodeForInstr(MI);
813 // Set the conditional execution predicate
814 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
816 // Encode S bit if MI modifies CPSR.
817 Binary |= getAddrModeSBit(MI, TID);
819 // Encode register def if there is one.
820 unsigned NumDefs = TID.getNumDefs();
823 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
825 // Special handling for implicit use (e.g. PC).
826 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
827 << ARMII::RegRdShift);
829 if (TID.Opcode == ARM::MOVi16) {
830 // Get immediate from MI.
831 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
832 ARM::reloc_arm_movw);
833 // Encode imm which is the same as in emitMOVi32immInstruction().
834 Binary |= Lo16 & 0xFFF;
835 Binary |= ((Lo16 >> 12) & 0xF) << 16;
838 } else if(TID.Opcode == ARM::MOVTi16) {
839 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
840 ARM::reloc_arm_movt) >> 16);
841 Binary |= Hi16 & 0xFFF;
842 Binary |= ((Hi16 >> 12) & 0xF) << 16;
845 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
846 uint32_t v = ~MI.getOperand(2).getImm();
847 int32_t lsb = CountTrailingZeros_32(v);
848 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
849 // Instr{20-16} = msb, Instr{11-7} = lsb
850 Binary |= (msb & 0x1F) << 16;
851 Binary |= (lsb & 0x1F) << 7;
854 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
855 // Encode Rn in Instr{0-3}
856 Binary |= getMachineOpValue(MI, OpIdx++);
858 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
859 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
861 // Instr{20-16} = widthm1, Instr{11-7} = lsb
862 Binary |= (widthm1 & 0x1F) << 16;
863 Binary |= (lsb & 0x1F) << 7;
868 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
869 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
872 // Encode first non-shifter register operand if there is one.
873 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
876 // Special handling for implicit use (e.g. PC).
877 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
878 << ARMII::RegRnShift);
880 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
885 // Encode shifter operand.
886 const MachineOperand &MO = MI.getOperand(OpIdx);
887 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
889 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
894 // Encode register Rm.
895 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
900 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
905 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
907 unsigned ImplicitRn) {
908 const TargetInstrDesc &TID = MI.getDesc();
909 unsigned Form = TID.TSFlags & ARMII::FormMask;
910 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
912 // Part of binary is determined by TableGn.
913 unsigned Binary = getBinaryCodeForInstr(MI);
915 // Set the conditional execution predicate
916 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
920 // Operand 0 of a pre- and post-indexed store is the address base
921 // writeback. Skip it.
922 bool Skipped = false;
923 if (IsPrePost && Form == ARMII::StFrm) {
930 // Special handling for implicit use (e.g. PC).
931 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
932 << ARMII::RegRdShift);
934 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
936 // Set second operand
938 // Special handling for implicit use (e.g. PC).
939 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
940 << ARMII::RegRnShift);
942 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
944 // If this is a two-address operand, skip it. e.g. LDR_PRE.
945 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
948 const MachineOperand &MO2 = MI.getOperand(OpIdx);
949 unsigned AM2Opc = (ImplicitRn == ARM::PC)
950 ? 0 : MI.getOperand(OpIdx+1).getImm();
952 // Set bit U(23) according to sign of immed value (positive or negative).
953 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
955 if (!MO2.getReg()) { // is immediate
956 if (ARM_AM::getAM2Offset(AM2Opc))
957 // Set the value of offset_12 field
958 Binary |= ARM_AM::getAM2Offset(AM2Opc);
963 // Set bit I(25), because this is not in immediate enconding.
964 Binary |= 1 << ARMII::I_BitShift;
965 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
966 // Set bit[3:0] to the corresponding Rm register
967 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
969 // If this instr is in scaled register offset/index instruction, set
970 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
971 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
972 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
973 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
979 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
980 unsigned ImplicitRn) {
981 const TargetInstrDesc &TID = MI.getDesc();
982 unsigned Form = TID.TSFlags & ARMII::FormMask;
983 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
985 // Part of binary is determined by TableGn.
986 unsigned Binary = getBinaryCodeForInstr(MI);
988 // Set the conditional execution predicate
989 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
993 // Operand 0 of a pre- and post-indexed store is the address base
994 // writeback. Skip it.
995 bool Skipped = false;
996 if (IsPrePost && Form == ARMII::StMiscFrm) {
1001 // Set first operand
1002 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1004 // Skip LDRD and STRD's second operand.
1005 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1008 // Set second operand
1010 // Special handling for implicit use (e.g. PC).
1011 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1012 << ARMII::RegRnShift);
1014 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1016 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1017 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1020 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1021 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1022 ? 0 : MI.getOperand(OpIdx+1).getImm();
1024 // Set bit U(23) according to sign of immed value (positive or negative)
1025 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1028 // If this instr is in register offset/index encoding, set bit[3:0]
1029 // to the corresponding Rm register.
1031 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1036 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1037 Binary |= 1 << ARMII::AM3_I_BitShift;
1038 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1040 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1041 Binary |= (ImmOffs & 0xF); // immedL
1047 static unsigned getAddrModeUPBits(unsigned Mode) {
1048 unsigned Binary = 0;
1050 // Set addressing mode by modifying bits U(23) and P(24)
1051 // IA - Increment after - bit U = 1 and bit P = 0
1052 // IB - Increment before - bit U = 1 and bit P = 1
1053 // DA - Decrement after - bit U = 0 and bit P = 0
1054 // DB - Decrement before - bit U = 0 and bit P = 1
1056 default: llvm_unreachable("Unknown addressing sub-mode!");
1057 case ARM_AM::da: break;
1058 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1059 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1060 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1066 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1067 const TargetInstrDesc &TID = MI.getDesc();
1068 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1070 // Part of binary is determined by TableGn.
1071 unsigned Binary = getBinaryCodeForInstr(MI);
1073 // Set the conditional execution predicate
1074 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1076 // Skip operand 0 of an instruction with base register update.
1081 // Set base address operand
1082 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1084 // Set addressing mode by modifying bits U(23) and P(24)
1085 const MachineOperand &MO = MI.getOperand(OpIdx++);
1086 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1090 Binary |= 0x1 << ARMII::W_BitShift;
1093 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1094 const MachineOperand &MO = MI.getOperand(i);
1095 if (!MO.isReg() || MO.isImplicit())
1097 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1098 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1100 Binary |= 0x1 << RegNum;
1106 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1107 const TargetInstrDesc &TID = MI.getDesc();
1109 // Part of binary is determined by TableGn.
1110 unsigned Binary = getBinaryCodeForInstr(MI);
1112 // Set the conditional execution predicate
1113 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1115 // Encode S bit if MI modifies CPSR.
1116 Binary |= getAddrModeSBit(MI, TID);
1118 // 32x32->64bit operations have two destination registers. The number
1119 // of register definitions will tell us if that's what we're dealing with.
1121 if (TID.getNumDefs() == 2)
1122 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1125 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1128 Binary |= getMachineOpValue(MI, OpIdx++);
1131 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1133 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1134 // it as Rn (for multiply, that's in the same offset as RdLo.
1135 if (TID.getNumOperands() > OpIdx &&
1136 !TID.OpInfo[OpIdx].isPredicate() &&
1137 !TID.OpInfo[OpIdx].isOptionalDef())
1138 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1143 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1144 const TargetInstrDesc &TID = MI.getDesc();
1146 // Part of binary is determined by TableGn.
1147 unsigned Binary = getBinaryCodeForInstr(MI);
1149 // Set the conditional execution predicate
1150 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1155 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1157 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1158 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1160 // Two register operand form.
1162 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1165 Binary |= getMachineOpValue(MI, MO2);
1168 Binary |= getMachineOpValue(MI, MO1);
1171 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1172 if (MI.getOperand(OpIdx).isImm() &&
1173 !TID.OpInfo[OpIdx].isPredicate() &&
1174 !TID.OpInfo[OpIdx].isOptionalDef())
1175 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1180 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1181 const TargetInstrDesc &TID = MI.getDesc();
1183 // Part of binary is determined by TableGn.
1184 unsigned Binary = getBinaryCodeForInstr(MI);
1186 // Set the conditional execution predicate
1187 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1192 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1194 const MachineOperand &MO = MI.getOperand(OpIdx++);
1195 if (OpIdx == TID.getNumOperands() ||
1196 TID.OpInfo[OpIdx].isPredicate() ||
1197 TID.OpInfo[OpIdx].isOptionalDef()) {
1198 // Encode Rm and it's done.
1199 Binary |= getMachineOpValue(MI, MO);
1205 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1208 Binary |= getMachineOpValue(MI, OpIdx++);
1210 // Encode shift_imm.
1211 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1212 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1213 Binary |= ShiftAmt << ARMII::ShiftShift;
1218 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1219 const TargetInstrDesc &TID = MI.getDesc();
1221 if (TID.Opcode == ARM::TPsoft) {
1222 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1225 // Part of binary is determined by TableGn.
1226 unsigned Binary = getBinaryCodeForInstr(MI);
1228 // Set the conditional execution predicate
1229 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1231 // Set signed_immed_24 field
1232 Binary |= getMachineOpValue(MI, 0);
1237 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1238 // Remember the base address of the inline jump table.
1239 uintptr_t JTBase = MCE.getCurrentPCValue();
1240 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1241 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1244 // Now emit the jump table entries.
1245 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1246 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1248 // DestBB address - JT base.
1249 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1251 // Absolute DestBB address.
1252 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1257 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1258 const TargetInstrDesc &TID = MI.getDesc();
1260 // Handle jump tables.
1261 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1262 // First emit a ldr pc, [] instruction.
1263 emitDataProcessingInstruction(MI, ARM::PC);
1265 // Then emit the inline jump table.
1267 (TID.Opcode == ARM::BR_JTr)
1268 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1269 emitInlineJumpTable(JTIndex);
1271 } else if (TID.Opcode == ARM::BR_JTm) {
1272 // First emit a ldr pc, [] instruction.
1273 emitLoadStoreInstruction(MI, ARM::PC);
1275 // Then emit the inline jump table.
1276 emitInlineJumpTable(MI.getOperand(3).getIndex());
1280 // Part of binary is determined by TableGn.
1281 unsigned Binary = getBinaryCodeForInstr(MI);
1283 // Set the conditional execution predicate
1284 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1286 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1287 // The return register is LR.
1288 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1290 // otherwise, set the return register
1291 Binary |= getMachineOpValue(MI, 0);
1296 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1297 unsigned RegD = MI.getOperand(OpIdx).getReg();
1298 unsigned Binary = 0;
1299 bool isSPVFP = false;
1300 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1302 Binary |= RegD << ARMII::RegRdShift;
1304 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1305 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1310 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1311 unsigned RegN = MI.getOperand(OpIdx).getReg();
1312 unsigned Binary = 0;
1313 bool isSPVFP = false;
1314 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1316 Binary |= RegN << ARMII::RegRnShift;
1318 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1319 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1324 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1325 unsigned RegM = MI.getOperand(OpIdx).getReg();
1326 unsigned Binary = 0;
1327 bool isSPVFP = false;
1328 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1332 Binary |= ((RegM & 0x1E) >> 1);
1333 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1338 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1339 const TargetInstrDesc &TID = MI.getDesc();
1341 // Part of binary is determined by TableGn.
1342 unsigned Binary = getBinaryCodeForInstr(MI);
1344 // Set the conditional execution predicate
1345 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1348 assert((Binary & ARMII::D_BitShift) == 0 &&
1349 (Binary & ARMII::N_BitShift) == 0 &&
1350 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1353 Binary |= encodeVFPRd(MI, OpIdx++);
1355 // If this is a two-address operand, skip it, e.g. FMACD.
1356 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1360 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1361 Binary |= encodeVFPRn(MI, OpIdx++);
1363 if (OpIdx == TID.getNumOperands() ||
1364 TID.OpInfo[OpIdx].isPredicate() ||
1365 TID.OpInfo[OpIdx].isOptionalDef()) {
1366 // FCMPEZD etc. has only one operand.
1372 Binary |= encodeVFPRm(MI, OpIdx);
1377 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1378 const TargetInstrDesc &TID = MI.getDesc();
1379 unsigned Form = TID.TSFlags & ARMII::FormMask;
1381 // Part of binary is determined by TableGn.
1382 unsigned Binary = getBinaryCodeForInstr(MI);
1384 // Set the conditional execution predicate
1385 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1389 case ARMII::VFPConv1Frm:
1390 case ARMII::VFPConv2Frm:
1391 case ARMII::VFPConv3Frm:
1393 Binary |= encodeVFPRd(MI, 0);
1395 case ARMII::VFPConv4Frm:
1397 Binary |= encodeVFPRn(MI, 0);
1399 case ARMII::VFPConv5Frm:
1401 Binary |= encodeVFPRm(MI, 0);
1407 case ARMII::VFPConv1Frm:
1409 Binary |= encodeVFPRm(MI, 1);
1411 case ARMII::VFPConv2Frm:
1412 case ARMII::VFPConv3Frm:
1414 Binary |= encodeVFPRn(MI, 1);
1416 case ARMII::VFPConv4Frm:
1417 case ARMII::VFPConv5Frm:
1419 Binary |= encodeVFPRd(MI, 1);
1423 if (Form == ARMII::VFPConv5Frm)
1425 Binary |= encodeVFPRn(MI, 2);
1426 else if (Form == ARMII::VFPConv3Frm)
1428 Binary |= encodeVFPRm(MI, 2);
1433 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1434 // Part of binary is determined by TableGn.
1435 unsigned Binary = getBinaryCodeForInstr(MI);
1437 // Set the conditional execution predicate
1438 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1443 Binary |= encodeVFPRd(MI, OpIdx++);
1445 // Encode address base.
1446 const MachineOperand &Base = MI.getOperand(OpIdx++);
1447 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1449 // If there is a non-zero immediate offset, encode it.
1451 const MachineOperand &Offset = MI.getOperand(OpIdx);
1452 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1453 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1454 Binary |= 1 << ARMII::U_BitShift;
1461 // If immediate offset is omitted, default to +0.
1462 Binary |= 1 << ARMII::U_BitShift;
1468 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1469 const TargetInstrDesc &TID = MI.getDesc();
1470 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1472 // Part of binary is determined by TableGn.
1473 unsigned Binary = getBinaryCodeForInstr(MI);
1475 // Set the conditional execution predicate
1476 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1478 // Skip operand 0 of an instruction with base register update.
1483 // Set base address operand
1484 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1486 // Set addressing mode by modifying bits U(23) and P(24)
1487 const MachineOperand &MO = MI.getOperand(OpIdx++);
1488 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1492 Binary |= 0x1 << ARMII::W_BitShift;
1494 // First register is encoded in Dd.
1495 Binary |= encodeVFPRd(MI, OpIdx+2);
1497 // Number of registers are encoded in offset field.
1498 unsigned NumRegs = 1;
1499 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1500 const MachineOperand &MO = MI.getOperand(i);
1501 if (!MO.isReg() || MO.isImplicit())
1505 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1506 // Otherwise, it will be 0, in the case of 32-bit registers.
1508 Binary |= NumRegs * 2;
1515 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1516 unsigned Opcode = MI.getDesc().Opcode;
1517 // Part of binary is determined by TableGn.
1518 unsigned Binary = getBinaryCodeForInstr(MI);
1520 // Set the conditional execution predicate
1521 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1525 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1528 // No further encoding needed.
1533 const MachineOperand &MO0 = MI.getOperand(0);
1535 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1536 << ARMII::RegRdShift;
1541 case ARM::FCONSTS: {
1543 Binary |= encodeVFPRd(MI, 0);
1545 // Encode imm., Table A7-18 VFP modified immediate constants
1546 const MachineOperand &MO1 = MI.getOperand(1);
1547 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1548 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1549 unsigned ModifiedImm;
1551 if(Opcode == ARM::FCONSTS)
1552 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1553 (Imm & 0x03F80000) >> 19; // bcdefgh
1554 else // Opcode == ARM::FCONSTD
1555 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1556 (Imm & 0x007F0000) >> 16; // bcdefgh
1558 // Insts{19-16} = abcd, Insts{3-0} = efgh
1559 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1560 Binary |= (ModifiedImm & 0xF);
1568 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1569 unsigned RegD = MI.getOperand(OpIdx).getReg();
1570 unsigned Binary = 0;
1571 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1572 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1573 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1577 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1578 unsigned RegN = MI.getOperand(OpIdx).getReg();
1579 unsigned Binary = 0;
1580 RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1581 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1582 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1586 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1587 unsigned RegM = MI.getOperand(OpIdx).getReg();
1588 unsigned Binary = 0;
1589 RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1590 Binary |= (RegM & 0xf);
1591 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1595 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1596 /// data-processing instruction to the corresponding Thumb encoding.
1597 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1598 assert((Binary & 0xfe000000) == 0xf2000000 &&
1599 "not an ARM NEON data-processing instruction");
1600 unsigned UBit = (Binary >> 24) & 1;
1601 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1604 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1605 unsigned Binary = getBinaryCodeForInstr(MI);
1607 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1608 const TargetInstrDesc &TID = MI.getDesc();
1609 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1613 } else { // ARMII::NSetLnFrm
1619 // Set the conditional execution predicate
1620 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1622 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1623 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1624 Binary |= (RegT << ARMII::RegRdShift);
1625 Binary |= encodeNEONRn(MI, RegNOpIdx);
1628 if ((Binary & (1 << 22)) != 0)
1629 LaneShift = 0; // 8-bit elements
1630 else if ((Binary & (1 << 5)) != 0)
1631 LaneShift = 1; // 16-bit elements
1633 LaneShift = 2; // 32-bit elements
1635 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1636 unsigned Opc1 = Lane >> 2;
1637 unsigned Opc2 = Lane & 3;
1638 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1639 Binary |= (Opc1 << 21);
1640 Binary |= (Opc2 << 5);
1645 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1646 unsigned Binary = getBinaryCodeForInstr(MI);
1648 // Set the conditional execution predicate
1649 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1651 unsigned RegT = MI.getOperand(1).getReg();
1652 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1653 Binary |= (RegT << ARMII::RegRdShift);
1654 Binary |= encodeNEONRn(MI, 0);
1658 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1659 unsigned Binary = getBinaryCodeForInstr(MI);
1660 // Destination register is encoded in Dd.
1661 Binary |= encodeNEONRd(MI, 0);
1662 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1663 unsigned Imm = MI.getOperand(1).getImm();
1664 unsigned Op = (Imm >> 12) & 1;
1665 unsigned Cmode = (Imm >> 8) & 0xf;
1666 unsigned I = (Imm >> 7) & 1;
1667 unsigned Imm3 = (Imm >> 4) & 0x7;
1668 unsigned Imm4 = Imm & 0xf;
1669 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1671 Binary = convertNEONDataProcToThumb(Binary);
1675 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1676 const TargetInstrDesc &TID = MI.getDesc();
1677 unsigned Binary = getBinaryCodeForInstr(MI);
1678 // Destination register is encoded in Dd; source register in Dm.
1680 Binary |= encodeNEONRd(MI, OpIdx++);
1681 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1683 Binary |= encodeNEONRm(MI, OpIdx);
1685 Binary = convertNEONDataProcToThumb(Binary);
1686 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1690 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1691 const TargetInstrDesc &TID = MI.getDesc();
1692 unsigned Binary = getBinaryCodeForInstr(MI);
1693 // Destination register is encoded in Dd; source registers in Dn and Dm.
1695 Binary |= encodeNEONRd(MI, OpIdx++);
1696 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1698 Binary |= encodeNEONRn(MI, OpIdx++);
1699 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1701 Binary |= encodeNEONRm(MI, OpIdx);
1703 Binary = convertNEONDataProcToThumb(Binary);
1704 // FIXME: This does not handle VMOVDneon or VMOVQ.
1708 #include "ARMGenCodeEmitter.inc"