1 const //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitMiscInstruction(const MachineInstr &MI);
145 void emitNEONLaneInstruction(const MachineInstr &MI);
146 void emitNEONDupInstruction(const MachineInstr &MI);
147 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148 void emitNEON2RegInstruction(const MachineInstr &MI);
149 void emitNEON3RegInstruction(const MachineInstr &MI);
151 /// getMachineOpValue - Return binary encoding of operand. If the machine
152 /// operand requires relocation, record the relocation and return zero.
153 unsigned getMachineOpValue(const MachineInstr &MI,
154 const MachineOperand &MO) const;
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
160 /// machine operand requires relocation, record the relocation and return
162 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
165 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167 unsigned getShiftOp(unsigned Imm) const ;
169 /// Routines that handle operands which add machine relocations which are
170 /// fixed up by the relocation stage.
171 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
172 bool MayNeedFarStub, bool Indirect,
173 intptr_t ACPV = 0) const;
174 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
175 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
176 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
177 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
178 intptr_t JTBase = 0) const;
182 char ARMCodeEmitter::ID = 0;
184 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
185 /// code to the specified MCE object.
186 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
187 JITCodeEmitter &JCE) {
188 return new ARMCodeEmitter(TM, JCE);
191 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
192 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
193 MF.getTarget().getRelocationModel() != Reloc::Static) &&
194 "JIT relocation model must be set to static or default!");
195 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
196 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
197 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
198 Subtarget = &TM.getSubtarget<ARMSubtarget>();
199 MCPEs = &MF.getConstantPool()->getConstants();
201 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
202 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
203 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
204 JTI->Initialize(MF, IsPIC);
205 MMI = &getAnalysis<MachineModuleInfo>();
206 MCE.setModuleInfo(MMI);
209 DEBUG(errs() << "JITTing function '"
210 << MF.getFunction()->getName() << "'\n");
211 MCE.startFunction(MF);
212 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
214 MCE.StartMachineBasicBlock(MBB);
215 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
219 } while (MCE.finishFunction(MF));
224 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
227 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
228 default: llvm_unreachable("Unknown shift opc!");
229 case ARM_AM::asr: return 2;
230 case ARM_AM::lsl: return 0;
231 case ARM_AM::lsr: return 1;
233 case ARM_AM::rrx: return 3;
238 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
239 /// machine operand requires relocation, record the relocation and return zero.
240 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
241 const MachineOperand &MO,
243 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
244 && "Relocation to this function should be for movt or movw");
247 return static_cast<unsigned>(MO.getImm());
248 else if (MO.isGlobal())
249 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
250 else if (MO.isSymbol())
251 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
253 emitMachineBasicBlock(MO.getMBB(), Reloc);
258 llvm_unreachable("Unsupported operand type for movw/movt");
263 /// getMachineOpValue - Return binary encoding of operand. If the machine
264 /// operand requires relocation, record the relocation and return zero.
265 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
266 const MachineOperand &MO) const {
268 return getARMRegisterNumbering(MO.getReg());
270 return static_cast<unsigned>(MO.getImm());
271 else if (MO.isGlobal())
272 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
273 else if (MO.isSymbol())
274 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
275 else if (MO.isCPI()) {
276 const TargetInstrDesc &TID = MI.getDesc();
277 // For VFP load, the immediate offset is multiplied by 4.
278 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
279 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
280 emitConstPoolAddress(MO.getIndex(), Reloc);
281 } else if (MO.isJTI())
282 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
284 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
294 /// emitGlobalAddress - Emit the specified address to the code stream.
296 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
297 bool MayNeedFarStub, bool Indirect,
298 intptr_t ACPV) const {
299 MachineRelocation MR = Indirect
300 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
301 const_cast<GlobalValue *>(GV),
302 ACPV, MayNeedFarStub)
303 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
304 const_cast<GlobalValue *>(GV), ACPV,
306 MCE.addRelocation(MR);
309 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
310 /// be emitted to the current location in the function, and allow it to be PC
312 void ARMCodeEmitter::
313 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
314 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
318 /// emitConstPoolAddress - Arrange for the address of an constant pool
319 /// to be emitted to the current location in the function, and allow it to be PC
321 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
322 // Tell JIT emitter we'll resolve the address.
323 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
324 Reloc, CPI, 0, true));
327 /// emitJumpTableAddress - Arrange for the address of a jump table to
328 /// be emitted to the current location in the function, and allow it to be PC
330 void ARMCodeEmitter::
331 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
332 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
333 Reloc, JTIndex, 0, true));
336 /// emitMachineBasicBlock - Emit the specified address basic block.
337 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
339 intptr_t JTBase) const {
340 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
344 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
345 DEBUG(errs() << " 0x";
346 errs().write_hex(Binary) << "\n");
347 MCE.emitWordLE(Binary);
350 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
351 DEBUG(errs() << " 0x";
352 errs().write_hex(Binary) << "\n");
353 MCE.emitDWordLE(Binary);
356 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
357 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
359 MCE.processDebugLoc(MI.getDebugLoc(), true);
361 ++NumEmitted; // Keep track of the # of mi's emitted
362 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
364 llvm_unreachable("Unhandled instruction encoding format!");
368 emitPseudoInstruction(MI);
371 case ARMII::DPSoRegFrm:
372 emitDataProcessingInstruction(MI);
376 emitLoadStoreInstruction(MI);
378 case ARMII::LdMiscFrm:
379 case ARMII::StMiscFrm:
380 emitMiscLoadStoreInstruction(MI);
382 case ARMII::LdStMulFrm:
383 emitLoadStoreMultipleInstruction(MI);
386 emitMulFrmInstruction(MI);
389 emitExtendInstruction(MI);
391 case ARMII::ArithMiscFrm:
392 emitMiscArithInstruction(MI);
395 emitSaturateInstruction(MI);
398 emitBranchInstruction(MI);
400 case ARMII::BrMiscFrm:
401 emitMiscBranchInstruction(MI);
404 case ARMII::VFPUnaryFrm:
405 case ARMII::VFPBinaryFrm:
406 emitVFPArithInstruction(MI);
408 case ARMII::VFPConv1Frm:
409 case ARMII::VFPConv2Frm:
410 case ARMII::VFPConv3Frm:
411 case ARMII::VFPConv4Frm:
412 case ARMII::VFPConv5Frm:
413 emitVFPConversionInstruction(MI);
415 case ARMII::VFPLdStFrm:
416 emitVFPLoadStoreInstruction(MI);
418 case ARMII::VFPLdStMulFrm:
419 emitVFPLoadStoreMultipleInstruction(MI);
421 case ARMII::VFPMiscFrm:
422 emitMiscInstruction(MI);
424 // NEON instructions.
425 case ARMII::NGetLnFrm:
426 case ARMII::NSetLnFrm:
427 emitNEONLaneInstruction(MI);
430 emitNEONDupInstruction(MI);
432 case ARMII::N1RegModImmFrm:
433 emitNEON1RegModImmInstruction(MI);
435 case ARMII::N2RegFrm:
436 emitNEON2RegInstruction(MI);
438 case ARMII::N3RegFrm:
439 emitNEON3RegInstruction(MI);
442 MCE.processDebugLoc(MI.getDebugLoc(), false);
445 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
446 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
447 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
448 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
450 // Remember the CONSTPOOL_ENTRY address for later relocation.
451 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
453 // Emit constpool island entry. In most cases, the actual values will be
454 // resolved and relocated after code emission.
455 if (MCPE.isMachineConstantPoolEntry()) {
456 ARMConstantPoolValue *ACPV =
457 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
459 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
460 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
462 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
463 const GlobalValue *GV = ACPV->getGV();
465 Reloc::Model RelocM = TM.getRelocationModel();
466 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
468 Subtarget->GVIsIndirectSymbol(GV, RelocM),
471 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
475 const Constant *CV = MCPE.Val.ConstVal;
478 errs() << " ** Constant pool #" << CPI << " @ "
479 << (void*)MCE.getCurrentPCValue() << " ";
480 if (const Function *F = dyn_cast<Function>(CV))
481 errs() << F->getName();
487 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
488 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
490 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
491 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
493 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
494 if (CFP->getType()->isFloatTy())
495 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
496 else if (CFP->getType()->isDoubleTy())
497 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
499 llvm_unreachable("Unable to handle this constantpool entry!");
502 llvm_unreachable("Unable to handle this constantpool entry!");
507 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
508 const MachineOperand &MO0 = MI.getOperand(0);
509 const MachineOperand &MO1 = MI.getOperand(1);
511 // Emit the 'movw' instruction.
512 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
514 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
516 // Set the conditional execution predicate.
517 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
522 // Encode imm16 as imm4:imm12
523 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
524 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
527 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
528 // Emit the 'movt' instruction.
529 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
531 // Set the conditional execution predicate.
532 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
535 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
537 // Encode imm16 as imm4:imm1, same as movw above.
538 Binary |= Hi16 & 0xFFF;
539 Binary |= ((Hi16 >> 12) & 0xF) << 16;
543 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
544 const MachineOperand &MO0 = MI.getOperand(0);
545 const MachineOperand &MO1 = MI.getOperand(1);
546 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
547 "Not a valid so_imm value!");
548 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
549 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
551 // Emit the 'mov' instruction.
552 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
554 // Set the conditional execution predicate.
555 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
558 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
561 // Set bit I(25) to identify this is the immediate form of <shifter_op>
562 Binary |= 1 << ARMII::I_BitShift;
563 Binary |= getMachineSoImmOpValue(V1);
566 // Now the 'orr' instruction.
567 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
569 // Set the conditional execution predicate.
570 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
573 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
576 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
579 // Set bit I(25) to identify this is the immediate form of <shifter_op>
580 Binary |= 1 << ARMII::I_BitShift;
581 Binary |= getMachineSoImmOpValue(V2);
585 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
586 // It's basically add r, pc, (LJTI - $+8)
588 const TargetInstrDesc &TID = MI.getDesc();
590 // Emit the 'add' instruction.
591 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
593 // Set the conditional execution predicate
594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
596 // Encode S bit if MI modifies CPSR.
597 Binary |= getAddrModeSBit(MI, TID);
600 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
602 // Encode Rn which is PC.
603 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
605 // Encode the displacement.
606 Binary |= 1 << ARMII::I_BitShift;
607 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
612 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
613 unsigned Opcode = MI.getDesc().Opcode;
615 // Part of binary is determined by TableGn.
616 unsigned Binary = getBinaryCodeForInstr(MI);
618 // Set the conditional execution predicate
619 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
621 // Encode S bit if MI modifies CPSR.
622 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
623 Binary |= 1 << ARMII::S_BitShift;
625 // Encode register def if there is one.
626 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
628 // Encode the shift operation.
635 case ARM::MOVsrl_flag:
637 Binary |= (0x2 << 4) | (1 << 7);
639 case ARM::MOVsra_flag:
641 Binary |= (0x4 << 4) | (1 << 7);
645 // Encode register Rm.
646 Binary |= getMachineOpValue(MI, 1);
651 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
652 DEBUG(errs() << " ** LPC" << LabelID << " @ "
653 << (void*)MCE.getCurrentPCValue() << '\n');
654 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
657 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
658 unsigned Opcode = MI.getDesc().Opcode;
661 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
665 case ARM::BMOVPCRXr9: {
666 // First emit mov lr, pc
667 unsigned Binary = 0x01a0e00f;
668 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
671 // and then emit the branch.
672 emitMiscBranchInstruction(MI);
675 case TargetOpcode::INLINEASM: {
676 // We allow inline assembler nodes with empty bodies - they can
677 // implicitly define registers, which is ok for JIT.
678 if (MI.getOperand(0).getSymbolName()[0]) {
679 report_fatal_error("JIT does not support inline asm!");
683 case TargetOpcode::PROLOG_LABEL:
684 case TargetOpcode::EH_LABEL:
685 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
687 case TargetOpcode::IMPLICIT_DEF:
688 case TargetOpcode::KILL:
691 case ARM::CONSTPOOL_ENTRY:
692 emitConstPoolInstruction(MI);
695 // Remember of the address of the PC label for relocation later.
696 addPCLabel(MI.getOperand(2).getImm());
697 // PICADD is just an add instruction that implicitly read pc.
698 emitDataProcessingInstruction(MI, 0, ARM::PC);
705 // Remember of the address of the PC label for relocation later.
706 addPCLabel(MI.getOperand(2).getImm());
707 // These are just load / store instructions that implicitly read pc.
708 emitLoadStoreInstruction(MI, 0, ARM::PC);
715 // Remember of the address of the PC label for relocation later.
716 addPCLabel(MI.getOperand(2).getImm());
717 // These are just load / store instructions that implicitly read pc.
718 emitMiscLoadStoreInstruction(MI, ARM::PC);
723 emitMOVi32immInstruction(MI);
726 case ARM::MOVi2pieces:
727 // Two instructions to materialize a constant.
728 emitMOVi2piecesInstruction(MI);
730 case ARM::LEApcrelJT:
731 // Materialize jumptable address.
732 emitLEApcrelJTInstruction(MI);
735 case ARM::MOVsrl_flag:
736 case ARM::MOVsra_flag:
737 emitPseudoMoveInstruction(MI);
742 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
743 const TargetInstrDesc &TID,
744 const MachineOperand &MO,
746 unsigned Binary = getMachineOpValue(MI, MO);
748 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
749 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
750 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
752 // Encode the shift opcode.
754 unsigned Rs = MO1.getReg();
756 // Set shift operand (bit[7:4]).
761 // RRX - 0110 and bit[11:8] clear.
763 default: llvm_unreachable("Unknown shift opc!");
764 case ARM_AM::lsl: SBits = 0x1; break;
765 case ARM_AM::lsr: SBits = 0x3; break;
766 case ARM_AM::asr: SBits = 0x5; break;
767 case ARM_AM::ror: SBits = 0x7; break;
768 case ARM_AM::rrx: SBits = 0x6; break;
771 // Set shift operand (bit[6:4]).
777 default: llvm_unreachable("Unknown shift opc!");
778 case ARM_AM::lsl: SBits = 0x0; break;
779 case ARM_AM::lsr: SBits = 0x2; break;
780 case ARM_AM::asr: SBits = 0x4; break;
781 case ARM_AM::ror: SBits = 0x6; break;
784 Binary |= SBits << 4;
785 if (SOpc == ARM_AM::rrx)
788 // Encode the shift operation Rs or shift_imm (except rrx).
790 // Encode Rs bit[11:8].
791 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
792 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
795 // Encode shift_imm bit[11:7].
796 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
799 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
800 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
801 assert(SoImmVal != -1 && "Not a valid so_imm value!");
803 // Encode rotate_imm.
804 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
805 << ARMII::SoRotImmShift;
808 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
812 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
813 const TargetInstrDesc &TID) const {
814 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
815 const MachineOperand &MO = MI.getOperand(i-1);
816 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
817 return 1 << ARMII::S_BitShift;
822 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
824 unsigned ImplicitRn) {
825 const TargetInstrDesc &TID = MI.getDesc();
827 // Part of binary is determined by TableGn.
828 unsigned Binary = getBinaryCodeForInstr(MI);
830 // Set the conditional execution predicate
831 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
833 // Encode S bit if MI modifies CPSR.
834 Binary |= getAddrModeSBit(MI, TID);
836 // Encode register def if there is one.
837 unsigned NumDefs = TID.getNumDefs();
840 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
842 // Special handling for implicit use (e.g. PC).
843 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
845 if (TID.Opcode == ARM::MOVi16) {
846 // Get immediate from MI.
847 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
848 ARM::reloc_arm_movw);
849 // Encode imm which is the same as in emitMOVi32immInstruction().
850 Binary |= Lo16 & 0xFFF;
851 Binary |= ((Lo16 >> 12) & 0xF) << 16;
854 } else if(TID.Opcode == ARM::MOVTi16) {
855 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
856 ARM::reloc_arm_movt) >> 16);
857 Binary |= Hi16 & 0xFFF;
858 Binary |= ((Hi16 >> 12) & 0xF) << 16;
861 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
862 uint32_t v = ~MI.getOperand(2).getImm();
863 int32_t lsb = CountTrailingZeros_32(v);
864 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
865 // Instr{20-16} = msb, Instr{11-7} = lsb
866 Binary |= (msb & 0x1F) << 16;
867 Binary |= (lsb & 0x1F) << 7;
870 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
871 // Encode Rn in Instr{0-3}
872 Binary |= getMachineOpValue(MI, OpIdx++);
874 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
875 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
877 // Instr{20-16} = widthm1, Instr{11-7} = lsb
878 Binary |= (widthm1 & 0x1F) << 16;
879 Binary |= (lsb & 0x1F) << 7;
884 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
885 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
888 // Encode first non-shifter register operand if there is one.
889 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
892 // Special handling for implicit use (e.g. PC).
893 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
895 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
900 // Encode shifter operand.
901 const MachineOperand &MO = MI.getOperand(OpIdx);
902 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
904 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
909 // Encode register Rm.
910 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
915 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
920 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
922 unsigned ImplicitRn) {
923 const TargetInstrDesc &TID = MI.getDesc();
924 unsigned Form = TID.TSFlags & ARMII::FormMask;
925 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
927 // Part of binary is determined by TableGn.
928 unsigned Binary = getBinaryCodeForInstr(MI);
930 // Set the conditional execution predicate
931 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
935 // Operand 0 of a pre- and post-indexed store is the address base
936 // writeback. Skip it.
937 bool Skipped = false;
938 if (IsPrePost && Form == ARMII::StFrm) {
945 // Special handling for implicit use (e.g. PC).
946 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
948 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
950 // Set second operand
952 // Special handling for implicit use (e.g. PC).
953 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
955 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
957 // If this is a two-address operand, skip it. e.g. LDR_PRE.
958 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
961 const MachineOperand &MO2 = MI.getOperand(OpIdx);
962 unsigned AM2Opc = (ImplicitRn == ARM::PC)
963 ? 0 : MI.getOperand(OpIdx+1).getImm();
965 // Set bit U(23) according to sign of immed value (positive or negative).
966 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
968 if (!MO2.getReg()) { // is immediate
969 if (ARM_AM::getAM2Offset(AM2Opc))
970 // Set the value of offset_12 field
971 Binary |= ARM_AM::getAM2Offset(AM2Opc);
976 // Set bit I(25), because this is not in immediate enconding.
977 Binary |= 1 << ARMII::I_BitShift;
978 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
979 // Set bit[3:0] to the corresponding Rm register
980 Binary |= getARMRegisterNumbering(MO2.getReg());
982 // If this instr is in scaled register offset/index instruction, set
983 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
984 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
985 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
986 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
992 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
993 unsigned ImplicitRn) {
994 const TargetInstrDesc &TID = MI.getDesc();
995 unsigned Form = TID.TSFlags & ARMII::FormMask;
996 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
998 // Part of binary is determined by TableGn.
999 unsigned Binary = getBinaryCodeForInstr(MI);
1001 // Set the conditional execution predicate
1002 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1006 // Operand 0 of a pre- and post-indexed store is the address base
1007 // writeback. Skip it.
1008 bool Skipped = false;
1009 if (IsPrePost && Form == ARMII::StMiscFrm) {
1014 // Set first operand
1015 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1017 // Skip LDRD and STRD's second operand.
1018 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1021 // Set second operand
1023 // Special handling for implicit use (e.g. PC).
1024 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1026 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1028 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1029 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1032 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1033 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1034 ? 0 : MI.getOperand(OpIdx+1).getImm();
1036 // Set bit U(23) according to sign of immed value (positive or negative)
1037 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1040 // If this instr is in register offset/index encoding, set bit[3:0]
1041 // to the corresponding Rm register.
1043 Binary |= getARMRegisterNumbering(MO2.getReg());
1048 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1049 Binary |= 1 << ARMII::AM3_I_BitShift;
1050 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1052 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1053 Binary |= (ImmOffs & 0xF); // immedL
1059 static unsigned getAddrModeUPBits(unsigned Mode) {
1060 unsigned Binary = 0;
1062 // Set addressing mode by modifying bits U(23) and P(24)
1063 // IA - Increment after - bit U = 1 and bit P = 0
1064 // IB - Increment before - bit U = 1 and bit P = 1
1065 // DA - Decrement after - bit U = 0 and bit P = 0
1066 // DB - Decrement before - bit U = 0 and bit P = 1
1068 default: llvm_unreachable("Unknown addressing sub-mode!");
1069 case ARM_AM::da: break;
1070 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1071 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1072 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1078 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1079 const TargetInstrDesc &TID = MI.getDesc();
1080 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1082 // Part of binary is determined by TableGn.
1083 unsigned Binary = getBinaryCodeForInstr(MI);
1085 // Set the conditional execution predicate
1086 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1088 // Skip operand 0 of an instruction with base register update.
1093 // Set base address operand
1094 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1096 // Set addressing mode by modifying bits U(23) and P(24)
1097 const MachineOperand &MO = MI.getOperand(OpIdx++);
1098 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1102 Binary |= 0x1 << ARMII::W_BitShift;
1105 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1106 const MachineOperand &MO = MI.getOperand(i);
1107 if (!MO.isReg() || MO.isImplicit())
1109 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1110 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1112 Binary |= 0x1 << RegNum;
1118 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1119 const TargetInstrDesc &TID = MI.getDesc();
1121 // Part of binary is determined by TableGn.
1122 unsigned Binary = getBinaryCodeForInstr(MI);
1124 // Set the conditional execution predicate
1125 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1127 // Encode S bit if MI modifies CPSR.
1128 Binary |= getAddrModeSBit(MI, TID);
1130 // 32x32->64bit operations have two destination registers. The number
1131 // of register definitions will tell us if that's what we're dealing with.
1133 if (TID.getNumDefs() == 2)
1134 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1137 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1140 Binary |= getMachineOpValue(MI, OpIdx++);
1143 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1145 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1146 // it as Rn (for multiply, that's in the same offset as RdLo.
1147 if (TID.getNumOperands() > OpIdx &&
1148 !TID.OpInfo[OpIdx].isPredicate() &&
1149 !TID.OpInfo[OpIdx].isOptionalDef())
1150 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1155 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1156 const TargetInstrDesc &TID = MI.getDesc();
1158 // Part of binary is determined by TableGn.
1159 unsigned Binary = getBinaryCodeForInstr(MI);
1161 // Set the conditional execution predicate
1162 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1167 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1169 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1170 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1172 // Two register operand form.
1174 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1177 Binary |= getMachineOpValue(MI, MO2);
1180 Binary |= getMachineOpValue(MI, MO1);
1183 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1184 if (MI.getOperand(OpIdx).isImm() &&
1185 !TID.OpInfo[OpIdx].isPredicate() &&
1186 !TID.OpInfo[OpIdx].isOptionalDef())
1187 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1192 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1193 const TargetInstrDesc &TID = MI.getDesc();
1195 // Part of binary is determined by TableGn.
1196 unsigned Binary = getBinaryCodeForInstr(MI);
1198 // Set the conditional execution predicate
1199 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1204 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1206 const MachineOperand &MO = MI.getOperand(OpIdx++);
1207 if (OpIdx == TID.getNumOperands() ||
1208 TID.OpInfo[OpIdx].isPredicate() ||
1209 TID.OpInfo[OpIdx].isOptionalDef()) {
1210 // Encode Rm and it's done.
1211 Binary |= getMachineOpValue(MI, MO);
1217 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1220 Binary |= getMachineOpValue(MI, OpIdx++);
1222 // Encode shift_imm.
1223 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1224 if (TID.Opcode == ARM::PKHTB) {
1225 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1229 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1230 Binary |= ShiftAmt << ARMII::ShiftShift;
1235 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1236 const TargetInstrDesc &TID = MI.getDesc();
1238 // Part of binary is determined by TableGen.
1239 unsigned Binary = getBinaryCodeForInstr(MI);
1241 // Set the conditional execution predicate
1242 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1245 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1247 // Encode saturate bit position.
1248 unsigned Pos = MI.getOperand(1).getImm();
1249 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1251 assert((Pos < 16 || (Pos < 32 &&
1252 TID.Opcode != ARM::SSAT16 &&
1253 TID.Opcode != ARM::USAT16)) &&
1254 "saturate bit position out of range");
1255 Binary |= Pos << 16;
1258 Binary |= getMachineOpValue(MI, 2);
1260 // Encode shift_imm.
1261 if (TID.getNumOperands() == 4) {
1262 unsigned ShiftOp = MI.getOperand(3).getImm();
1263 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1264 if (Opc == ARM_AM::asr)
1266 unsigned ShiftAmt = MI.getOperand(3).getImm();
1267 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1269 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1270 Binary |= ShiftAmt << ARMII::ShiftShift;
1276 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1277 const TargetInstrDesc &TID = MI.getDesc();
1279 if (TID.Opcode == ARM::TPsoft) {
1280 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1283 // Part of binary is determined by TableGn.
1284 unsigned Binary = getBinaryCodeForInstr(MI);
1286 // Set the conditional execution predicate
1287 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1289 // Set signed_immed_24 field
1290 Binary |= getMachineOpValue(MI, 0);
1295 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1296 // Remember the base address of the inline jump table.
1297 uintptr_t JTBase = MCE.getCurrentPCValue();
1298 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1299 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1302 // Now emit the jump table entries.
1303 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1304 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1306 // DestBB address - JT base.
1307 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1309 // Absolute DestBB address.
1310 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1315 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1316 const TargetInstrDesc &TID = MI.getDesc();
1318 // Handle jump tables.
1319 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1320 // First emit a ldr pc, [] instruction.
1321 emitDataProcessingInstruction(MI, ARM::PC);
1323 // Then emit the inline jump table.
1325 (TID.Opcode == ARM::BR_JTr)
1326 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1327 emitInlineJumpTable(JTIndex);
1329 } else if (TID.Opcode == ARM::BR_JTm) {
1330 // First emit a ldr pc, [] instruction.
1331 emitLoadStoreInstruction(MI, ARM::PC);
1333 // Then emit the inline jump table.
1334 emitInlineJumpTable(MI.getOperand(3).getIndex());
1338 // Part of binary is determined by TableGn.
1339 unsigned Binary = getBinaryCodeForInstr(MI);
1341 // Set the conditional execution predicate
1342 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1345 // The return register is LR.
1346 Binary |= getARMRegisterNumbering(ARM::LR);
1348 // otherwise, set the return register
1349 Binary |= getMachineOpValue(MI, 0);
1354 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1355 unsigned RegD = MI.getOperand(OpIdx).getReg();
1356 unsigned Binary = 0;
1357 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1358 RegD = getARMRegisterNumbering(RegD);
1360 Binary |= RegD << ARMII::RegRdShift;
1362 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1363 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1368 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1369 unsigned RegN = MI.getOperand(OpIdx).getReg();
1370 unsigned Binary = 0;
1371 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1372 RegN = getARMRegisterNumbering(RegN);
1374 Binary |= RegN << ARMII::RegRnShift;
1376 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1377 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1382 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1383 unsigned RegM = MI.getOperand(OpIdx).getReg();
1384 unsigned Binary = 0;
1385 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1386 RegM = getARMRegisterNumbering(RegM);
1390 Binary |= ((RegM & 0x1E) >> 1);
1391 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1396 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1397 const TargetInstrDesc &TID = MI.getDesc();
1399 // Part of binary is determined by TableGn.
1400 unsigned Binary = getBinaryCodeForInstr(MI);
1402 // Set the conditional execution predicate
1403 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1406 assert((Binary & ARMII::D_BitShift) == 0 &&
1407 (Binary & ARMII::N_BitShift) == 0 &&
1408 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1411 Binary |= encodeVFPRd(MI, OpIdx++);
1413 // If this is a two-address operand, skip it, e.g. FMACD.
1414 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1418 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1419 Binary |= encodeVFPRn(MI, OpIdx++);
1421 if (OpIdx == TID.getNumOperands() ||
1422 TID.OpInfo[OpIdx].isPredicate() ||
1423 TID.OpInfo[OpIdx].isOptionalDef()) {
1424 // FCMPEZD etc. has only one operand.
1430 Binary |= encodeVFPRm(MI, OpIdx);
1435 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1436 const TargetInstrDesc &TID = MI.getDesc();
1437 unsigned Form = TID.TSFlags & ARMII::FormMask;
1439 // Part of binary is determined by TableGn.
1440 unsigned Binary = getBinaryCodeForInstr(MI);
1442 // Set the conditional execution predicate
1443 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1447 case ARMII::VFPConv1Frm:
1448 case ARMII::VFPConv2Frm:
1449 case ARMII::VFPConv3Frm:
1451 Binary |= encodeVFPRd(MI, 0);
1453 case ARMII::VFPConv4Frm:
1455 Binary |= encodeVFPRn(MI, 0);
1457 case ARMII::VFPConv5Frm:
1459 Binary |= encodeVFPRm(MI, 0);
1465 case ARMII::VFPConv1Frm:
1467 Binary |= encodeVFPRm(MI, 1);
1469 case ARMII::VFPConv2Frm:
1470 case ARMII::VFPConv3Frm:
1472 Binary |= encodeVFPRn(MI, 1);
1474 case ARMII::VFPConv4Frm:
1475 case ARMII::VFPConv5Frm:
1477 Binary |= encodeVFPRd(MI, 1);
1481 if (Form == ARMII::VFPConv5Frm)
1483 Binary |= encodeVFPRn(MI, 2);
1484 else if (Form == ARMII::VFPConv3Frm)
1486 Binary |= encodeVFPRm(MI, 2);
1491 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1492 // Part of binary is determined by TableGn.
1493 unsigned Binary = getBinaryCodeForInstr(MI);
1495 // Set the conditional execution predicate
1496 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1501 Binary |= encodeVFPRd(MI, OpIdx++);
1503 // Encode address base.
1504 const MachineOperand &Base = MI.getOperand(OpIdx++);
1505 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1507 // If there is a non-zero immediate offset, encode it.
1509 const MachineOperand &Offset = MI.getOperand(OpIdx);
1510 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1511 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1512 Binary |= 1 << ARMII::U_BitShift;
1519 // If immediate offset is omitted, default to +0.
1520 Binary |= 1 << ARMII::U_BitShift;
1526 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1527 const TargetInstrDesc &TID = MI.getDesc();
1528 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1530 // Part of binary is determined by TableGn.
1531 unsigned Binary = getBinaryCodeForInstr(MI);
1533 // Set the conditional execution predicate
1534 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1536 // Skip operand 0 of an instruction with base register update.
1541 // Set base address operand
1542 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1544 // Set addressing mode by modifying bits U(23) and P(24)
1545 const MachineOperand &MO = MI.getOperand(OpIdx++);
1546 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1550 Binary |= 0x1 << ARMII::W_BitShift;
1552 // First register is encoded in Dd.
1553 Binary |= encodeVFPRd(MI, OpIdx+2);
1555 // Count the number of registers.
1556 unsigned NumRegs = 1;
1557 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1558 const MachineOperand &MO = MI.getOperand(i);
1559 if (!MO.isReg() || MO.isImplicit())
1563 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1564 // Otherwise, it will be 0, in the case of 32-bit registers.
1566 Binary |= NumRegs * 2;
1573 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1574 unsigned Opcode = MI.getDesc().Opcode;
1575 // Part of binary is determined by TableGn.
1576 unsigned Binary = getBinaryCodeForInstr(MI);
1578 // Set the conditional execution predicate
1579 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1583 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1586 // No further encoding needed.
1591 const MachineOperand &MO0 = MI.getOperand(0);
1593 Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift;
1598 case ARM::FCONSTS: {
1600 Binary |= encodeVFPRd(MI, 0);
1602 // Encode imm., Table A7-18 VFP modified immediate constants
1603 const MachineOperand &MO1 = MI.getOperand(1);
1604 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1605 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1606 unsigned ModifiedImm;
1608 if(Opcode == ARM::FCONSTS)
1609 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1610 (Imm & 0x03F80000) >> 19; // bcdefgh
1611 else // Opcode == ARM::FCONSTD
1612 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1613 (Imm & 0x007F0000) >> 16; // bcdefgh
1615 // Insts{19-16} = abcd, Insts{3-0} = efgh
1616 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1617 Binary |= (ModifiedImm & 0xF);
1625 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1626 unsigned RegD = MI.getOperand(OpIdx).getReg();
1627 unsigned Binary = 0;
1628 RegD = getARMRegisterNumbering(RegD);
1629 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1630 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1634 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1635 unsigned RegN = MI.getOperand(OpIdx).getReg();
1636 unsigned Binary = 0;
1637 RegN = getARMRegisterNumbering(RegN);
1638 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1639 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1643 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1644 unsigned RegM = MI.getOperand(OpIdx).getReg();
1645 unsigned Binary = 0;
1646 RegM = getARMRegisterNumbering(RegM);
1647 Binary |= (RegM & 0xf);
1648 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1652 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1653 /// data-processing instruction to the corresponding Thumb encoding.
1654 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1655 assert((Binary & 0xfe000000) == 0xf2000000 &&
1656 "not an ARM NEON data-processing instruction");
1657 unsigned UBit = (Binary >> 24) & 1;
1658 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1661 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1662 unsigned Binary = getBinaryCodeForInstr(MI);
1664 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1665 const TargetInstrDesc &TID = MI.getDesc();
1666 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1670 } else { // ARMII::NSetLnFrm
1676 // Set the conditional execution predicate
1677 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1679 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1680 RegT = getARMRegisterNumbering(RegT);
1681 Binary |= (RegT << ARMII::RegRdShift);
1682 Binary |= encodeNEONRn(MI, RegNOpIdx);
1685 if ((Binary & (1 << 22)) != 0)
1686 LaneShift = 0; // 8-bit elements
1687 else if ((Binary & (1 << 5)) != 0)
1688 LaneShift = 1; // 16-bit elements
1690 LaneShift = 2; // 32-bit elements
1692 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1693 unsigned Opc1 = Lane >> 2;
1694 unsigned Opc2 = Lane & 3;
1695 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1696 Binary |= (Opc1 << 21);
1697 Binary |= (Opc2 << 5);
1702 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1703 unsigned Binary = getBinaryCodeForInstr(MI);
1705 // Set the conditional execution predicate
1706 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1708 unsigned RegT = MI.getOperand(1).getReg();
1709 RegT = getARMRegisterNumbering(RegT);
1710 Binary |= (RegT << ARMII::RegRdShift);
1711 Binary |= encodeNEONRn(MI, 0);
1715 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1716 unsigned Binary = getBinaryCodeForInstr(MI);
1717 // Destination register is encoded in Dd.
1718 Binary |= encodeNEONRd(MI, 0);
1719 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1720 unsigned Imm = MI.getOperand(1).getImm();
1721 unsigned Op = (Imm >> 12) & 1;
1722 unsigned Cmode = (Imm >> 8) & 0xf;
1723 unsigned I = (Imm >> 7) & 1;
1724 unsigned Imm3 = (Imm >> 4) & 0x7;
1725 unsigned Imm4 = Imm & 0xf;
1726 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1728 Binary = convertNEONDataProcToThumb(Binary);
1732 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1733 const TargetInstrDesc &TID = MI.getDesc();
1734 unsigned Binary = getBinaryCodeForInstr(MI);
1735 // Destination register is encoded in Dd; source register in Dm.
1737 Binary |= encodeNEONRd(MI, OpIdx++);
1738 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1740 Binary |= encodeNEONRm(MI, OpIdx);
1742 Binary = convertNEONDataProcToThumb(Binary);
1743 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1747 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1748 const TargetInstrDesc &TID = MI.getDesc();
1749 unsigned Binary = getBinaryCodeForInstr(MI);
1750 // Destination register is encoded in Dd; source registers in Dn and Dm.
1752 Binary |= encodeNEONRd(MI, OpIdx++);
1753 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1755 Binary |= encodeNEONRn(MI, OpIdx++);
1756 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1758 Binary |= encodeNEONRm(MI, OpIdx);
1760 Binary = convertNEONDataProcToThumb(Binary);
1761 // FIXME: This does not handle VMOVDneon or VMOVQ.
1765 #include "ARMGenCodeEmitter.inc"