1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMInstrInfo.h"
17 #include "ARMSubtarget.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMRelocations.h"
20 #include "ARMAddressingModes.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Function.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/Compiler.h"
32 STATISTIC(NumEmitted, "Number of machine instructions emitted");
35 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
36 const ARMInstrInfo *II;
39 MachineCodeEmitter &MCE;
42 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
43 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
45 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
46 const ARMInstrInfo &ii, const TargetData &td)
47 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
50 bool runOnMachineFunction(MachineFunction &MF);
52 virtual const char *getPassName() const {
53 return "ARM Machine Code Emitter";
56 void emitInstruction(const MachineInstr &MI);
57 int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
58 unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
59 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
61 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
62 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
63 void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
64 int Disp = 0, unsigned PCAdj = 0 );
65 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
67 void emitGlobalConstant(const Constant *CV);
68 void emitMachineBasicBlock(MachineBasicBlock *BB);
71 int getShiftOp(const MachineOperand &MO);
77 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
78 /// to the specified MCE object.
79 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
80 MachineCodeEmitter &MCE) {
81 return new Emitter(TM, MCE);
84 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
85 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
86 MF.getTarget().getRelocationModel() != Reloc::Static) &&
87 "JIT relocation model must be set to static or default!");
88 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
89 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
92 MCE.startFunction(MF);
93 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
95 MCE.StartMachineBasicBlock(MBB);
96 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
100 } while (MCE.finishFunction(MF));
105 /// getBaseOpcodeFor - Return the opcode value
106 unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
107 return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
110 /// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
112 int Emitter::getShiftOp(const MachineOperand &MO) {
113 unsigned ShiftOp = 0x0;
114 switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
115 default: assert(0 && "Unknown shift opc!");
133 int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
135 const MachineOperand &MO = MI.getOperand(OpIndex);
136 if (MO.isRegister()) {
137 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
138 rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
139 } else if (MO.isImmediate()) {
141 } else if (MO.isGlobalAddress()) {
142 emitGlobalAddressForCall(MO.getGlobal(), false);
143 } else if (MO.isExternalSymbol()) {
144 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
145 } else if (MO.isConstantPoolIndex()) {
146 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
147 } else if (MO.isJumpTableIndex()) {
148 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
149 } else if (MO.isMachineBasicBlock()) {
150 emitMachineBasicBlock(MO.getMBB());
156 /// emitGlobalAddressForCall - Emit the specified address to the code stream
157 /// assuming this is part of a function call, which is PC relative.
159 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
160 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
161 ARM::reloc_arm_branch, GV, 0,
165 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
166 /// be emitted to the current location in the function, and allow it to be PC
168 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
169 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
173 /// emitConstPoolAddress - Arrange for the address of an constant pool
174 /// to be emitted to the current location in the function, and allow it to be PC
176 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
178 unsigned PCAdj /* = 0 */) {
179 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
183 /// emitJumpTableAddress - Arrange for the address of a jump table to
184 /// be emitted to the current location in the function, and allow it to be PC
186 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
187 unsigned PCAdj /* = 0 */) {
188 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
192 /// emitMachineBasicBlock - Emit the specified address basic block.
193 void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
194 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
195 ARM::reloc_arm_branch, BB));
198 void Emitter::emitInstruction(const MachineInstr &MI) {
199 NumEmitted++; // Keep track of the # of mi's emitted
200 MCE.emitWordLE(getBinaryCodeForInstr(MI));
203 unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
204 const TargetInstrDesc &Desc = MI.getDesc();
205 unsigned opcode = Desc.Opcode;
206 // initial instruction mask
207 unsigned Value = 0xE0000000;
210 switch (Desc.TSFlags & ARMII::AddrModeMask) {
211 case ARMII::AddrModeNone: {
212 switch(Desc.TSFlags & ARMII::FormMask) {
214 assert(0 && "Unknown instruction subtype!");
215 // treat special instruction CLZ
216 if(opcode == ARM::CLZ) {
218 op = getMachineOpValue(MI,0);
219 Value |= op << ARMII::RegRdShift;
221 // set second operand
222 op = getMachineOpValue(MI,1);
227 case ARMII::MulSMLAW:
228 case ARMII::MulSMULW:
232 case ARMII::MulSMUL: {
236 // set opcode (bit[7:4]). For more information, see ARM-ARM page A3-31
241 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
242 Value |= BaseOpcode << 4;
244 unsigned Format = (Desc.TSFlags & ARMII::FormMask);
245 if (Format == ARMII::MulSMUL)
249 op = getMachineOpValue(MI,0);
250 Value |= op << ARMII::RegRnShift;
252 // set second operand
253 op = getMachineOpValue(MI,1);
257 op = getMachineOpValue(MI,2);
258 Value |= op << ARMII::RegRsShift;
260 // instructions SMLA and SMLAW have a fourth operand
261 if (Format != ARMII::MulSMULW && Format != ARMII::MulSMUL) {
262 op = getMachineOpValue(MI,3);
263 Value |= op << ARMII::RegRdShift;
268 case ARMII::MulFrm: {
269 // bit[7:4] is always 9
271 // set opcode (bit[23:20])
272 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
273 Value |= BaseOpcode << 20;
275 bool isMUL = opcode == ARM::MUL;
276 bool isMLA = opcode == ARM::MLA;
279 op = getMachineOpValue(MI,0);
280 Value |= op << (isMUL || isMLA ? ARMII::RegRnShift : ARMII::RegRdShift);
282 // set second operand
283 op = getMachineOpValue(MI,1);
284 Value |= op << (isMUL || isMLA ? 0 : ARMII::RegRnShift);
287 op = getMachineOpValue(MI,2);
288 Value |= op << (isMUL || isMLA ? ARMII::RegRsShift : 0);
290 // multiply instructions (except MUL), have a fourth operand
292 op = getMachineOpValue(MI,3);
293 Value |= op << (isMLA ? ARMII::RegRdShift : ARMII::RegRsShift);
298 case ARMII::Branch: {
299 // set opcode (bit[27:24])
300 unsigned BaseOpcode = getBaseOpcodeFor(Desc);
301 Value |= BaseOpcode << 24;
303 // set signed_immed_24 field
304 op = getMachineOpValue(MI,0);
307 // if it is a conditional branch, set cond field
308 if (opcode == ARM::Bcc) {
309 op = getMachineOpValue(MI,1);
310 Value &= 0x0FFFFFFF; // clear conditional field
311 Value |= op << 28; // set conditional field
316 case ARMII::BranchMisc: {
317 // set opcode (bit[7:4])
318 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
319 Value |= BaseOpcode << 4;
320 // set bit[27:24] to 1, set bit[23:20] to 2 and set bit[19:8] to 0xFFF
321 Value |= 0x12fff << 8;
323 if (opcode == ARM::BX_RET)
324 op = 0xe; // the return register is LR
326 // otherwise, set the return register
327 op = getMachineOpValue(MI,0);
338 case ARMII::AddrMode1: {
339 // set opcode (bit[24:21]) of data-processing instructions
340 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
341 Value |= BaseOpcode << 21;
343 // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
345 unsigned Format = Desc.TSFlags & ARMII::FormMask;
346 if (Format == ARMII::DPRdMisc) {
347 Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
348 Value |= getMachineOpValue(MI,1);
350 case ARM::MOVsra_flag: {
355 case ARM::MOVsrl_flag: {
368 // Data processing operand instructions has 3 possible encodings (for more
369 // information, see ARM-ARM page A3-10):
370 // 1. <instr> <Rd>,<shifter_operand>
371 // 2. <instr> <Rn>,<shifter_operand>
372 // 3. <instr> <Rd>,<Rn>,<shifter_operand>
373 bool IsDataProcessing1 = Format == ARMII::DPRdIm ||
374 Format == ARMII::DPRdReg ||
375 Format == ARMII::DPRdSoReg;
376 bool IsDataProcessing2 = Format == ARMII::DPRnIm ||
377 Format == ARMII::DPRnReg ||
378 Format == ARMII::DPRnSoReg;
379 bool IsDataProcessing3 = false;
382 if (Format == ARMII::DPRImS || Format == ARMII::DPRRegS ||
383 Format == ARMII::DPRSoRegS || IsDataProcessing2) {
384 Value |= 1 << ARMII::S_BitShift;
385 IsDataProcessing3 = !IsDataProcessing2;
388 IsDataProcessing3 = Format == ARMII::DPRIm ||
389 Format == ARMII::DPRReg ||
390 Format == ARMII::DPRSoReg ||
394 op = getMachineOpValue(MI,0);
395 if (IsDataProcessing1 || IsDataProcessing3) {
396 Value |= op << ARMII::RegRdShift;
397 } else if (IsDataProcessing2) {
398 Value |= op << ARMII::RegRnShift;
401 // set second operand of data processing #3 instructions
402 if (IsDataProcessing3) {
403 op = getMachineOpValue(MI,1);
404 Value |= op << ARMII::RegRnShift;
407 unsigned OperandIndex = IsDataProcessing3 ? 2 : 1;
409 case ARMII::DPRdIm: case ARMII::DPRnIm:
410 case ARMII::DPRIm: case ARMII::DPRImS: {
411 // set bit I(25) to identify this is the immediate form of <shifter_op>
412 Value |= 1 << ARMII::I_BitShift;
414 const MachineOperand &MO = MI.getOperand(OperandIndex);
415 op = ARM_AM::getSOImmVal(MO.getImm());
420 case ARMII::DPRdReg: case ARMII::DPRnReg:
421 case ARMII::DPRReg: case ARMII::DPRRegS: {
422 // set last operand (register Rm)
423 op = getMachineOpValue(MI,OperandIndex);
428 case ARMII::DPRdSoReg: case ARMII::DPRnSoReg:
429 case ARMII::DPRSoReg: case ARMII::DPRSoRegS: {
430 // set last operand (register Rm)
431 op = getMachineOpValue(MI,OperandIndex);
434 const MachineOperand &MO1 = MI.getOperand(OperandIndex + 1);
435 const MachineOperand &MO2 = MI.getOperand(OperandIndex + 2);
436 // identify it the instr is in immed or register shifts encoding
437 bool IsShiftByRegister = MO1.getReg() > 0;
438 // set shift operand (bit[6:4]).
439 // ASR - 101 if it is in register shifts encoding; 100, otherwise.
440 // LSL - 001 if it is in register shifts encoding; 000, otherwise.
441 // LSR - 011 if it is in register shifts encoding; 010, otherwise.
442 // ROR - 111 if it is in register shifts encoding; 110, otherwise.
443 // RRX - 110 and bit[11:7] clear.
444 switch(ARM_AM::getSORegShOp(MO2.getImm())) {
445 default: assert(0 && "Unknown shift opc!");
447 if(IsShiftByRegister)
454 if(IsShiftByRegister)
459 if(IsShiftByRegister)
466 if(IsShiftByRegister)
477 // set the field related to shift operations (except rrx).
478 if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
479 if (IsShiftByRegister) {
480 // set the value of bit[11:8] (register Rs).
481 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
482 op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
483 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
484 Value |= op << ARMII::RegRsShift;
486 // set the value of bit [11:7] (shift_immed field).
487 op = ARM_AM::getSORegOffset(MO2.getImm());
493 default: assert(false && "Unknown operand type!");
499 case ARMII::AddrMode2: {
500 // bit 26 is always 1
503 unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
504 // if the instruction uses offset addressing or pre-indexed addressing,
505 // set bit P(24) to 1
506 if (Index == ARMII::IndexModePre || Index == 0)
507 Value |= 1 << ARMII::IndexShift;
508 // if the instruction uses post-indexed addressing, set bit W(21) to 1
509 if (Index == ARMII::IndexModePre)
512 unsigned Format = Desc.TSFlags & ARMII::FormMask;
513 // If it is a load instruction (except LDRD), set bit L(20) to 1
514 if (Format == ARMII::LdFrm)
515 Value |= 1 << ARMII::L_BitShift;
518 unsigned BitByte = getBaseOpcodeFor(Desc);
519 Value |= BitByte << 22;
522 op = getMachineOpValue(MI,0);
523 Value |= op << ARMII::RegRdShift;
525 // set second operand
526 op = getMachineOpValue(MI,1);
527 Value |= op << ARMII::RegRnShift;
529 const MachineOperand &MO2 = MI.getOperand(2);
530 const MachineOperand &MO3 = MI.getOperand(3);
532 // set bit U(23) according to signal of immed value (positive or negative)
533 Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
535 if (!MO2.getReg()) { // is immediate
536 if (ARM_AM::getAM2Offset(MO3.getImm()))
537 // set the value of offset_12 field
538 Value |= ARM_AM::getAM2Offset(MO3.getImm());
542 // set bit I(25), because this is not in immediate enconding.
543 Value |= 1 << ARMII::I_BitShift;
544 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
545 // set bit[3:0] to the corresponding Rm register
546 Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
548 // if this instr is in scaled register offset/index instruction, set
549 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
550 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
551 unsigned ShiftOp = getShiftOp(MO3);
552 Value |= ShiftOp << 5; // shift
553 Value |= ShImm << 7; // shift_immed
558 case ARMII::AddrMode3: {
559 unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
560 // if the instruction uses offset addressing or pre-indexed addressing,
561 // set bit P(24) to 1
562 if (Index == ARMII::IndexModePre || Index == 0)
563 Value |= 1 << ARMII::IndexShift;
565 unsigned Format = Desc.TSFlags & ARMII::FormMask;
566 // If it is a load instruction (except LDRD), set bit L(20) to 1
567 if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
568 Value |= 1 << ARMII::L_BitShift;
570 // bit[7:4] is the opcode of this instruction class (bits S and H).
571 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
572 Value |= BaseOpcode << 4;
575 op = getMachineOpValue(MI,0);
576 Value |= op << ARMII::RegRdShift;
578 // set second operand
579 op = getMachineOpValue(MI,1);
580 Value |= op << ARMII::RegRnShift;
582 const MachineOperand &MO2 = MI.getOperand(2);
583 const MachineOperand &MO3 = MI.getOperand(3);
585 // set bit U(23) according to signal of immed value (positive or negative)
586 Value |= (ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
589 // if this instr is in register offset/index encoding, set bit[3:0]
590 // to the corresponding Rm register.
592 Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
596 // if this instr is in immediate offset/index encoding, set bit 22 to 1
597 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
600 Value |= (ImmOffs >> 4) << 8; // immedH
601 Value |= (ImmOffs & ~0xF); // immedL
606 case ARMII::AddrMode4: {
607 // bit 27 is always 1
610 unsigned Format = Desc.TSFlags & ARMII::FormMask;
611 // if it is a load instr, set bit L(20) to 1
612 if (Format == ARMII::LdFrm)
613 Value |= 1 << ARMII::L_BitShift;
615 unsigned OpIndex = 0;
618 op = getMachineOpValue(MI,OpIndex);
619 Value |= op << ARMII::RegRnShift;
621 // set addressing mode by modifying bits U(23) and P(24)
622 // IA - Increment after - bit U = 1 and bit P = 0
623 // IB - Increment before - bit U = 1 and bit P = 1
624 // DA - Decrement after - bit U = 0 and bit P = 0
625 // DB - Decrement before - bit U = 0 and bit P = 1
626 const MachineOperand &MO = MI.getOperand(OpIndex + 1);
627 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
629 default: assert(0 && "Unknown addressing sub-mode!");
630 case ARM_AM::ia: Value |= 0x1 << 23; break;
631 case ARM_AM::ib: Value |= 0x3 << 23; break;
632 case ARM_AM::da: break;
633 case ARM_AM::db: Value |= 0x1 << 24; break;
637 if (ARM_AM::getAM4WBFlag(MO.getImm()))
641 for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) {
642 const MachineOperand &MOR = MI.getOperand(i);
643 unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg());
644 assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) &&
646 Value |= 0x1 << RegNumber;