1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitNEONLaneInstruction(const MachineInstr &MI);
144 void emitNEONDupInstruction(const MachineInstr &MI);
145 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146 void emitNEON2RegInstruction(const MachineInstr &MI);
147 void emitNEON3RegInstruction(const MachineInstr &MI);
149 /// getMachineOpValue - Return binary encoding of operand. If the machine
150 /// operand requires relocation, record the relocation and return zero.
151 unsigned getMachineOpValue(const MachineInstr &MI,
152 const MachineOperand &MO) const;
153 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
154 return getMachineOpValue(MI, MI.getOperand(OpIdx));
157 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
158 // TableGen'erated getBinaryCodeForInstr() function to encode any
159 // operand values, instead querying getMachineOpValue() directly for
160 // each operand it needs to encode. Thus, any of the new encoder
161 // helper functions can simply return 0 as the values the return
162 // are already handled elsewhere. They are placeholders to allow this
163 // encoder to continue to function until the MC encoder is sufficiently
164 // far along that this one can be eliminated entirely.
165 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
167 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
169 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
171 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
173 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
175 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
176 unsigned Op) const { return 0; }
177 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
180 // {12} = (U)nsigned (add == '1', sub == '0')
182 const MachineOperand &MO = MI.getOperand(Op);
183 const MachineOperand &MO1 = MI.getOperand(Op + 1);
185 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
188 unsigned Reg = getARMRegisterNumbering(MO.getReg());
189 int32_t Imm12 = MO1.getImm();
191 Binary = Imm12 & 0xfff;
194 Binary |= (Reg << 13);
197 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
200 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
201 /// machine operand requires relocation, record the relocation and return
203 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
206 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
208 unsigned getShiftOp(unsigned Imm) const ;
210 /// Routines that handle operands which add machine relocations which are
211 /// fixed up by the relocation stage.
212 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
213 bool MayNeedFarStub, bool Indirect,
214 intptr_t ACPV = 0) const;
215 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
216 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
217 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
218 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
219 intptr_t JTBase = 0) const;
223 char ARMCodeEmitter::ID = 0;
225 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
226 /// code to the specified MCE object.
227 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
228 JITCodeEmitter &JCE) {
229 return new ARMCodeEmitter(TM, JCE);
232 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
233 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
234 MF.getTarget().getRelocationModel() != Reloc::Static) &&
235 "JIT relocation model must be set to static or default!");
236 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
237 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
238 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
239 Subtarget = &TM.getSubtarget<ARMSubtarget>();
240 MCPEs = &MF.getConstantPool()->getConstants();
242 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
243 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
244 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
245 JTI->Initialize(MF, IsPIC);
246 MMI = &getAnalysis<MachineModuleInfo>();
247 MCE.setModuleInfo(MMI);
250 DEBUG(errs() << "JITTing function '"
251 << MF.getFunction()->getName() << "'\n");
252 MCE.startFunction(MF);
253 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
255 MCE.StartMachineBasicBlock(MBB);
256 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
260 } while (MCE.finishFunction(MF));
265 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
267 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
268 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
269 default: llvm_unreachable("Unknown shift opc!");
270 case ARM_AM::asr: return 2;
271 case ARM_AM::lsl: return 0;
272 case ARM_AM::lsr: return 1;
274 case ARM_AM::rrx: return 3;
279 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
280 /// machine operand requires relocation, record the relocation and return zero.
281 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
282 const MachineOperand &MO,
284 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
285 && "Relocation to this function should be for movt or movw");
288 return static_cast<unsigned>(MO.getImm());
289 else if (MO.isGlobal())
290 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
291 else if (MO.isSymbol())
292 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
294 emitMachineBasicBlock(MO.getMBB(), Reloc);
299 llvm_unreachable("Unsupported operand type for movw/movt");
304 /// getMachineOpValue - Return binary encoding of operand. If the machine
305 /// operand requires relocation, record the relocation and return zero.
306 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
307 const MachineOperand &MO) const {
309 return getARMRegisterNumbering(MO.getReg());
311 return static_cast<unsigned>(MO.getImm());
312 else if (MO.isGlobal())
313 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
314 else if (MO.isSymbol())
315 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
316 else if (MO.isCPI()) {
317 const TargetInstrDesc &TID = MI.getDesc();
318 // For VFP load, the immediate offset is multiplied by 4.
319 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
320 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
321 emitConstPoolAddress(MO.getIndex(), Reloc);
322 } else if (MO.isJTI())
323 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
325 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
335 /// emitGlobalAddress - Emit the specified address to the code stream.
337 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
338 bool MayNeedFarStub, bool Indirect,
339 intptr_t ACPV) const {
340 MachineRelocation MR = Indirect
341 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
342 const_cast<GlobalValue *>(GV),
343 ACPV, MayNeedFarStub)
344 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
345 const_cast<GlobalValue *>(GV), ACPV,
347 MCE.addRelocation(MR);
350 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
351 /// be emitted to the current location in the function, and allow it to be PC
353 void ARMCodeEmitter::
354 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
355 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
359 /// emitConstPoolAddress - Arrange for the address of an constant pool
360 /// to be emitted to the current location in the function, and allow it to be PC
362 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
363 // Tell JIT emitter we'll resolve the address.
364 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
365 Reloc, CPI, 0, true));
368 /// emitJumpTableAddress - Arrange for the address of a jump table to
369 /// be emitted to the current location in the function, and allow it to be PC
371 void ARMCodeEmitter::
372 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
373 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
374 Reloc, JTIndex, 0, true));
377 /// emitMachineBasicBlock - Emit the specified address basic block.
378 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
380 intptr_t JTBase) const {
381 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
385 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
386 DEBUG(errs() << " 0x";
387 errs().write_hex(Binary) << "\n");
388 MCE.emitWordLE(Binary);
391 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
392 DEBUG(errs() << " 0x";
393 errs().write_hex(Binary) << "\n");
394 MCE.emitDWordLE(Binary);
397 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
398 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
400 MCE.processDebugLoc(MI.getDebugLoc(), true);
402 ++NumEmitted; // Keep track of the # of mi's emitted
403 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
405 llvm_unreachable("Unhandled instruction encoding format!");
409 emitPseudoInstruction(MI);
412 case ARMII::DPSoRegFrm:
413 emitDataProcessingInstruction(MI);
417 emitLoadStoreInstruction(MI);
419 case ARMII::LdMiscFrm:
420 case ARMII::StMiscFrm:
421 emitMiscLoadStoreInstruction(MI);
423 case ARMII::LdStMulFrm:
424 emitLoadStoreMultipleInstruction(MI);
427 emitMulFrmInstruction(MI);
430 emitExtendInstruction(MI);
432 case ARMII::ArithMiscFrm:
433 emitMiscArithInstruction(MI);
436 emitSaturateInstruction(MI);
439 emitBranchInstruction(MI);
441 case ARMII::BrMiscFrm:
442 emitMiscBranchInstruction(MI);
445 case ARMII::VFPUnaryFrm:
446 case ARMII::VFPBinaryFrm:
447 emitVFPArithInstruction(MI);
449 case ARMII::VFPConv1Frm:
450 case ARMII::VFPConv2Frm:
451 case ARMII::VFPConv3Frm:
452 case ARMII::VFPConv4Frm:
453 case ARMII::VFPConv5Frm:
454 emitVFPConversionInstruction(MI);
456 case ARMII::VFPLdStFrm:
457 emitVFPLoadStoreInstruction(MI);
459 case ARMII::VFPLdStMulFrm:
460 emitVFPLoadStoreMultipleInstruction(MI);
463 // NEON instructions.
464 case ARMII::NGetLnFrm:
465 case ARMII::NSetLnFrm:
466 emitNEONLaneInstruction(MI);
469 emitNEONDupInstruction(MI);
471 case ARMII::N1RegModImmFrm:
472 emitNEON1RegModImmInstruction(MI);
474 case ARMII::N2RegFrm:
475 emitNEON2RegInstruction(MI);
477 case ARMII::N3RegFrm:
478 emitNEON3RegInstruction(MI);
481 MCE.processDebugLoc(MI.getDebugLoc(), false);
484 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
485 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
486 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
487 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
489 // Remember the CONSTPOOL_ENTRY address for later relocation.
490 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
492 // Emit constpool island entry. In most cases, the actual values will be
493 // resolved and relocated after code emission.
494 if (MCPE.isMachineConstantPoolEntry()) {
495 ARMConstantPoolValue *ACPV =
496 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
498 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
499 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
501 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
502 const GlobalValue *GV = ACPV->getGV();
504 Reloc::Model RelocM = TM.getRelocationModel();
505 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
507 Subtarget->GVIsIndirectSymbol(GV, RelocM),
510 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
514 const Constant *CV = MCPE.Val.ConstVal;
517 errs() << " ** Constant pool #" << CPI << " @ "
518 << (void*)MCE.getCurrentPCValue() << " ";
519 if (const Function *F = dyn_cast<Function>(CV))
520 errs() << F->getName();
526 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
527 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
529 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
530 uint32_t Val = uint32_t(*CI->getValue().getRawData());
532 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
533 if (CFP->getType()->isFloatTy())
534 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
535 else if (CFP->getType()->isDoubleTy())
536 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
538 llvm_unreachable("Unable to handle this constantpool entry!");
541 llvm_unreachable("Unable to handle this constantpool entry!");
546 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
547 const MachineOperand &MO0 = MI.getOperand(0);
548 const MachineOperand &MO1 = MI.getOperand(1);
550 // Emit the 'movw' instruction.
551 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
553 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
555 // Set the conditional execution predicate.
556 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
559 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
561 // Encode imm16 as imm4:imm12
562 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
563 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
566 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
567 // Emit the 'movt' instruction.
568 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
570 // Set the conditional execution predicate.
571 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
574 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
576 // Encode imm16 as imm4:imm1, same as movw above.
577 Binary |= Hi16 & 0xFFF;
578 Binary |= ((Hi16 >> 12) & 0xF) << 16;
582 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
583 const MachineOperand &MO0 = MI.getOperand(0);
584 const MachineOperand &MO1 = MI.getOperand(1);
585 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
586 "Not a valid so_imm value!");
587 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
588 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
590 // Emit the 'mov' instruction.
591 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
593 // Set the conditional execution predicate.
594 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
597 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
600 // Set bit I(25) to identify this is the immediate form of <shifter_op>
601 Binary |= 1 << ARMII::I_BitShift;
602 Binary |= getMachineSoImmOpValue(V1);
605 // Now the 'orr' instruction.
606 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
608 // Set the conditional execution predicate.
609 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
612 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
615 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
618 // Set bit I(25) to identify this is the immediate form of <shifter_op>
619 Binary |= 1 << ARMII::I_BitShift;
620 Binary |= getMachineSoImmOpValue(V2);
624 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
625 // It's basically add r, pc, (LJTI - $+8)
627 const TargetInstrDesc &TID = MI.getDesc();
629 // Emit the 'add' instruction.
630 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
632 // Set the conditional execution predicate
633 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
635 // Encode S bit if MI modifies CPSR.
636 Binary |= getAddrModeSBit(MI, TID);
639 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
641 // Encode Rn which is PC.
642 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
644 // Encode the displacement.
645 Binary |= 1 << ARMII::I_BitShift;
646 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
651 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
652 unsigned Opcode = MI.getDesc().Opcode;
654 // Part of binary is determined by TableGn.
655 unsigned Binary = getBinaryCodeForInstr(MI);
657 // Set the conditional execution predicate
658 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
660 // Encode S bit if MI modifies CPSR.
661 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
662 Binary |= 1 << ARMII::S_BitShift;
664 // Encode register def if there is one.
665 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
667 // Encode the shift operation.
674 case ARM::MOVsrl_flag:
676 Binary |= (0x2 << 4) | (1 << 7);
678 case ARM::MOVsra_flag:
680 Binary |= (0x4 << 4) | (1 << 7);
684 // Encode register Rm.
685 Binary |= getMachineOpValue(MI, 1);
690 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
691 DEBUG(errs() << " ** LPC" << LabelID << " @ "
692 << (void*)MCE.getCurrentPCValue() << '\n');
693 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
696 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
697 unsigned Opcode = MI.getDesc().Opcode;
700 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
704 case ARM::BMOVPCRXr9: {
705 // First emit mov lr, pc
706 unsigned Binary = 0x01a0e00f;
707 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
710 // and then emit the branch.
711 emitMiscBranchInstruction(MI);
714 case TargetOpcode::INLINEASM: {
715 // We allow inline assembler nodes with empty bodies - they can
716 // implicitly define registers, which is ok for JIT.
717 if (MI.getOperand(0).getSymbolName()[0]) {
718 report_fatal_error("JIT does not support inline asm!");
722 case TargetOpcode::PROLOG_LABEL:
723 case TargetOpcode::EH_LABEL:
724 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
726 case TargetOpcode::IMPLICIT_DEF:
727 case TargetOpcode::KILL:
730 case ARM::CONSTPOOL_ENTRY:
731 emitConstPoolInstruction(MI);
734 // Remember of the address of the PC label for relocation later.
735 addPCLabel(MI.getOperand(2).getImm());
736 // PICADD is just an add instruction that implicitly read pc.
737 emitDataProcessingInstruction(MI, 0, ARM::PC);
744 // Remember of the address of the PC label for relocation later.
745 addPCLabel(MI.getOperand(2).getImm());
746 // These are just load / store instructions that implicitly read pc.
747 emitLoadStoreInstruction(MI, 0, ARM::PC);
754 // Remember of the address of the PC label for relocation later.
755 addPCLabel(MI.getOperand(2).getImm());
756 // These are just load / store instructions that implicitly read pc.
757 emitMiscLoadStoreInstruction(MI, ARM::PC);
762 emitMOVi32immInstruction(MI);
765 case ARM::MOVi2pieces:
766 // Two instructions to materialize a constant.
767 emitMOVi2piecesInstruction(MI);
769 case ARM::LEApcrelJT:
770 // Materialize jumptable address.
771 emitLEApcrelJTInstruction(MI);
774 case ARM::MOVsrl_flag:
775 case ARM::MOVsra_flag:
776 emitPseudoMoveInstruction(MI);
781 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
782 const TargetInstrDesc &TID,
783 const MachineOperand &MO,
785 unsigned Binary = getMachineOpValue(MI, MO);
787 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
788 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
789 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
791 // Encode the shift opcode.
793 unsigned Rs = MO1.getReg();
795 // Set shift operand (bit[7:4]).
800 // RRX - 0110 and bit[11:8] clear.
802 default: llvm_unreachable("Unknown shift opc!");
803 case ARM_AM::lsl: SBits = 0x1; break;
804 case ARM_AM::lsr: SBits = 0x3; break;
805 case ARM_AM::asr: SBits = 0x5; break;
806 case ARM_AM::ror: SBits = 0x7; break;
807 case ARM_AM::rrx: SBits = 0x6; break;
810 // Set shift operand (bit[6:4]).
816 default: llvm_unreachable("Unknown shift opc!");
817 case ARM_AM::lsl: SBits = 0x0; break;
818 case ARM_AM::lsr: SBits = 0x2; break;
819 case ARM_AM::asr: SBits = 0x4; break;
820 case ARM_AM::ror: SBits = 0x6; break;
823 Binary |= SBits << 4;
824 if (SOpc == ARM_AM::rrx)
827 // Encode the shift operation Rs or shift_imm (except rrx).
829 // Encode Rs bit[11:8].
830 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
831 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
834 // Encode shift_imm bit[11:7].
835 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
838 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
839 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
840 assert(SoImmVal != -1 && "Not a valid so_imm value!");
842 // Encode rotate_imm.
843 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
844 << ARMII::SoRotImmShift;
847 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
851 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
852 const TargetInstrDesc &TID) const {
853 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
854 const MachineOperand &MO = MI.getOperand(i-1);
855 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
856 return 1 << ARMII::S_BitShift;
861 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
863 unsigned ImplicitRn) {
864 const TargetInstrDesc &TID = MI.getDesc();
866 // Part of binary is determined by TableGn.
867 unsigned Binary = getBinaryCodeForInstr(MI);
869 // Set the conditional execution predicate
870 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
872 // Encode S bit if MI modifies CPSR.
873 Binary |= getAddrModeSBit(MI, TID);
875 // Encode register def if there is one.
876 unsigned NumDefs = TID.getNumDefs();
879 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
881 // Special handling for implicit use (e.g. PC).
882 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
884 if (TID.Opcode == ARM::MOVi16) {
885 // Get immediate from MI.
886 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
887 ARM::reloc_arm_movw);
888 // Encode imm which is the same as in emitMOVi32immInstruction().
889 Binary |= Lo16 & 0xFFF;
890 Binary |= ((Lo16 >> 12) & 0xF) << 16;
893 } else if(TID.Opcode == ARM::MOVTi16) {
894 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
895 ARM::reloc_arm_movt) >> 16);
896 Binary |= Hi16 & 0xFFF;
897 Binary |= ((Hi16 >> 12) & 0xF) << 16;
900 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
901 uint32_t v = ~MI.getOperand(2).getImm();
902 int32_t lsb = CountTrailingZeros_32(v);
903 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
904 // Instr{20-16} = msb, Instr{11-7} = lsb
905 Binary |= (msb & 0x1F) << 16;
906 Binary |= (lsb & 0x1F) << 7;
909 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
910 // Encode Rn in Instr{0-3}
911 Binary |= getMachineOpValue(MI, OpIdx++);
913 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
914 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
916 // Instr{20-16} = widthm1, Instr{11-7} = lsb
917 Binary |= (widthm1 & 0x1F) << 16;
918 Binary |= (lsb & 0x1F) << 7;
923 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
924 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
927 // Encode first non-shifter register operand if there is one.
928 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
931 // Special handling for implicit use (e.g. PC).
932 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
934 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
939 // Encode shifter operand.
940 const MachineOperand &MO = MI.getOperand(OpIdx);
941 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
943 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
948 // Encode register Rm.
949 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
954 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
959 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
961 unsigned ImplicitRn) {
962 const TargetInstrDesc &TID = MI.getDesc();
963 unsigned Form = TID.TSFlags & ARMII::FormMask;
964 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
966 // Part of binary is determined by TableGn.
967 unsigned Binary = getBinaryCodeForInstr(MI);
969 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
970 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
971 MI.getOpcode() == ARM::STRi12) {
976 // Set the conditional execution predicate
977 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
981 // Operand 0 of a pre- and post-indexed store is the address base
982 // writeback. Skip it.
983 bool Skipped = false;
984 if (IsPrePost && Form == ARMII::StFrm) {
991 // Special handling for implicit use (e.g. PC).
992 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
994 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
996 // Set second operand
998 // Special handling for implicit use (e.g. PC).
999 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1001 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1003 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1004 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1007 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1008 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1009 ? 0 : MI.getOperand(OpIdx+1).getImm();
1011 // Set bit U(23) according to sign of immed value (positive or negative).
1012 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1014 if (!MO2.getReg()) { // is immediate
1015 if (ARM_AM::getAM2Offset(AM2Opc))
1016 // Set the value of offset_12 field
1017 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1022 // Set bit I(25), because this is not in immediate encoding.
1023 Binary |= 1 << ARMII::I_BitShift;
1024 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1025 // Set bit[3:0] to the corresponding Rm register
1026 Binary |= getARMRegisterNumbering(MO2.getReg());
1028 // If this instr is in scaled register offset/index instruction, set
1029 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1030 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1031 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1032 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1038 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1039 unsigned ImplicitRn) {
1040 const TargetInstrDesc &TID = MI.getDesc();
1041 unsigned Form = TID.TSFlags & ARMII::FormMask;
1042 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1044 // Part of binary is determined by TableGn.
1045 unsigned Binary = getBinaryCodeForInstr(MI);
1047 // Set the conditional execution predicate
1048 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1052 // Operand 0 of a pre- and post-indexed store is the address base
1053 // writeback. Skip it.
1054 bool Skipped = false;
1055 if (IsPrePost && Form == ARMII::StMiscFrm) {
1060 // Set first operand
1061 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1063 // Skip LDRD and STRD's second operand.
1064 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1067 // Set second operand
1069 // Special handling for implicit use (e.g. PC).
1070 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1072 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1074 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1075 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1078 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1079 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1080 ? 0 : MI.getOperand(OpIdx+1).getImm();
1082 // Set bit U(23) according to sign of immed value (positive or negative)
1083 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1086 // If this instr is in register offset/index encoding, set bit[3:0]
1087 // to the corresponding Rm register.
1089 Binary |= getARMRegisterNumbering(MO2.getReg());
1094 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1095 Binary |= 1 << ARMII::AM3_I_BitShift;
1096 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1098 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1099 Binary |= (ImmOffs & 0xF); // immedL
1105 static unsigned getAddrModeUPBits(unsigned Mode) {
1106 unsigned Binary = 0;
1108 // Set addressing mode by modifying bits U(23) and P(24)
1109 // IA - Increment after - bit U = 1 and bit P = 0
1110 // IB - Increment before - bit U = 1 and bit P = 1
1111 // DA - Decrement after - bit U = 0 and bit P = 0
1112 // DB - Decrement before - bit U = 0 and bit P = 1
1114 default: llvm_unreachable("Unknown addressing sub-mode!");
1115 case ARM_AM::da: break;
1116 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1117 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1118 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1124 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1125 const TargetInstrDesc &TID = MI.getDesc();
1126 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1128 // Part of binary is determined by TableGn.
1129 unsigned Binary = getBinaryCodeForInstr(MI);
1131 // Set the conditional execution predicate
1132 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1134 // Skip operand 0 of an instruction with base register update.
1139 // Set base address operand
1140 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1142 // Set addressing mode by modifying bits U(23) and P(24)
1143 const MachineOperand &MO = MI.getOperand(OpIdx++);
1144 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1148 Binary |= 0x1 << ARMII::W_BitShift;
1151 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1152 const MachineOperand &MO = MI.getOperand(i);
1153 if (!MO.isReg() || MO.isImplicit())
1155 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1156 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1158 Binary |= 0x1 << RegNum;
1164 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1165 const TargetInstrDesc &TID = MI.getDesc();
1167 // Part of binary is determined by TableGn.
1168 unsigned Binary = getBinaryCodeForInstr(MI);
1170 // Set the conditional execution predicate
1171 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1173 // Encode S bit if MI modifies CPSR.
1174 Binary |= getAddrModeSBit(MI, TID);
1176 // 32x32->64bit operations have two destination registers. The number
1177 // of register definitions will tell us if that's what we're dealing with.
1179 if (TID.getNumDefs() == 2)
1180 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1183 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1186 Binary |= getMachineOpValue(MI, OpIdx++);
1189 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1191 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1192 // it as Rn (for multiply, that's in the same offset as RdLo.
1193 if (TID.getNumOperands() > OpIdx &&
1194 !TID.OpInfo[OpIdx].isPredicate() &&
1195 !TID.OpInfo[OpIdx].isOptionalDef())
1196 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1201 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1202 const TargetInstrDesc &TID = MI.getDesc();
1204 // Part of binary is determined by TableGn.
1205 unsigned Binary = getBinaryCodeForInstr(MI);
1207 // Set the conditional execution predicate
1208 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1213 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1215 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1216 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1218 // Two register operand form.
1220 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1223 Binary |= getMachineOpValue(MI, MO2);
1226 Binary |= getMachineOpValue(MI, MO1);
1229 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1230 if (MI.getOperand(OpIdx).isImm() &&
1231 !TID.OpInfo[OpIdx].isPredicate() &&
1232 !TID.OpInfo[OpIdx].isOptionalDef())
1233 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1238 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1239 const TargetInstrDesc &TID = MI.getDesc();
1241 // Part of binary is determined by TableGn.
1242 unsigned Binary = getBinaryCodeForInstr(MI);
1244 // Set the conditional execution predicate
1245 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1250 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1252 const MachineOperand &MO = MI.getOperand(OpIdx++);
1253 if (OpIdx == TID.getNumOperands() ||
1254 TID.OpInfo[OpIdx].isPredicate() ||
1255 TID.OpInfo[OpIdx].isOptionalDef()) {
1256 // Encode Rm and it's done.
1257 Binary |= getMachineOpValue(MI, MO);
1263 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1266 Binary |= getMachineOpValue(MI, OpIdx++);
1268 // Encode shift_imm.
1269 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1270 if (TID.Opcode == ARM::PKHTB) {
1271 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1275 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1276 Binary |= ShiftAmt << ARMII::ShiftShift;
1281 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1282 const TargetInstrDesc &TID = MI.getDesc();
1284 // Part of binary is determined by TableGen.
1285 unsigned Binary = getBinaryCodeForInstr(MI);
1287 // Set the conditional execution predicate
1288 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1291 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1293 // Encode saturate bit position.
1294 unsigned Pos = MI.getOperand(1).getImm();
1295 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1297 assert((Pos < 16 || (Pos < 32 &&
1298 TID.Opcode != ARM::SSAT16 &&
1299 TID.Opcode != ARM::USAT16)) &&
1300 "saturate bit position out of range");
1301 Binary |= Pos << 16;
1304 Binary |= getMachineOpValue(MI, 2);
1306 // Encode shift_imm.
1307 if (TID.getNumOperands() == 4) {
1308 unsigned ShiftOp = MI.getOperand(3).getImm();
1309 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1310 if (Opc == ARM_AM::asr)
1312 unsigned ShiftAmt = MI.getOperand(3).getImm();
1313 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1315 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1316 Binary |= ShiftAmt << ARMII::ShiftShift;
1322 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1323 const TargetInstrDesc &TID = MI.getDesc();
1325 if (TID.Opcode == ARM::TPsoft) {
1326 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1329 // Part of binary is determined by TableGn.
1330 unsigned Binary = getBinaryCodeForInstr(MI);
1332 // Set the conditional execution predicate
1333 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1335 // Set signed_immed_24 field
1336 Binary |= getMachineOpValue(MI, 0);
1341 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1342 // Remember the base address of the inline jump table.
1343 uintptr_t JTBase = MCE.getCurrentPCValue();
1344 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1345 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1348 // Now emit the jump table entries.
1349 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1350 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1352 // DestBB address - JT base.
1353 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1355 // Absolute DestBB address.
1356 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1361 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1362 const TargetInstrDesc &TID = MI.getDesc();
1364 // Handle jump tables.
1365 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1366 // First emit a ldr pc, [] instruction.
1367 emitDataProcessingInstruction(MI, ARM::PC);
1369 // Then emit the inline jump table.
1371 (TID.Opcode == ARM::BR_JTr)
1372 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1373 emitInlineJumpTable(JTIndex);
1375 } else if (TID.Opcode == ARM::BR_JTm) {
1376 // First emit a ldr pc, [] instruction.
1377 emitLoadStoreInstruction(MI, ARM::PC);
1379 // Then emit the inline jump table.
1380 emitInlineJumpTable(MI.getOperand(3).getIndex());
1384 // Part of binary is determined by TableGn.
1385 unsigned Binary = getBinaryCodeForInstr(MI);
1387 // Set the conditional execution predicate
1388 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1390 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1391 // The return register is LR.
1392 Binary |= getARMRegisterNumbering(ARM::LR);
1394 // otherwise, set the return register
1395 Binary |= getMachineOpValue(MI, 0);
1400 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1401 unsigned RegD = MI.getOperand(OpIdx).getReg();
1402 unsigned Binary = 0;
1403 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1404 RegD = getARMRegisterNumbering(RegD);
1406 Binary |= RegD << ARMII::RegRdShift;
1408 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1409 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1414 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1415 unsigned RegN = MI.getOperand(OpIdx).getReg();
1416 unsigned Binary = 0;
1417 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1418 RegN = getARMRegisterNumbering(RegN);
1420 Binary |= RegN << ARMII::RegRnShift;
1422 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1423 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1428 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1429 unsigned RegM = MI.getOperand(OpIdx).getReg();
1430 unsigned Binary = 0;
1431 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1432 RegM = getARMRegisterNumbering(RegM);
1436 Binary |= ((RegM & 0x1E) >> 1);
1437 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1442 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1443 const TargetInstrDesc &TID = MI.getDesc();
1445 // Part of binary is determined by TableGn.
1446 unsigned Binary = getBinaryCodeForInstr(MI);
1448 // Set the conditional execution predicate
1449 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1452 assert((Binary & ARMII::D_BitShift) == 0 &&
1453 (Binary & ARMII::N_BitShift) == 0 &&
1454 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1457 Binary |= encodeVFPRd(MI, OpIdx++);
1459 // If this is a two-address operand, skip it, e.g. FMACD.
1460 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1464 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1465 Binary |= encodeVFPRn(MI, OpIdx++);
1467 if (OpIdx == TID.getNumOperands() ||
1468 TID.OpInfo[OpIdx].isPredicate() ||
1469 TID.OpInfo[OpIdx].isOptionalDef()) {
1470 // FCMPEZD etc. has only one operand.
1476 Binary |= encodeVFPRm(MI, OpIdx);
1481 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1482 const TargetInstrDesc &TID = MI.getDesc();
1483 unsigned Form = TID.TSFlags & ARMII::FormMask;
1485 // Part of binary is determined by TableGn.
1486 unsigned Binary = getBinaryCodeForInstr(MI);
1488 // Set the conditional execution predicate
1489 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1493 case ARMII::VFPConv1Frm:
1494 case ARMII::VFPConv2Frm:
1495 case ARMII::VFPConv3Frm:
1497 Binary |= encodeVFPRd(MI, 0);
1499 case ARMII::VFPConv4Frm:
1501 Binary |= encodeVFPRn(MI, 0);
1503 case ARMII::VFPConv5Frm:
1505 Binary |= encodeVFPRm(MI, 0);
1511 case ARMII::VFPConv1Frm:
1513 Binary |= encodeVFPRm(MI, 1);
1515 case ARMII::VFPConv2Frm:
1516 case ARMII::VFPConv3Frm:
1518 Binary |= encodeVFPRn(MI, 1);
1520 case ARMII::VFPConv4Frm:
1521 case ARMII::VFPConv5Frm:
1523 Binary |= encodeVFPRd(MI, 1);
1527 if (Form == ARMII::VFPConv5Frm)
1529 Binary |= encodeVFPRn(MI, 2);
1530 else if (Form == ARMII::VFPConv3Frm)
1532 Binary |= encodeVFPRm(MI, 2);
1537 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1538 // Part of binary is determined by TableGn.
1539 unsigned Binary = getBinaryCodeForInstr(MI);
1541 // Set the conditional execution predicate
1542 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1547 Binary |= encodeVFPRd(MI, OpIdx++);
1549 // Encode address base.
1550 const MachineOperand &Base = MI.getOperand(OpIdx++);
1551 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1553 // If there is a non-zero immediate offset, encode it.
1555 const MachineOperand &Offset = MI.getOperand(OpIdx);
1556 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1557 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1558 Binary |= 1 << ARMII::U_BitShift;
1565 // If immediate offset is omitted, default to +0.
1566 Binary |= 1 << ARMII::U_BitShift;
1572 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1573 const TargetInstrDesc &TID = MI.getDesc();
1574 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1576 // Part of binary is determined by TableGn.
1577 unsigned Binary = getBinaryCodeForInstr(MI);
1579 // Set the conditional execution predicate
1580 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1582 // Skip operand 0 of an instruction with base register update.
1587 // Set base address operand
1588 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1590 // Set addressing mode by modifying bits U(23) and P(24)
1591 const MachineOperand &MO = MI.getOperand(OpIdx++);
1592 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1596 Binary |= 0x1 << ARMII::W_BitShift;
1598 // First register is encoded in Dd.
1599 Binary |= encodeVFPRd(MI, OpIdx+2);
1601 // Count the number of registers.
1602 unsigned NumRegs = 1;
1603 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1604 const MachineOperand &MO = MI.getOperand(i);
1605 if (!MO.isReg() || MO.isImplicit())
1609 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1610 // Otherwise, it will be 0, in the case of 32-bit registers.
1612 Binary |= NumRegs * 2;
1619 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1620 unsigned RegD = MI.getOperand(OpIdx).getReg();
1621 unsigned Binary = 0;
1622 RegD = getARMRegisterNumbering(RegD);
1623 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1624 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1628 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1629 unsigned RegN = MI.getOperand(OpIdx).getReg();
1630 unsigned Binary = 0;
1631 RegN = getARMRegisterNumbering(RegN);
1632 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1633 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1637 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1638 unsigned RegM = MI.getOperand(OpIdx).getReg();
1639 unsigned Binary = 0;
1640 RegM = getARMRegisterNumbering(RegM);
1641 Binary |= (RegM & 0xf);
1642 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1646 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1647 /// data-processing instruction to the corresponding Thumb encoding.
1648 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1649 assert((Binary & 0xfe000000) == 0xf2000000 &&
1650 "not an ARM NEON data-processing instruction");
1651 unsigned UBit = (Binary >> 24) & 1;
1652 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1655 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1656 unsigned Binary = getBinaryCodeForInstr(MI);
1658 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1659 const TargetInstrDesc &TID = MI.getDesc();
1660 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1664 } else { // ARMII::NSetLnFrm
1670 // Set the conditional execution predicate
1671 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1673 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1674 RegT = getARMRegisterNumbering(RegT);
1675 Binary |= (RegT << ARMII::RegRdShift);
1676 Binary |= encodeNEONRn(MI, RegNOpIdx);
1679 if ((Binary & (1 << 22)) != 0)
1680 LaneShift = 0; // 8-bit elements
1681 else if ((Binary & (1 << 5)) != 0)
1682 LaneShift = 1; // 16-bit elements
1684 LaneShift = 2; // 32-bit elements
1686 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1687 unsigned Opc1 = Lane >> 2;
1688 unsigned Opc2 = Lane & 3;
1689 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1690 Binary |= (Opc1 << 21);
1691 Binary |= (Opc2 << 5);
1696 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1697 unsigned Binary = getBinaryCodeForInstr(MI);
1699 // Set the conditional execution predicate
1700 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1702 unsigned RegT = MI.getOperand(1).getReg();
1703 RegT = getARMRegisterNumbering(RegT);
1704 Binary |= (RegT << ARMII::RegRdShift);
1705 Binary |= encodeNEONRn(MI, 0);
1709 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1710 unsigned Binary = getBinaryCodeForInstr(MI);
1711 // Destination register is encoded in Dd.
1712 Binary |= encodeNEONRd(MI, 0);
1713 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1714 unsigned Imm = MI.getOperand(1).getImm();
1715 unsigned Op = (Imm >> 12) & 1;
1716 unsigned Cmode = (Imm >> 8) & 0xf;
1717 unsigned I = (Imm >> 7) & 1;
1718 unsigned Imm3 = (Imm >> 4) & 0x7;
1719 unsigned Imm4 = Imm & 0xf;
1720 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1722 Binary = convertNEONDataProcToThumb(Binary);
1726 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1727 const TargetInstrDesc &TID = MI.getDesc();
1728 unsigned Binary = getBinaryCodeForInstr(MI);
1729 // Destination register is encoded in Dd; source register in Dm.
1731 Binary |= encodeNEONRd(MI, OpIdx++);
1732 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1734 Binary |= encodeNEONRm(MI, OpIdx);
1736 Binary = convertNEONDataProcToThumb(Binary);
1737 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1741 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1742 const TargetInstrDesc &TID = MI.getDesc();
1743 unsigned Binary = getBinaryCodeForInstr(MI);
1744 // Destination register is encoded in Dd; source registers in Dn and Dm.
1746 Binary |= encodeNEONRd(MI, OpIdx++);
1747 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1749 Binary |= encodeNEONRn(MI, OpIdx++);
1750 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1752 Binary |= encodeNEONRm(MI, OpIdx);
1754 Binary = convertNEONDataProcToThumb(Binary);
1755 // FIXME: This does not handle VMOVDneon or VMOVQ.
1759 #include "ARMGenCodeEmitter.inc"