1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/MachineConstantPool.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/Debug.h"
42 STATISTIC(NumEmitted, "Number of machine instructions emitted");
46 class ARMCodeEmitter {
48 /// getBinaryCodeForInstr - This function, generated by the
49 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
50 /// machine instructions.
51 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
54 template<class CodeEmitter>
55 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
56 public ARMCodeEmitter {
58 const ARMInstrInfo *II;
62 const std::vector<MachineConstantPoolEntry> *MCPEs;
63 const std::vector<MachineJumpTableEntry> *MJTEs;
68 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
69 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
70 MCE(mce), MCPEs(0), MJTEs(0),
71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
72 Emitter(TargetMachine &tm, CodeEmitter &mce,
73 const ARMInstrInfo &ii, const TargetData &td)
74 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
75 MCE(mce), MCPEs(0), MJTEs(0),
76 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
78 bool runOnMachineFunction(MachineFunction &MF);
80 virtual const char *getPassName() const {
81 return "ARM Machine Code Emitter";
84 void emitInstruction(const MachineInstr &MI);
88 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
92 void emitConstPoolInstruction(const MachineInstr &MI);
94 void emitMOVi2piecesInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
98 void emitPseudoMoveInstruction(const MachineInstr &MI);
100 void addPCLabel(unsigned LabelID);
102 void emitPseudoInstruction(const MachineInstr &MI);
104 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
105 const TargetInstrDesc &TID,
106 const MachineOperand &MO,
109 unsigned getMachineSoImmOpValue(unsigned SoImm);
111 unsigned getAddrModeSBit(const MachineInstr &MI,
112 const TargetInstrDesc &TID) const;
114 void emitDataProcessingInstruction(const MachineInstr &MI,
115 unsigned ImplicitRd = 0,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreInstruction(const MachineInstr &MI,
119 unsigned ImplicitRd = 0,
120 unsigned ImplicitRn = 0);
122 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
123 unsigned ImplicitRn = 0);
125 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
127 void emitMulFrmInstruction(const MachineInstr &MI);
129 void emitExtendInstruction(const MachineInstr &MI);
131 void emitMiscArithInstruction(const MachineInstr &MI);
133 void emitBranchInstruction(const MachineInstr &MI);
135 void emitInlineJumpTable(unsigned JTIndex);
137 void emitMiscBranchInstruction(const MachineInstr &MI);
139 void emitVFPArithInstruction(const MachineInstr &MI);
141 void emitVFPConversionInstruction(const MachineInstr &MI);
143 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
145 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
147 void emitMiscInstruction(const MachineInstr &MI);
149 /// getMachineOpValue - Return binary encoding of operand. If the machine
150 /// operand requires relocation, record the relocation and return zero.
151 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
158 unsigned getShiftOp(unsigned Imm) const ;
160 /// Routines that handle operands which add machine relocations which are
161 /// fixed up by the relocation stage.
162 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
163 bool NeedStub, intptr_t ACPV = 0);
164 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
165 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
166 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
167 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
168 intptr_t JTBase = 0);
170 template <class CodeEmitter>
171 char Emitter<CodeEmitter>::ID = 0;
174 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
175 /// to the specified MCE object.
179 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
180 MachineCodeEmitter &MCE) {
181 return new Emitter<MachineCodeEmitter>(TM, MCE);
183 FunctionPass *createARMJITCodeEmitterPass(ARMTargetMachine &TM,
184 JITCodeEmitter &JCE) {
185 return new Emitter<JITCodeEmitter>(TM, JCE);
188 } // end namespace llvm
190 template<class CodeEmitter>
191 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
192 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
193 MF.getTarget().getRelocationModel() != Reloc::Static) &&
194 "JIT relocation model must be set to static or default!");
195 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
196 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
197 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
198 MCPEs = &MF.getConstantPool()->getConstants();
199 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
200 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
201 JTI->Initialize(MF, IsPIC);
204 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
205 MCE.startFunction(MF);
206 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
208 MCE.StartMachineBasicBlock(MBB);
209 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
213 } while (MCE.finishFunction(MF));
218 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
220 template<class CodeEmitter>
221 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
222 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
223 default: assert(0 && "Unknown shift opc!");
224 case ARM_AM::asr: return 2;
225 case ARM_AM::lsl: return 0;
226 case ARM_AM::lsr: return 1;
228 case ARM_AM::rrx: return 3;
233 /// getMachineOpValue - Return binary encoding of operand. If the machine
234 /// operand requires relocation, record the relocation and return zero.
235 template<class CodeEmitter>
236 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
237 const MachineOperand &MO) {
239 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
241 return static_cast<unsigned>(MO.getImm());
242 else if (MO.isGlobal())
243 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
244 else if (MO.isSymbol())
245 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
246 else if (MO.isCPI()) {
247 const TargetInstrDesc &TID = MI.getDesc();
248 // For VFP load, the immediate offset is multiplied by 4.
249 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
250 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
251 emitConstPoolAddress(MO.getIndex(), Reloc);
252 } else if (MO.isJTI())
253 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
255 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
257 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
263 /// emitGlobalAddress - Emit the specified address to the code stream.
265 template<class CodeEmitter>
266 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
267 bool NeedStub, intptr_t ACPV) {
268 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
269 GV, ACPV, NeedStub));
272 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
273 /// be emitted to the current location in the function, and allow it to be PC
275 template<class CodeEmitter>
276 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
278 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
282 /// emitConstPoolAddress - Arrange for the address of an constant pool
283 /// to be emitted to the current location in the function, and allow it to be PC
285 template<class CodeEmitter>
286 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
288 // Tell JIT emitter we'll resolve the address.
289 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
290 Reloc, CPI, 0, true));
293 /// emitJumpTableAddress - Arrange for the address of a jump table to
294 /// be emitted to the current location in the function, and allow it to be PC
296 template<class CodeEmitter>
297 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
299 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
300 Reloc, JTIndex, 0, true));
303 /// emitMachineBasicBlock - Emit the specified address basic block.
304 template<class CodeEmitter>
305 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
306 unsigned Reloc, intptr_t JTBase) {
307 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
311 template<class CodeEmitter>
312 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
314 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
315 << Binary << std::dec << "\n";
317 MCE.emitWordLE(Binary);
320 template<class CodeEmitter>
321 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
323 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
324 << (unsigned)Binary << std::dec << "\n";
325 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
326 << (unsigned)(Binary >> 32) << std::dec << "\n";
328 MCE.emitDWordLE(Binary);
331 template<class CodeEmitter>
332 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
333 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
335 NumEmitted++; // Keep track of the # of mi's emitted
336 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
338 assert(0 && "Unhandled instruction encoding format!");
342 emitPseudoInstruction(MI);
345 case ARMII::DPSoRegFrm:
346 emitDataProcessingInstruction(MI);
350 emitLoadStoreInstruction(MI);
352 case ARMII::LdMiscFrm:
353 case ARMII::StMiscFrm:
354 emitMiscLoadStoreInstruction(MI);
356 case ARMII::LdStMulFrm:
357 emitLoadStoreMultipleInstruction(MI);
360 emitMulFrmInstruction(MI);
363 emitExtendInstruction(MI);
365 case ARMII::ArithMiscFrm:
366 emitMiscArithInstruction(MI);
369 emitBranchInstruction(MI);
371 case ARMII::BrMiscFrm:
372 emitMiscBranchInstruction(MI);
375 case ARMII::VFPUnaryFrm:
376 case ARMII::VFPBinaryFrm:
377 emitVFPArithInstruction(MI);
379 case ARMII::VFPConv1Frm:
380 case ARMII::VFPConv2Frm:
381 case ARMII::VFPConv3Frm:
382 case ARMII::VFPConv4Frm:
383 case ARMII::VFPConv5Frm:
384 emitVFPConversionInstruction(MI);
386 case ARMII::VFPLdStFrm:
387 emitVFPLoadStoreInstruction(MI);
389 case ARMII::VFPLdStMulFrm:
390 emitVFPLoadStoreMultipleInstruction(MI);
392 case ARMII::VFPMiscFrm:
393 emitMiscInstruction(MI);
398 template<class CodeEmitter>
399 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
400 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
401 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
402 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
404 // Remember the CONSTPOOL_ENTRY address for later relocation.
405 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
407 // Emit constpool island entry. In most cases, the actual values will be
408 // resolved and relocated after code emission.
409 if (MCPE.isMachineConstantPoolEntry()) {
410 ARMConstantPoolValue *ACPV =
411 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
413 DOUT << " ** ARM constant pool #" << CPI << " @ "
414 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
416 GlobalValue *GV = ACPV->getGV();
418 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
419 if (ACPV->isNonLazyPointer())
420 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
421 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
422 (intptr_t)ACPV, false));
424 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
425 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
427 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
428 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
432 Constant *CV = MCPE.Val.ConstVal;
435 DOUT << " ** Constant pool #" << CPI << " @ "
436 << (void*)MCE.getCurrentPCValue() << " ";
437 if (const Function *F = dyn_cast<Function>(CV))
438 DOUT << F->getName();
444 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
445 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
447 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
448 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
450 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
451 if (CFP->getType() == Type::FloatTy)
452 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
453 else if (CFP->getType() == Type::DoubleTy)
454 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
456 assert(0 && "Unable to handle this constantpool entry!");
460 assert(0 && "Unable to handle this constantpool entry!");
466 template<class CodeEmitter>
467 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
468 const MachineOperand &MO0 = MI.getOperand(0);
469 const MachineOperand &MO1 = MI.getOperand(1);
470 assert(MO1.isImm() && "Not a valid so_imm value!");
471 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
472 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
474 // Emit the 'mov' instruction.
475 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
477 // Set the conditional execution predicate.
478 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
481 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
484 // Set bit I(25) to identify this is the immediate form of <shifter_op>
485 Binary |= 1 << ARMII::I_BitShift;
486 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
489 // Now the 'orr' instruction.
490 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
492 // Set the conditional execution predicate.
493 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
496 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
499 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
502 // Set bit I(25) to identify this is the immediate form of <shifter_op>
503 Binary |= 1 << ARMII::I_BitShift;
504 Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
508 template<class CodeEmitter>
509 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
510 // It's basically add r, pc, (LJTI - $+8)
512 const TargetInstrDesc &TID = MI.getDesc();
514 // Emit the 'add' instruction.
515 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
517 // Set the conditional execution predicate
518 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520 // Encode S bit if MI modifies CPSR.
521 Binary |= getAddrModeSBit(MI, TID);
524 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
526 // Encode Rn which is PC.
527 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
529 // Encode the displacement.
530 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
531 Binary |= 1 << ARMII::I_BitShift;
532 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
537 template<class CodeEmitter>
538 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
539 unsigned Opcode = MI.getDesc().Opcode;
541 // Part of binary is determined by TableGn.
542 unsigned Binary = getBinaryCodeForInstr(MI);
544 // Set the conditional execution predicate
545 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
547 // Encode S bit if MI modifies CPSR.
548 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
549 Binary |= 1 << ARMII::S_BitShift;
551 // Encode register def if there is one.
552 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
554 // Encode the shift operation.
561 case ARM::MOVsrl_flag:
563 Binary |= (0x2 << 4) | (1 << 7);
565 case ARM::MOVsra_flag:
567 Binary |= (0x4 << 4) | (1 << 7);
571 // Encode register Rm.
572 Binary |= getMachineOpValue(MI, 1);
577 template<class CodeEmitter>
578 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
579 DOUT << " ** LPC" << LabelID << " @ "
580 << (void*)MCE.getCurrentPCValue() << '\n';
581 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
584 template<class CodeEmitter>
585 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
586 unsigned Opcode = MI.getDesc().Opcode;
590 case TargetInstrInfo::INLINEASM: {
591 // We allow inline assembler nodes with empty bodies - they can
592 // implicitly define registers, which is ok for JIT.
593 if (MI.getOperand(0).getSymbolName()[0]) {
594 assert(0 && "JIT does not support inline asm!\n");
599 case TargetInstrInfo::DBG_LABEL:
600 case TargetInstrInfo::EH_LABEL:
601 MCE.emitLabel(MI.getOperand(0).getImm());
603 case TargetInstrInfo::IMPLICIT_DEF:
604 case TargetInstrInfo::DECLARE:
608 case ARM::CONSTPOOL_ENTRY:
609 emitConstPoolInstruction(MI);
612 // Remember of the address of the PC label for relocation later.
613 addPCLabel(MI.getOperand(2).getImm());
614 // PICADD is just an add instruction that implicitly read pc.
615 emitDataProcessingInstruction(MI, 0, ARM::PC);
622 // Remember of the address of the PC label for relocation later.
623 addPCLabel(MI.getOperand(2).getImm());
624 // These are just load / store instructions that implicitly read pc.
625 emitLoadStoreInstruction(MI, 0, ARM::PC);
632 // Remember of the address of the PC label for relocation later.
633 addPCLabel(MI.getOperand(2).getImm());
634 // These are just load / store instructions that implicitly read pc.
635 emitMiscLoadStoreInstruction(MI, ARM::PC);
638 case ARM::MOVi2pieces:
639 // Two instructions to materialize a constant.
640 emitMOVi2piecesInstruction(MI);
642 case ARM::LEApcrelJT:
643 // Materialize jumptable address.
644 emitLEApcrelJTInstruction(MI);
647 case ARM::MOVsrl_flag:
648 case ARM::MOVsra_flag:
649 emitPseudoMoveInstruction(MI);
654 template<class CodeEmitter>
655 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
656 const MachineInstr &MI,
657 const TargetInstrDesc &TID,
658 const MachineOperand &MO,
660 unsigned Binary = getMachineOpValue(MI, MO);
662 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
663 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
664 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
666 // Encode the shift opcode.
668 unsigned Rs = MO1.getReg();
670 // Set shift operand (bit[7:4]).
675 // RRX - 0110 and bit[11:8] clear.
677 default: assert(0 && "Unknown shift opc!");
678 case ARM_AM::lsl: SBits = 0x1; break;
679 case ARM_AM::lsr: SBits = 0x3; break;
680 case ARM_AM::asr: SBits = 0x5; break;
681 case ARM_AM::ror: SBits = 0x7; break;
682 case ARM_AM::rrx: SBits = 0x6; break;
685 // Set shift operand (bit[6:4]).
691 default: assert(0 && "Unknown shift opc!");
692 case ARM_AM::lsl: SBits = 0x0; break;
693 case ARM_AM::lsr: SBits = 0x2; break;
694 case ARM_AM::asr: SBits = 0x4; break;
695 case ARM_AM::ror: SBits = 0x6; break;
698 Binary |= SBits << 4;
699 if (SOpc == ARM_AM::rrx)
702 // Encode the shift operation Rs or shift_imm (except rrx).
704 // Encode Rs bit[11:8].
705 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
707 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
710 // Encode shift_imm bit[11:7].
711 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
714 template<class CodeEmitter>
715 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
716 // Encode rotate_imm.
717 unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
718 << ARMII::SoRotImmShift;
721 Binary |= ARM_AM::getSOImmValImm(SoImm);
725 template<class CodeEmitter>
726 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
727 const TargetInstrDesc &TID) const {
728 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
729 const MachineOperand &MO = MI.getOperand(i-1);
730 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
731 return 1 << ARMII::S_BitShift;
736 template<class CodeEmitter>
737 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
738 const MachineInstr &MI,
740 unsigned ImplicitRn) {
741 const TargetInstrDesc &TID = MI.getDesc();
743 // Part of binary is determined by TableGn.
744 unsigned Binary = getBinaryCodeForInstr(MI);
746 // Set the conditional execution predicate
747 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
749 // Encode S bit if MI modifies CPSR.
750 Binary |= getAddrModeSBit(MI, TID);
752 // Encode register def if there is one.
753 unsigned NumDefs = TID.getNumDefs();
756 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
758 // Special handling for implicit use (e.g. PC).
759 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
760 << ARMII::RegRdShift);
762 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
763 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
766 // Encode first non-shifter register operand if there is one.
767 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
770 // Special handling for implicit use (e.g. PC).
771 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
772 << ARMII::RegRnShift);
774 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
779 // Encode shifter operand.
780 const MachineOperand &MO = MI.getOperand(OpIdx);
781 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
783 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
788 // Encode register Rm.
789 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
794 // Set bit I(25) to identify this is the immediate form of <shifter_op>.
795 Binary |= 1 << ARMII::I_BitShift;
796 Binary |= getMachineSoImmOpValue(MO.getImm());
801 template<class CodeEmitter>
802 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
803 const MachineInstr &MI,
805 unsigned ImplicitRn) {
806 const TargetInstrDesc &TID = MI.getDesc();
807 unsigned Form = TID.TSFlags & ARMII::FormMask;
808 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
810 // Part of binary is determined by TableGn.
811 unsigned Binary = getBinaryCodeForInstr(MI);
813 // Set the conditional execution predicate
814 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
818 // Operand 0 of a pre- and post-indexed store is the address base
819 // writeback. Skip it.
820 bool Skipped = false;
821 if (IsPrePost && Form == ARMII::StFrm) {
828 // Special handling for implicit use (e.g. PC).
829 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
830 << ARMII::RegRdShift);
832 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
834 // Set second operand
836 // Special handling for implicit use (e.g. PC).
837 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
838 << ARMII::RegRnShift);
840 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
842 // If this is a two-address operand, skip it. e.g. LDR_PRE.
843 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
846 const MachineOperand &MO2 = MI.getOperand(OpIdx);
847 unsigned AM2Opc = (ImplicitRn == ARM::PC)
848 ? 0 : MI.getOperand(OpIdx+1).getImm();
850 // Set bit U(23) according to sign of immed value (positive or negative).
851 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
853 if (!MO2.getReg()) { // is immediate
854 if (ARM_AM::getAM2Offset(AM2Opc))
855 // Set the value of offset_12 field
856 Binary |= ARM_AM::getAM2Offset(AM2Opc);
861 // Set bit I(25), because this is not in immediate enconding.
862 Binary |= 1 << ARMII::I_BitShift;
863 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
864 // Set bit[3:0] to the corresponding Rm register
865 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
867 // If this instr is in scaled register offset/index instruction, set
868 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
869 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
870 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
871 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
877 template<class CodeEmitter>
878 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
879 unsigned ImplicitRn) {
880 const TargetInstrDesc &TID = MI.getDesc();
881 unsigned Form = TID.TSFlags & ARMII::FormMask;
882 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
884 // Part of binary is determined by TableGn.
885 unsigned Binary = getBinaryCodeForInstr(MI);
887 // Set the conditional execution predicate
888 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
892 // Operand 0 of a pre- and post-indexed store is the address base
893 // writeback. Skip it.
894 bool Skipped = false;
895 if (IsPrePost && Form == ARMII::StMiscFrm) {
901 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
903 // Skip LDRD and STRD's second operand.
904 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
907 // Set second operand
909 // Special handling for implicit use (e.g. PC).
910 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
911 << ARMII::RegRnShift);
913 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
915 // If this is a two-address operand, skip it. e.g. LDRH_POST.
916 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
919 const MachineOperand &MO2 = MI.getOperand(OpIdx);
920 unsigned AM3Opc = (ImplicitRn == ARM::PC)
921 ? 0 : MI.getOperand(OpIdx+1).getImm();
923 // Set bit U(23) according to sign of immed value (positive or negative)
924 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
927 // If this instr is in register offset/index encoding, set bit[3:0]
928 // to the corresponding Rm register.
930 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
935 // This instr is in immediate offset/index encoding, set bit 22 to 1.
936 Binary |= 1 << ARMII::AM3_I_BitShift;
937 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
939 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
940 Binary |= (ImmOffs & 0xF); // immedL
946 static unsigned getAddrModeUPBits(unsigned Mode) {
949 // Set addressing mode by modifying bits U(23) and P(24)
950 // IA - Increment after - bit U = 1 and bit P = 0
951 // IB - Increment before - bit U = 1 and bit P = 1
952 // DA - Decrement after - bit U = 0 and bit P = 0
953 // DB - Decrement before - bit U = 0 and bit P = 1
955 default: assert(0 && "Unknown addressing sub-mode!");
956 case ARM_AM::da: break;
957 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
958 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
959 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
965 template<class CodeEmitter>
966 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
967 const MachineInstr &MI) {
968 // Part of binary is determined by TableGn.
969 unsigned Binary = getBinaryCodeForInstr(MI);
971 // Set the conditional execution predicate
972 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
974 // Set base address operand
975 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
977 // Set addressing mode by modifying bits U(23) and P(24)
978 const MachineOperand &MO = MI.getOperand(1);
979 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
982 if (ARM_AM::getAM4WBFlag(MO.getImm()))
983 Binary |= 0x1 << ARMII::W_BitShift;
986 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
987 const MachineOperand &MO = MI.getOperand(i);
988 if (!MO.isReg() || MO.isImplicit())
990 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
991 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
993 Binary |= 0x1 << RegNum;
999 template<class CodeEmitter>
1000 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1001 const TargetInstrDesc &TID = MI.getDesc();
1003 // Part of binary is determined by TableGn.
1004 unsigned Binary = getBinaryCodeForInstr(MI);
1006 // Set the conditional execution predicate
1007 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1009 // Encode S bit if MI modifies CPSR.
1010 Binary |= getAddrModeSBit(MI, TID);
1012 // 32x32->64bit operations have two destination registers. The number
1013 // of register definitions will tell us if that's what we're dealing with.
1015 if (TID.getNumDefs() == 2)
1016 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1019 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1022 Binary |= getMachineOpValue(MI, OpIdx++);
1025 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1027 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1028 // it as Rn (for multiply, that's in the same offset as RdLo.
1029 if (TID.getNumOperands() > OpIdx &&
1030 !TID.OpInfo[OpIdx].isPredicate() &&
1031 !TID.OpInfo[OpIdx].isOptionalDef())
1032 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1037 template<class CodeEmitter>
1038 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1039 const TargetInstrDesc &TID = MI.getDesc();
1041 // Part of binary is determined by TableGn.
1042 unsigned Binary = getBinaryCodeForInstr(MI);
1044 // Set the conditional execution predicate
1045 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1050 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1052 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1053 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1055 // Two register operand form.
1057 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1060 Binary |= getMachineOpValue(MI, MO2);
1063 Binary |= getMachineOpValue(MI, MO1);
1066 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1067 if (MI.getOperand(OpIdx).isImm() &&
1068 !TID.OpInfo[OpIdx].isPredicate() &&
1069 !TID.OpInfo[OpIdx].isOptionalDef())
1070 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1075 template<class CodeEmitter>
1076 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1077 const TargetInstrDesc &TID = MI.getDesc();
1079 // Part of binary is determined by TableGn.
1080 unsigned Binary = getBinaryCodeForInstr(MI);
1082 // Set the conditional execution predicate
1083 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1088 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1090 const MachineOperand &MO = MI.getOperand(OpIdx++);
1091 if (OpIdx == TID.getNumOperands() ||
1092 TID.OpInfo[OpIdx].isPredicate() ||
1093 TID.OpInfo[OpIdx].isOptionalDef()) {
1094 // Encode Rm and it's done.
1095 Binary |= getMachineOpValue(MI, MO);
1101 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1104 Binary |= getMachineOpValue(MI, OpIdx++);
1106 // Encode shift_imm.
1107 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1108 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1109 Binary |= ShiftAmt << ARMII::ShiftShift;
1114 template<class CodeEmitter>
1115 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1116 const TargetInstrDesc &TID = MI.getDesc();
1118 if (TID.Opcode == ARM::TPsoft)
1121 // Part of binary is determined by TableGn.
1122 unsigned Binary = getBinaryCodeForInstr(MI);
1124 // Set the conditional execution predicate
1125 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1127 // Set signed_immed_24 field
1128 Binary |= getMachineOpValue(MI, 0);
1133 template<class CodeEmitter>
1134 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1135 // Remember the base address of the inline jump table.
1136 uintptr_t JTBase = MCE.getCurrentPCValue();
1137 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1138 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1140 // Now emit the jump table entries.
1141 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1142 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1144 // DestBB address - JT base.
1145 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1147 // Absolute DestBB address.
1148 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1153 template<class CodeEmitter>
1154 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1155 const TargetInstrDesc &TID = MI.getDesc();
1157 // Handle jump tables.
1158 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1159 // First emit a ldr pc, [] instruction.
1160 emitDataProcessingInstruction(MI, ARM::PC);
1162 // Then emit the inline jump table.
1163 unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1164 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1165 emitInlineJumpTable(JTIndex);
1167 } else if (TID.Opcode == ARM::BR_JTm) {
1168 // First emit a ldr pc, [] instruction.
1169 emitLoadStoreInstruction(MI, ARM::PC);
1171 // Then emit the inline jump table.
1172 emitInlineJumpTable(MI.getOperand(3).getIndex());
1176 // Part of binary is determined by TableGn.
1177 unsigned Binary = getBinaryCodeForInstr(MI);
1179 // Set the conditional execution predicate
1180 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1182 if (TID.Opcode == ARM::BX_RET)
1183 // The return register is LR.
1184 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1186 // otherwise, set the return register
1187 Binary |= getMachineOpValue(MI, 0);
1192 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1193 unsigned RegD = MI.getOperand(OpIdx).getReg();
1194 unsigned Binary = 0;
1195 bool isSPVFP = false;
1196 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1198 Binary |= RegD << ARMII::RegRdShift;
1200 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1201 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1206 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1207 unsigned RegN = MI.getOperand(OpIdx).getReg();
1208 unsigned Binary = 0;
1209 bool isSPVFP = false;
1210 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1212 Binary |= RegN << ARMII::RegRnShift;
1214 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1215 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1220 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1221 unsigned RegM = MI.getOperand(OpIdx).getReg();
1222 unsigned Binary = 0;
1223 bool isSPVFP = false;
1224 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1228 Binary |= ((RegM & 0x1E) >> 1);
1229 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1234 template<class CodeEmitter>
1235 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1236 const TargetInstrDesc &TID = MI.getDesc();
1238 // Part of binary is determined by TableGn.
1239 unsigned Binary = getBinaryCodeForInstr(MI);
1241 // Set the conditional execution predicate
1242 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1245 assert((Binary & ARMII::D_BitShift) == 0 &&
1246 (Binary & ARMII::N_BitShift) == 0 &&
1247 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1250 Binary |= encodeVFPRd(MI, OpIdx++);
1252 // If this is a two-address operand, skip it, e.g. FMACD.
1253 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1257 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1258 Binary |= encodeVFPRn(MI, OpIdx++);
1260 if (OpIdx == TID.getNumOperands() ||
1261 TID.OpInfo[OpIdx].isPredicate() ||
1262 TID.OpInfo[OpIdx].isOptionalDef()) {
1263 // FCMPEZD etc. has only one operand.
1269 Binary |= encodeVFPRm(MI, OpIdx);
1274 template<class CodeEmitter>
1275 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1276 const MachineInstr &MI) {
1277 const TargetInstrDesc &TID = MI.getDesc();
1278 unsigned Form = TID.TSFlags & ARMII::FormMask;
1280 // Part of binary is determined by TableGn.
1281 unsigned Binary = getBinaryCodeForInstr(MI);
1283 // Set the conditional execution predicate
1284 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1288 case ARMII::VFPConv1Frm:
1289 case ARMII::VFPConv2Frm:
1290 case ARMII::VFPConv3Frm:
1292 Binary |= encodeVFPRd(MI, 0);
1294 case ARMII::VFPConv4Frm:
1296 Binary |= encodeVFPRn(MI, 0);
1298 case ARMII::VFPConv5Frm:
1300 Binary |= encodeVFPRm(MI, 0);
1306 case ARMII::VFPConv1Frm:
1308 Binary |= encodeVFPRm(MI, 1);
1310 case ARMII::VFPConv2Frm:
1311 case ARMII::VFPConv3Frm:
1313 Binary |= encodeVFPRn(MI, 1);
1315 case ARMII::VFPConv4Frm:
1316 case ARMII::VFPConv5Frm:
1318 Binary |= encodeVFPRd(MI, 1);
1322 if (Form == ARMII::VFPConv5Frm)
1324 Binary |= encodeVFPRn(MI, 2);
1325 else if (Form == ARMII::VFPConv3Frm)
1327 Binary |= encodeVFPRm(MI, 2);
1332 template<class CodeEmitter>
1333 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1334 // Part of binary is determined by TableGn.
1335 unsigned Binary = getBinaryCodeForInstr(MI);
1337 // Set the conditional execution predicate
1338 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1343 Binary |= encodeVFPRd(MI, OpIdx++);
1345 // Encode address base.
1346 const MachineOperand &Base = MI.getOperand(OpIdx++);
1347 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1349 // If there is a non-zero immediate offset, encode it.
1351 const MachineOperand &Offset = MI.getOperand(OpIdx);
1352 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1353 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1354 Binary |= 1 << ARMII::U_BitShift;
1361 // If immediate offset is omitted, default to +0.
1362 Binary |= 1 << ARMII::U_BitShift;
1367 template<class CodeEmitter>
1368 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1369 const MachineInstr &MI) {
1370 // Part of binary is determined by TableGn.
1371 unsigned Binary = getBinaryCodeForInstr(MI);
1373 // Set the conditional execution predicate
1374 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1376 // Set base address operand
1377 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1379 // Set addressing mode by modifying bits U(23) and P(24)
1380 const MachineOperand &MO = MI.getOperand(1);
1381 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1384 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1385 Binary |= 0x1 << ARMII::W_BitShift;
1387 // First register is encoded in Dd.
1388 Binary |= encodeVFPRd(MI, 4);
1390 // Number of registers are encoded in offset field.
1391 unsigned NumRegs = 1;
1392 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1393 const MachineOperand &MO = MI.getOperand(i);
1394 if (!MO.isReg() || MO.isImplicit())
1398 Binary |= NumRegs * 2;
1403 template<class CodeEmitter>
1404 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1405 // Part of binary is determined by TableGn.
1406 unsigned Binary = getBinaryCodeForInstr(MI);
1408 // Set the conditional execution predicate
1409 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1414 #include "ARMGenCodeEmitter.inc"