1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
59 void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<MachineModuleInfo>();
61 MachineFunctionPass::getAnalysisUsage(AU);
66 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
67 : MachineFunctionPass(&ID), JTI(0),
68 II((const ARMInstrInfo *)tm.getInstrInfo()),
69 TD(tm.getTargetData()), TM(tm),
70 MCE(mce), MCPEs(0), MJTEs(0),
71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73 /// getBinaryCodeForInstr - This function, generated by the
74 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75 /// machine instructions.
76 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78 bool runOnMachineFunction(MachineFunction &MF);
80 virtual const char *getPassName() const {
81 return "ARM Machine Code Emitter";
84 void emitInstruction(const MachineInstr &MI);
88 void emitWordLE(unsigned Binary);
89 void emitDWordLE(uint64_t Binary);
90 void emitConstPoolInstruction(const MachineInstr &MI);
91 void emitMOVi2piecesInstruction(const MachineInstr &MI);
92 void emitLEApcrelJTInstruction(const MachineInstr &MI);
93 void emitPseudoMoveInstruction(const MachineInstr &MI);
94 void addPCLabel(unsigned LabelID);
95 void emitPseudoInstruction(const MachineInstr &MI);
96 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
97 const TargetInstrDesc &TID,
98 const MachineOperand &MO,
101 unsigned getMachineSoImmOpValue(unsigned SoImm);
103 unsigned getAddrModeSBit(const MachineInstr &MI,
104 const TargetInstrDesc &TID) const;
106 void emitDataProcessingInstruction(const MachineInstr &MI,
107 unsigned ImplicitRd = 0,
108 unsigned ImplicitRn = 0);
110 void emitLoadStoreInstruction(const MachineInstr &MI,
111 unsigned ImplicitRd = 0,
112 unsigned ImplicitRn = 0);
114 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
115 unsigned ImplicitRn = 0);
117 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119 void emitMulFrmInstruction(const MachineInstr &MI);
121 void emitExtendInstruction(const MachineInstr &MI);
123 void emitMiscArithInstruction(const MachineInstr &MI);
125 void emitBranchInstruction(const MachineInstr &MI);
127 void emitInlineJumpTable(unsigned JTIndex);
129 void emitMiscBranchInstruction(const MachineInstr &MI);
131 void emitVFPArithInstruction(const MachineInstr &MI);
133 void emitVFPConversionInstruction(const MachineInstr &MI);
135 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
137 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
139 void emitMiscInstruction(const MachineInstr &MI);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
144 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
145 return getMachineOpValue(MI, MI.getOperand(OpIdx));
148 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
150 unsigned getShiftOp(unsigned Imm) const ;
152 /// Routines that handle operands which add machine relocations which are
153 /// fixed up by the relocation stage.
154 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
155 bool MayNeedFarStub, bool Indirect,
157 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
158 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
159 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
160 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
161 intptr_t JTBase = 0);
165 char ARMCodeEmitter::ID = 0;
167 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
168 /// code to the specified MCE object.
169 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
170 JITCodeEmitter &JCE) {
171 return new ARMCodeEmitter(TM, JCE);
174 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
175 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
176 MF.getTarget().getRelocationModel() != Reloc::Static) &&
177 "JIT relocation model must be set to static or default!");
178 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
179 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
180 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
181 Subtarget = &TM.getSubtarget<ARMSubtarget>();
182 MCPEs = &MF.getConstantPool()->getConstants();
184 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
185 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
186 JTI->Initialize(MF, IsPIC);
187 MMI = &getAnalysis<MachineModuleInfo>();
188 MCE.setModuleInfo(MMI);
191 DEBUG(errs() << "JITTing function '"
192 << MF.getFunction()->getName() << "'\n");
193 MCE.startFunction(MF);
194 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
196 MCE.StartMachineBasicBlock(MBB);
197 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
201 } while (MCE.finishFunction(MF));
206 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
208 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
209 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
210 default: llvm_unreachable("Unknown shift opc!");
211 case ARM_AM::asr: return 2;
212 case ARM_AM::lsl: return 0;
213 case ARM_AM::lsr: return 1;
215 case ARM_AM::rrx: return 3;
220 /// getMachineOpValue - Return binary encoding of operand. If the machine
221 /// operand requires relocation, record the relocation and return zero.
222 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
223 const MachineOperand &MO) {
225 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
227 return static_cast<unsigned>(MO.getImm());
228 else if (MO.isGlobal())
229 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
230 else if (MO.isSymbol())
231 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
232 else if (MO.isCPI()) {
233 const TargetInstrDesc &TID = MI.getDesc();
234 // For VFP load, the immediate offset is multiplied by 4.
235 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
236 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
237 emitConstPoolAddress(MO.getIndex(), Reloc);
238 } else if (MO.isJTI())
239 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
241 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
251 /// emitGlobalAddress - Emit the specified address to the code stream.
253 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
254 bool MayNeedFarStub, bool Indirect,
256 MachineRelocation MR = Indirect
257 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
258 const_cast<GlobalValue *>(GV),
259 ACPV, MayNeedFarStub)
260 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
261 const_cast<GlobalValue *>(GV), ACPV,
263 MCE.addRelocation(MR);
266 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
267 /// be emitted to the current location in the function, and allow it to be PC
269 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
270 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
274 /// emitConstPoolAddress - Arrange for the address of an constant pool
275 /// to be emitted to the current location in the function, and allow it to be PC
277 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
278 // Tell JIT emitter we'll resolve the address.
279 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
280 Reloc, CPI, 0, true));
283 /// emitJumpTableAddress - Arrange for the address of a jump table to
284 /// be emitted to the current location in the function, and allow it to be PC
286 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
287 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
288 Reloc, JTIndex, 0, true));
291 /// emitMachineBasicBlock - Emit the specified address basic block.
292 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
293 unsigned Reloc, intptr_t JTBase) {
294 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
298 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
299 DEBUG(errs() << " 0x";
300 errs().write_hex(Binary) << "\n");
301 MCE.emitWordLE(Binary);
304 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
305 DEBUG(errs() << " 0x";
306 errs().write_hex(Binary) << "\n");
307 MCE.emitDWordLE(Binary);
310 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
311 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
313 MCE.processDebugLoc(MI.getDebugLoc(), true);
315 NumEmitted++; // Keep track of the # of mi's emitted
316 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
318 llvm_unreachable("Unhandled instruction encoding format!");
322 emitPseudoInstruction(MI);
325 case ARMII::DPSoRegFrm:
326 emitDataProcessingInstruction(MI);
330 emitLoadStoreInstruction(MI);
332 case ARMII::LdMiscFrm:
333 case ARMII::StMiscFrm:
334 emitMiscLoadStoreInstruction(MI);
336 case ARMII::LdStMulFrm:
337 emitLoadStoreMultipleInstruction(MI);
340 emitMulFrmInstruction(MI);
343 emitExtendInstruction(MI);
345 case ARMII::ArithMiscFrm:
346 emitMiscArithInstruction(MI);
349 emitBranchInstruction(MI);
351 case ARMII::BrMiscFrm:
352 emitMiscBranchInstruction(MI);
355 case ARMII::VFPUnaryFrm:
356 case ARMII::VFPBinaryFrm:
357 emitVFPArithInstruction(MI);
359 case ARMII::VFPConv1Frm:
360 case ARMII::VFPConv2Frm:
361 case ARMII::VFPConv3Frm:
362 case ARMII::VFPConv4Frm:
363 case ARMII::VFPConv5Frm:
364 emitVFPConversionInstruction(MI);
366 case ARMII::VFPLdStFrm:
367 emitVFPLoadStoreInstruction(MI);
369 case ARMII::VFPLdStMulFrm:
370 emitVFPLoadStoreMultipleInstruction(MI);
372 case ARMII::VFPMiscFrm:
373 emitMiscInstruction(MI);
376 MCE.processDebugLoc(MI.getDebugLoc(), false);
379 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
380 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
381 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
382 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
384 // Remember the CONSTPOOL_ENTRY address for later relocation.
385 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
387 // Emit constpool island entry. In most cases, the actual values will be
388 // resolved and relocated after code emission.
389 if (MCPE.isMachineConstantPoolEntry()) {
390 ARMConstantPoolValue *ACPV =
391 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
393 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
394 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
396 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
397 const GlobalValue *GV = ACPV->getGV();
399 Reloc::Model RelocM = TM.getRelocationModel();
400 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
402 Subtarget->GVIsIndirectSymbol(GV, RelocM),
405 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
409 const Constant *CV = MCPE.Val.ConstVal;
412 errs() << " ** Constant pool #" << CPI << " @ "
413 << (void*)MCE.getCurrentPCValue() << " ";
414 if (const Function *F = dyn_cast<Function>(CV))
415 errs() << F->getName();
421 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
422 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
424 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
425 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
427 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
428 if (CFP->getType()->isFloatTy())
429 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
430 else if (CFP->getType()->isDoubleTy())
431 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
433 llvm_unreachable("Unable to handle this constantpool entry!");
436 llvm_unreachable("Unable to handle this constantpool entry!");
441 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
442 const MachineOperand &MO0 = MI.getOperand(0);
443 const MachineOperand &MO1 = MI.getOperand(1);
444 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
445 "Not a valid so_imm value!");
446 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
447 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
449 // Emit the 'mov' instruction.
450 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
452 // Set the conditional execution predicate.
453 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
456 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
459 // Set bit I(25) to identify this is the immediate form of <shifter_op>
460 Binary |= 1 << ARMII::I_BitShift;
461 Binary |= getMachineSoImmOpValue(V1);
464 // Now the 'orr' instruction.
465 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
467 // Set the conditional execution predicate.
468 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
471 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
474 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
477 // Set bit I(25) to identify this is the immediate form of <shifter_op>
478 Binary |= 1 << ARMII::I_BitShift;
479 Binary |= getMachineSoImmOpValue(V2);
483 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
484 // It's basically add r, pc, (LJTI - $+8)
486 const TargetInstrDesc &TID = MI.getDesc();
488 // Emit the 'add' instruction.
489 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
491 // Set the conditional execution predicate
492 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
494 // Encode S bit if MI modifies CPSR.
495 Binary |= getAddrModeSBit(MI, TID);
498 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
500 // Encode Rn which is PC.
501 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
503 // Encode the displacement.
504 Binary |= 1 << ARMII::I_BitShift;
505 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
510 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
511 unsigned Opcode = MI.getDesc().Opcode;
513 // Part of binary is determined by TableGn.
514 unsigned Binary = getBinaryCodeForInstr(MI);
516 // Set the conditional execution predicate
517 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
519 // Encode S bit if MI modifies CPSR.
520 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
521 Binary |= 1 << ARMII::S_BitShift;
523 // Encode register def if there is one.
524 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
526 // Encode the shift operation.
533 case ARM::MOVsrl_flag:
535 Binary |= (0x2 << 4) | (1 << 7);
537 case ARM::MOVsra_flag:
539 Binary |= (0x4 << 4) | (1 << 7);
543 // Encode register Rm.
544 Binary |= getMachineOpValue(MI, 1);
549 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
550 DEBUG(errs() << " ** LPC" << LabelID << " @ "
551 << (void*)MCE.getCurrentPCValue() << '\n');
552 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
555 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
556 unsigned Opcode = MI.getDesc().Opcode;
559 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
560 // FIXME: Add support for MOVimm32.
561 case TargetOpcode::INLINEASM: {
562 // We allow inline assembler nodes with empty bodies - they can
563 // implicitly define registers, which is ok for JIT.
564 if (MI.getOperand(0).getSymbolName()[0]) {
565 report_fatal_error("JIT does not support inline asm!");
569 case TargetOpcode::DBG_LABEL:
570 case TargetOpcode::EH_LABEL:
571 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
573 case TargetOpcode::IMPLICIT_DEF:
574 case TargetOpcode::KILL:
577 case ARM::CONSTPOOL_ENTRY:
578 emitConstPoolInstruction(MI);
581 // Remember of the address of the PC label for relocation later.
582 addPCLabel(MI.getOperand(2).getImm());
583 // PICADD is just an add instruction that implicitly read pc.
584 emitDataProcessingInstruction(MI, 0, ARM::PC);
591 // Remember of the address of the PC label for relocation later.
592 addPCLabel(MI.getOperand(2).getImm());
593 // These are just load / store instructions that implicitly read pc.
594 emitLoadStoreInstruction(MI, 0, ARM::PC);
601 // Remember of the address of the PC label for relocation later.
602 addPCLabel(MI.getOperand(2).getImm());
603 // These are just load / store instructions that implicitly read pc.
604 emitMiscLoadStoreInstruction(MI, ARM::PC);
607 case ARM::MOVi2pieces:
608 // Two instructions to materialize a constant.
609 emitMOVi2piecesInstruction(MI);
611 case ARM::LEApcrelJT:
612 // Materialize jumptable address.
613 emitLEApcrelJTInstruction(MI);
616 case ARM::MOVsrl_flag:
617 case ARM::MOVsra_flag:
618 emitPseudoMoveInstruction(MI);
623 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
624 const TargetInstrDesc &TID,
625 const MachineOperand &MO,
627 unsigned Binary = getMachineOpValue(MI, MO);
629 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
630 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
631 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
633 // Encode the shift opcode.
635 unsigned Rs = MO1.getReg();
637 // Set shift operand (bit[7:4]).
642 // RRX - 0110 and bit[11:8] clear.
644 default: llvm_unreachable("Unknown shift opc!");
645 case ARM_AM::lsl: SBits = 0x1; break;
646 case ARM_AM::lsr: SBits = 0x3; break;
647 case ARM_AM::asr: SBits = 0x5; break;
648 case ARM_AM::ror: SBits = 0x7; break;
649 case ARM_AM::rrx: SBits = 0x6; break;
652 // Set shift operand (bit[6:4]).
658 default: llvm_unreachable("Unknown shift opc!");
659 case ARM_AM::lsl: SBits = 0x0; break;
660 case ARM_AM::lsr: SBits = 0x2; break;
661 case ARM_AM::asr: SBits = 0x4; break;
662 case ARM_AM::ror: SBits = 0x6; break;
665 Binary |= SBits << 4;
666 if (SOpc == ARM_AM::rrx)
669 // Encode the shift operation Rs or shift_imm (except rrx).
671 // Encode Rs bit[11:8].
672 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
674 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
677 // Encode shift_imm bit[11:7].
678 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
681 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
682 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
683 assert(SoImmVal != -1 && "Not a valid so_imm value!");
685 // Encode rotate_imm.
686 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
687 << ARMII::SoRotImmShift;
690 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
694 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
695 const TargetInstrDesc &TID) const {
696 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
697 const MachineOperand &MO = MI.getOperand(i-1);
698 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
699 return 1 << ARMII::S_BitShift;
704 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
706 unsigned ImplicitRn) {
707 const TargetInstrDesc &TID = MI.getDesc();
709 if (TID.Opcode == ARM::BFC) {
710 report_fatal_error("ARMv6t2 JIT is not yet supported.");
713 // Part of binary is determined by TableGn.
714 unsigned Binary = getBinaryCodeForInstr(MI);
716 // Set the conditional execution predicate
717 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
719 // Encode S bit if MI modifies CPSR.
720 Binary |= getAddrModeSBit(MI, TID);
722 // Encode register def if there is one.
723 unsigned NumDefs = TID.getNumDefs();
726 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
728 // Special handling for implicit use (e.g. PC).
729 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
730 << ARMII::RegRdShift);
732 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
733 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
736 // Encode first non-shifter register operand if there is one.
737 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
740 // Special handling for implicit use (e.g. PC).
741 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
742 << ARMII::RegRnShift);
744 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
749 // Encode shifter operand.
750 const MachineOperand &MO = MI.getOperand(OpIdx);
751 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
753 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
758 // Encode register Rm.
759 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
764 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
769 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
771 unsigned ImplicitRn) {
772 const TargetInstrDesc &TID = MI.getDesc();
773 unsigned Form = TID.TSFlags & ARMII::FormMask;
774 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
776 // Part of binary is determined by TableGn.
777 unsigned Binary = getBinaryCodeForInstr(MI);
779 // Set the conditional execution predicate
780 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
784 // Operand 0 of a pre- and post-indexed store is the address base
785 // writeback. Skip it.
786 bool Skipped = false;
787 if (IsPrePost && Form == ARMII::StFrm) {
794 // Special handling for implicit use (e.g. PC).
795 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
796 << ARMII::RegRdShift);
798 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
800 // Set second operand
802 // Special handling for implicit use (e.g. PC).
803 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
804 << ARMII::RegRnShift);
806 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
808 // If this is a two-address operand, skip it. e.g. LDR_PRE.
809 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
812 const MachineOperand &MO2 = MI.getOperand(OpIdx);
813 unsigned AM2Opc = (ImplicitRn == ARM::PC)
814 ? 0 : MI.getOperand(OpIdx+1).getImm();
816 // Set bit U(23) according to sign of immed value (positive or negative).
817 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
819 if (!MO2.getReg()) { // is immediate
820 if (ARM_AM::getAM2Offset(AM2Opc))
821 // Set the value of offset_12 field
822 Binary |= ARM_AM::getAM2Offset(AM2Opc);
827 // Set bit I(25), because this is not in immediate enconding.
828 Binary |= 1 << ARMII::I_BitShift;
829 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
830 // Set bit[3:0] to the corresponding Rm register
831 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
833 // If this instr is in scaled register offset/index instruction, set
834 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
835 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
836 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
837 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
843 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
844 unsigned ImplicitRn) {
845 const TargetInstrDesc &TID = MI.getDesc();
846 unsigned Form = TID.TSFlags & ARMII::FormMask;
847 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
849 // Part of binary is determined by TableGn.
850 unsigned Binary = getBinaryCodeForInstr(MI);
852 // Set the conditional execution predicate
853 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
857 // Operand 0 of a pre- and post-indexed store is the address base
858 // writeback. Skip it.
859 bool Skipped = false;
860 if (IsPrePost && Form == ARMII::StMiscFrm) {
866 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
868 // Skip LDRD and STRD's second operand.
869 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
872 // Set second operand
874 // Special handling for implicit use (e.g. PC).
875 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
876 << ARMII::RegRnShift);
878 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
880 // If this is a two-address operand, skip it. e.g. LDRH_POST.
881 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
884 const MachineOperand &MO2 = MI.getOperand(OpIdx);
885 unsigned AM3Opc = (ImplicitRn == ARM::PC)
886 ? 0 : MI.getOperand(OpIdx+1).getImm();
888 // Set bit U(23) according to sign of immed value (positive or negative)
889 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
892 // If this instr is in register offset/index encoding, set bit[3:0]
893 // to the corresponding Rm register.
895 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
900 // This instr is in immediate offset/index encoding, set bit 22 to 1.
901 Binary |= 1 << ARMII::AM3_I_BitShift;
902 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
904 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
905 Binary |= (ImmOffs & 0xF); // immedL
911 static unsigned getAddrModeUPBits(unsigned Mode) {
914 // Set addressing mode by modifying bits U(23) and P(24)
915 // IA - Increment after - bit U = 1 and bit P = 0
916 // IB - Increment before - bit U = 1 and bit P = 1
917 // DA - Decrement after - bit U = 0 and bit P = 0
918 // DB - Decrement before - bit U = 0 and bit P = 1
920 default: llvm_unreachable("Unknown addressing sub-mode!");
921 case ARM_AM::da: break;
922 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
923 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
924 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
930 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
931 const TargetInstrDesc &TID = MI.getDesc();
932 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
934 // Part of binary is determined by TableGn.
935 unsigned Binary = getBinaryCodeForInstr(MI);
937 // Set the conditional execution predicate
938 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
940 // Skip operand 0 of an instruction with base register update.
945 // Set base address operand
946 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
948 // Set addressing mode by modifying bits U(23) and P(24)
949 const MachineOperand &MO = MI.getOperand(OpIdx++);
950 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
954 Binary |= 0x1 << ARMII::W_BitShift;
957 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
958 const MachineOperand &MO = MI.getOperand(i);
959 if (!MO.isReg() || MO.isImplicit())
961 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
962 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
964 Binary |= 0x1 << RegNum;
970 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
971 const TargetInstrDesc &TID = MI.getDesc();
973 // Part of binary is determined by TableGn.
974 unsigned Binary = getBinaryCodeForInstr(MI);
976 // Set the conditional execution predicate
977 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
979 // Encode S bit if MI modifies CPSR.
980 Binary |= getAddrModeSBit(MI, TID);
982 // 32x32->64bit operations have two destination registers. The number
983 // of register definitions will tell us if that's what we're dealing with.
985 if (TID.getNumDefs() == 2)
986 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
989 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
992 Binary |= getMachineOpValue(MI, OpIdx++);
995 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
997 // Many multiple instructions (e.g. MLA) have three src operands. Encode
998 // it as Rn (for multiply, that's in the same offset as RdLo.
999 if (TID.getNumOperands() > OpIdx &&
1000 !TID.OpInfo[OpIdx].isPredicate() &&
1001 !TID.OpInfo[OpIdx].isOptionalDef())
1002 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1007 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1008 const TargetInstrDesc &TID = MI.getDesc();
1010 // Part of binary is determined by TableGn.
1011 unsigned Binary = getBinaryCodeForInstr(MI);
1013 // Set the conditional execution predicate
1014 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1019 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1021 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1022 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1024 // Two register operand form.
1026 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1029 Binary |= getMachineOpValue(MI, MO2);
1032 Binary |= getMachineOpValue(MI, MO1);
1035 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1036 if (MI.getOperand(OpIdx).isImm() &&
1037 !TID.OpInfo[OpIdx].isPredicate() &&
1038 !TID.OpInfo[OpIdx].isOptionalDef())
1039 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1044 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1045 const TargetInstrDesc &TID = MI.getDesc();
1047 // Part of binary is determined by TableGn.
1048 unsigned Binary = getBinaryCodeForInstr(MI);
1050 // Set the conditional execution predicate
1051 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1056 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1058 const MachineOperand &MO = MI.getOperand(OpIdx++);
1059 if (OpIdx == TID.getNumOperands() ||
1060 TID.OpInfo[OpIdx].isPredicate() ||
1061 TID.OpInfo[OpIdx].isOptionalDef()) {
1062 // Encode Rm and it's done.
1063 Binary |= getMachineOpValue(MI, MO);
1069 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1072 Binary |= getMachineOpValue(MI, OpIdx++);
1074 // Encode shift_imm.
1075 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1076 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1077 Binary |= ShiftAmt << ARMII::ShiftShift;
1082 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1083 const TargetInstrDesc &TID = MI.getDesc();
1085 if (TID.Opcode == ARM::TPsoft) {
1086 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1089 // Part of binary is determined by TableGn.
1090 unsigned Binary = getBinaryCodeForInstr(MI);
1092 // Set the conditional execution predicate
1093 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1095 // Set signed_immed_24 field
1096 Binary |= getMachineOpValue(MI, 0);
1101 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1102 // Remember the base address of the inline jump table.
1103 uintptr_t JTBase = MCE.getCurrentPCValue();
1104 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1105 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1108 // Now emit the jump table entries.
1109 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1110 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1112 // DestBB address - JT base.
1113 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1115 // Absolute DestBB address.
1116 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1121 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1122 const TargetInstrDesc &TID = MI.getDesc();
1124 // Handle jump tables.
1125 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1126 // First emit a ldr pc, [] instruction.
1127 emitDataProcessingInstruction(MI, ARM::PC);
1129 // Then emit the inline jump table.
1131 (TID.Opcode == ARM::BR_JTr)
1132 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1133 emitInlineJumpTable(JTIndex);
1135 } else if (TID.Opcode == ARM::BR_JTm) {
1136 // First emit a ldr pc, [] instruction.
1137 emitLoadStoreInstruction(MI, ARM::PC);
1139 // Then emit the inline jump table.
1140 emitInlineJumpTable(MI.getOperand(3).getIndex());
1144 // Part of binary is determined by TableGn.
1145 unsigned Binary = getBinaryCodeForInstr(MI);
1147 // Set the conditional execution predicate
1148 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1150 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1151 // The return register is LR.
1152 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1154 // otherwise, set the return register
1155 Binary |= getMachineOpValue(MI, 0);
1160 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1161 unsigned RegD = MI.getOperand(OpIdx).getReg();
1162 unsigned Binary = 0;
1163 bool isSPVFP = false;
1164 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1166 Binary |= RegD << ARMII::RegRdShift;
1168 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1169 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1174 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1175 unsigned RegN = MI.getOperand(OpIdx).getReg();
1176 unsigned Binary = 0;
1177 bool isSPVFP = false;
1178 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1180 Binary |= RegN << ARMII::RegRnShift;
1182 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1183 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1188 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1189 unsigned RegM = MI.getOperand(OpIdx).getReg();
1190 unsigned Binary = 0;
1191 bool isSPVFP = false;
1192 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1196 Binary |= ((RegM & 0x1E) >> 1);
1197 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1202 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1203 const TargetInstrDesc &TID = MI.getDesc();
1205 // Part of binary is determined by TableGn.
1206 unsigned Binary = getBinaryCodeForInstr(MI);
1208 // Set the conditional execution predicate
1209 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1212 assert((Binary & ARMII::D_BitShift) == 0 &&
1213 (Binary & ARMII::N_BitShift) == 0 &&
1214 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1217 Binary |= encodeVFPRd(MI, OpIdx++);
1219 // If this is a two-address operand, skip it, e.g. FMACD.
1220 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1224 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1225 Binary |= encodeVFPRn(MI, OpIdx++);
1227 if (OpIdx == TID.getNumOperands() ||
1228 TID.OpInfo[OpIdx].isPredicate() ||
1229 TID.OpInfo[OpIdx].isOptionalDef()) {
1230 // FCMPEZD etc. has only one operand.
1236 Binary |= encodeVFPRm(MI, OpIdx);
1241 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1242 const TargetInstrDesc &TID = MI.getDesc();
1243 unsigned Form = TID.TSFlags & ARMII::FormMask;
1245 // Part of binary is determined by TableGn.
1246 unsigned Binary = getBinaryCodeForInstr(MI);
1248 // Set the conditional execution predicate
1249 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1253 case ARMII::VFPConv1Frm:
1254 case ARMII::VFPConv2Frm:
1255 case ARMII::VFPConv3Frm:
1257 Binary |= encodeVFPRd(MI, 0);
1259 case ARMII::VFPConv4Frm:
1261 Binary |= encodeVFPRn(MI, 0);
1263 case ARMII::VFPConv5Frm:
1265 Binary |= encodeVFPRm(MI, 0);
1271 case ARMII::VFPConv1Frm:
1273 Binary |= encodeVFPRm(MI, 1);
1275 case ARMII::VFPConv2Frm:
1276 case ARMII::VFPConv3Frm:
1278 Binary |= encodeVFPRn(MI, 1);
1280 case ARMII::VFPConv4Frm:
1281 case ARMII::VFPConv5Frm:
1283 Binary |= encodeVFPRd(MI, 1);
1287 if (Form == ARMII::VFPConv5Frm)
1289 Binary |= encodeVFPRn(MI, 2);
1290 else if (Form == ARMII::VFPConv3Frm)
1292 Binary |= encodeVFPRm(MI, 2);
1297 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1298 // Part of binary is determined by TableGn.
1299 unsigned Binary = getBinaryCodeForInstr(MI);
1301 // Set the conditional execution predicate
1302 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1307 Binary |= encodeVFPRd(MI, OpIdx++);
1309 // Encode address base.
1310 const MachineOperand &Base = MI.getOperand(OpIdx++);
1311 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1313 // If there is a non-zero immediate offset, encode it.
1315 const MachineOperand &Offset = MI.getOperand(OpIdx);
1316 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1317 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1318 Binary |= 1 << ARMII::U_BitShift;
1325 // If immediate offset is omitted, default to +0.
1326 Binary |= 1 << ARMII::U_BitShift;
1332 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1333 const TargetInstrDesc &TID = MI.getDesc();
1334 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1336 // Part of binary is determined by TableGn.
1337 unsigned Binary = getBinaryCodeForInstr(MI);
1339 // Set the conditional execution predicate
1340 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1342 // Skip operand 0 of an instruction with base register update.
1347 // Set base address operand
1348 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1350 // Set addressing mode by modifying bits U(23) and P(24)
1351 const MachineOperand &MO = MI.getOperand(OpIdx++);
1352 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1356 Binary |= 0x1 << ARMII::W_BitShift;
1358 // First register is encoded in Dd.
1359 Binary |= encodeVFPRd(MI, OpIdx+2);
1361 // Number of registers are encoded in offset field.
1362 unsigned NumRegs = 1;
1363 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1364 const MachineOperand &MO = MI.getOperand(i);
1365 if (!MO.isReg() || MO.isImplicit())
1369 Binary |= NumRegs * 2;
1374 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1375 // Part of binary is determined by TableGn.
1376 unsigned Binary = getBinaryCodeForInstr(MI);
1378 // Set the conditional execution predicate
1379 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1384 #include "ARMGenCodeEmitter.inc"