1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-emitter"
17 #include "ARMAddressingModes.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "llvm/Function.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/CodeGen/MachineCodeEmitter.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
34 STATISTIC(NumEmitted, "Number of machine instructions emitted");
37 class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
39 const ARMInstrInfo *II;
42 MachineCodeEmitter &MCE;
43 const MachineConstantPool *MCP;
46 explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
47 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
49 ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
50 const ARMInstrInfo &ii, const TargetData &td)
51 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
54 bool runOnMachineFunction(MachineFunction &MF);
56 virtual const char *getPassName() const {
57 return "ARM Machine Code Emitter";
60 void emitInstruction(const MachineInstr &MI);
64 void emitConstPoolInstruction(const MachineInstr &MI);
66 void emitPseudoInstruction(const MachineInstr &MI);
68 unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
69 const TargetInstrDesc &TID,
72 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
73 const TargetInstrDesc &TID,
76 unsigned getAddrMode1SBit(const MachineInstr &MI,
77 const TargetInstrDesc &TID) const;
79 unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
80 const TargetInstrDesc &TID,
82 unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
83 const TargetInstrDesc &TID,
85 unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
86 const TargetInstrDesc &TID,
88 unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
89 const TargetInstrDesc &TID,
92 /// getInstrBinary - Return binary encoding for the specified
93 /// machine instruction.
94 unsigned getInstrBinary(const MachineInstr &MI);
96 /// getBinaryCodeForInstr - This function, generated by the
97 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
98 /// machine instructions.
100 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
102 /// getMachineOpValue - Return binary encoding of operand. If the machine
103 /// operand requires relocation, record the relocation and return zero.
104 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
105 return getMachineOpValue(MI, MI.getOperand(OpIdx));
107 unsigned getMachineOpValue(const MachineInstr &MI,
108 const MachineOperand &MO);
110 /// getBaseOpcodeFor - Return the opcode value.
112 unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
113 return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
116 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
118 unsigned getShiftOp(const MachineOperand &MO) const ;
120 /// Routines that handle operands which add machine relocations which are
121 /// fixed up by the JIT fixup stage.
122 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
124 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
125 void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
126 int Disp = 0, unsigned PCAdj = 0 );
127 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
129 void emitGlobalConstant(const Constant *CV);
130 void emitMachineBasicBlock(MachineBasicBlock *BB);
132 char ARMCodeEmitter::ID = 0;
135 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
136 /// to the specified MCE object.
137 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
138 MachineCodeEmitter &MCE) {
139 return new ARMCodeEmitter(TM, MCE);
142 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
143 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
144 MF.getTarget().getRelocationModel() != Reloc::Static) &&
145 "JIT relocation model must be set to static or default!");
146 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
147 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
148 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
149 MCP = MF.getConstantPool();
152 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
153 MCE.startFunction(MF);
154 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
156 MCE.StartMachineBasicBlock(MBB);
157 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
161 } while (MCE.finishFunction(MF));
166 /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
168 unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
169 switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
170 default: assert(0 && "Unknown shift opc!");
171 case ARM_AM::asr: return 2;
172 case ARM_AM::lsl: return 0;
173 case ARM_AM::lsr: return 1;
175 case ARM_AM::rrx: return 3;
180 /// getMachineOpValue - Return binary encoding of operand. If the machine
181 /// operand requires relocation, record the relocation and return zero.
182 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
183 const MachineOperand &MO) {
185 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
187 return static_cast<unsigned>(MO.getImm());
188 else if (MO.isGlobal())
189 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
190 else if (MO.isSymbol())
191 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
193 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
195 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
197 emitMachineBasicBlock(MO.getMBB());
199 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
205 /// emitGlobalAddress - Emit the specified address to the code stream.
207 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
208 unsigned Reloc, bool NeedStub) {
209 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
210 Reloc, GV, 0, NeedStub));
213 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
214 /// be emitted to the current location in the function, and allow it to be PC
216 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
217 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
221 /// emitConstPoolAddress - Arrange for the address of an constant pool
222 /// to be emitted to the current location in the function, and allow it to be PC
224 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
226 unsigned PCAdj /* = 0 */) {
227 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
231 /// emitJumpTableAddress - Arrange for the address of a jump table to
232 /// be emitted to the current location in the function, and allow it to be PC
234 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
235 unsigned PCAdj /* = 0 */) {
236 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
237 Reloc, JTIndex, PCAdj));
240 /// emitMachineBasicBlock - Emit the specified address basic block.
241 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
242 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
243 ARM::reloc_arm_branch, BB));
246 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
249 NumEmitted++; // Keep track of the # of mi's emitted
250 if ((MI.getDesc().TSFlags & ARMII::FormMask) == ARMII::Pseudo)
251 emitPseudoInstruction(MI);
253 MCE.emitWordLE(getInstrBinary(MI));
256 unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
257 const TargetInstrDesc &TID,
259 // FIXME: Assume CC is AL for now.
260 Binary |= ARMCC::AL << 28;
262 switch (TID.TSFlags & ARMII::FormMask) {
264 assert(0 && "Unknown instruction subtype!");
266 case ARMII::Branch: {
267 // Set signed_immed_24 field
268 Binary |= getMachineOpValue(MI, 0);
270 // if it is a conditional branch, set cond field
271 if (TID.Opcode == ARM::Bcc) {
272 Binary &= 0x0FFFFFFF; // clear conditional field
273 Binary |= getMachineOpValue(MI, 1) << 28; // set conditional field
277 case ARMII::BranchMisc: {
278 if (TID.Opcode == ARM::BX)
280 if (TID.Opcode == ARM::BX_RET)
281 Binary |= 0xe; // the return register is LR
283 // otherwise, set the return register
284 Binary |= getMachineOpValue(MI, 0);
292 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
293 const TargetInstrDesc &TID,
295 // Set last operand (register Rm)
296 unsigned Binary = getMachineOpValue(MI, OpIdx);
298 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
299 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
300 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
302 // Encode the shift opcode.
304 unsigned Rs = MO1.getReg();
306 // Set shift operand (bit[7:4]).
311 // RRX - 0110 and bit[11:8] clear.
313 default: assert(0 && "Unknown shift opc!");
314 case ARM_AM::lsl: SBits = 0x1; break;
315 case ARM_AM::lsr: SBits = 0x3; break;
316 case ARM_AM::asr: SBits = 0x5; break;
317 case ARM_AM::ror: SBits = 0x7; break;
318 case ARM_AM::rrx: SBits = 0x6; break;
321 // Set shift operand (bit[6:4]).
327 default: assert(0 && "Unknown shift opc!");
328 case ARM_AM::lsl: SBits = 0x0; break;
329 case ARM_AM::lsr: SBits = 0x2; break;
330 case ARM_AM::asr: SBits = 0x4; break;
331 case ARM_AM::ror: SBits = 0x6; break;
334 Binary |= SBits << 4;
335 if (SOpc == ARM_AM::rrx)
338 // Encode the shift operation Rs or shift_imm (except rrx).
340 // Encode Rs bit[11:8].
341 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
343 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
346 // Encode shift_imm bit[11:7].
347 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
350 unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
351 const TargetInstrDesc &TID) const {
352 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
353 const MachineOperand &MO = MI.getOperand(i-1);
354 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
355 return 1 << ARMII::S_BitShift;
360 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
364 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
365 unsigned Opcode = MI.getDesc().Opcode;
369 case ARM::CONSTPOOL_ENTRY: {
370 emitConstPoolInstruction(MI);
376 unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
377 const TargetInstrDesc &TID,
379 // FIXME: Assume CC is AL for now.
380 Binary |= ARMCC::AL << 28;
382 // Encode S bit if MI modifies CPSR.
383 Binary |= getAddrMode1SBit(MI, TID);
385 // Encode register def if there is one.
386 unsigned NumDefs = TID.getNumDefs();
389 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
393 // Encode first non-shifter register operand if there is one.
394 unsigned Format = TID.TSFlags & ARMII::FormMask;
395 bool isUnary = (Format == ARMII::DPRdMisc ||
396 Format == ARMII::DPRdIm ||
397 Format == ARMII::DPRdReg ||
398 Format == ARMII::DPRdSoReg ||
399 Format == ARMII::DPRnIm ||
400 Format == ARMII::DPRnReg ||
401 Format == ARMII::DPRnSoReg);
403 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
407 // Encode shifter operand.
408 bool HasSoReg = (Format == ARMII::DPRdSoReg ||
409 Format == ARMII::DPRnSoReg ||
410 Format == ARMII::DPRSoReg ||
411 Format == ARMII::DPRSoRegS);
414 return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
416 const MachineOperand &MO = MI.getOperand(OpIdx);
418 // Encode register Rm.
419 return Binary | getMachineOpValue(MI, NumDefs + 1);
422 // Set bit I(25) to identify this is the immediate form of <shifter_op>
423 Binary |= 1 << ARMII::I_BitShift;
424 unsigned SoImm = MO.getImm();
425 // Encode rotate_imm.
426 Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
428 Binary |= ARM_AM::getSOImmVal(SoImm);
432 unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
433 const TargetInstrDesc &TID,
435 // FIXME: Assume CC is AL for now.
436 Binary |= ARMCC::AL << 28;
439 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
441 // Set second operand
442 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
444 const MachineOperand &MO2 = MI.getOperand(2);
445 const MachineOperand &MO3 = MI.getOperand(3);
447 // Set bit U(23) according to sign of immed value (positive or negative).
448 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
450 if (!MO2.getReg()) { // is immediate
451 if (ARM_AM::getAM2Offset(MO3.getImm()))
452 // Set the value of offset_12 field
453 Binary |= ARM_AM::getAM2Offset(MO3.getImm());
457 // Set bit I(25), because this is not in immediate enconding.
458 Binary |= 1 << ARMII::I_BitShift;
459 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
460 // Set bit[3:0] to the corresponding Rm register
461 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
463 // if this instr is in scaled register offset/index instruction, set
464 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
465 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
466 Binary |= getShiftOp(MO3) << 5; // shift
467 Binary |= ShImm << 7; // shift_immed
473 unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
474 const TargetInstrDesc &TID,
476 // FIXME: Assume CC is AL for now.
477 Binary |= ARMCC::AL << 28;
480 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
482 // Set second operand
483 Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
485 const MachineOperand &MO2 = MI.getOperand(2);
486 const MachineOperand &MO3 = MI.getOperand(3);
488 // Set bit U(23) according to sign of immed value (positive or negative)
489 Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
492 // If this instr is in register offset/index encoding, set bit[3:0]
493 // to the corresponding Rm register.
495 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
499 // if this instr is in immediate offset/index encoding, set bit 22 to 1
500 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
503 Binary |= (ImmOffs >> 4) << 8; // immedH
504 Binary |= (ImmOffs & ~0xF); // immedL
510 unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
511 const TargetInstrDesc &TID,
513 // FIXME: Assume CC is AL for now.
514 Binary |= ARMCC::AL << 28;
517 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
519 // Set addressing mode by modifying bits U(23) and P(24)
520 // IA - Increment after - bit U = 1 and bit P = 0
521 // IB - Increment before - bit U = 1 and bit P = 1
522 // DA - Decrement after - bit U = 0 and bit P = 0
523 // DB - Decrement before - bit U = 0 and bit P = 1
524 const MachineOperand &MO = MI.getOperand(1);
525 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
527 default: assert(0 && "Unknown addressing sub-mode!");
528 case ARM_AM::da: break;
529 case ARM_AM::db: Binary |= 0x1 << 24; break;
530 case ARM_AM::ia: Binary |= 0x1 << 23; break;
531 case ARM_AM::ib: Binary |= 0x3 << 23; break;
535 if (ARM_AM::getAM4WBFlag(MO.getImm()))
539 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
540 const MachineOperand &MO = MI.getOperand(i);
541 if (MO.isReg() && MO.isImplicit())
543 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
544 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
546 Binary |= 0x1 << RegNum;
552 /// getInstrBinary - Return binary encoding for the specified
553 /// machine instruction.
554 unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
555 // Part of binary is determined by TableGn.
556 unsigned Binary = getBinaryCodeForInstr(MI);
558 const TargetInstrDesc &TID = MI.getDesc();
559 switch (TID.TSFlags & ARMII::AddrModeMask) {
560 case ARMII::AddrModeNone:
561 return getAddrModeNoneInstrBinary(MI, TID, Binary);
562 case ARMII::AddrMode1:
563 return getAddrMode1InstrBinary(MI, TID, Binary);
564 case ARMII::AddrMode2:
565 return getAddrMode2InstrBinary(MI, TID, Binary);
566 case ARMII::AddrMode3:
567 return getAddrMode3InstrBinary(MI, TID, Binary);
568 case ARMII::AddrMode4:
569 return getAddrMode4InstrBinary(MI, TID, Binary);
576 #include "ARMGenCodeEmitter.inc"