1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
59 void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<MachineModuleInfo>();
61 MachineFunctionPass::getAnalysisUsage(AU);
66 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
67 : MachineFunctionPass(&ID), JTI(0),
68 II((const ARMInstrInfo *)tm.getInstrInfo()),
69 TD(tm.getTargetData()), TM(tm),
70 MCE(mce), MCPEs(0), MJTEs(0),
71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73 /// getBinaryCodeForInstr - This function, generated by the
74 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75 /// machine instructions.
76 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78 bool runOnMachineFunction(MachineFunction &MF);
80 virtual const char *getPassName() const {
81 return "ARM Machine Code Emitter";
84 void emitInstruction(const MachineInstr &MI);
88 void emitWordLE(unsigned Binary);
89 void emitDWordLE(uint64_t Binary);
90 void emitConstPoolInstruction(const MachineInstr &MI);
91 void emitMOVi32immInstruction(const MachineInstr &MI);
92 void emitMOVi2piecesInstruction(const MachineInstr &MI);
93 void emitLEApcrelJTInstruction(const MachineInstr &MI);
94 void emitPseudoMoveInstruction(const MachineInstr &MI);
95 void addPCLabel(unsigned LabelID);
96 void emitPseudoInstruction(const MachineInstr &MI);
97 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
98 const TargetInstrDesc &TID,
99 const MachineOperand &MO,
102 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitBranchInstruction(const MachineInstr &MI);
128 void emitInlineJumpTable(unsigned JTIndex);
130 void emitMiscBranchInstruction(const MachineInstr &MI);
132 void emitVFPArithInstruction(const MachineInstr &MI);
134 void emitVFPConversionInstruction(const MachineInstr &MI);
136 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
140 void emitMiscInstruction(const MachineInstr &MI);
142 void emitNEONGetLaneInstruction(const MachineInstr &MI);
143 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
144 void emitNEON2RegInstruction(const MachineInstr &MI);
145 void emitNEON3RegInstruction(const MachineInstr &MI);
147 /// getMachineOpValue - Return binary encoding of operand. If the machine
148 /// operand requires relocation, record the relocation and return zero.
149 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
150 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
151 return getMachineOpValue(MI, MI.getOperand(OpIdx));
154 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
155 /// machine operand requires relocation, record the relocation and return
157 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
159 unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
161 return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166 unsigned getShiftOp(unsigned Imm) const ;
168 /// Routines that handle operands which add machine relocations which are
169 /// fixed up by the relocation stage.
170 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
171 bool MayNeedFarStub, bool Indirect,
173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177 intptr_t JTBase = 0);
181 char ARMCodeEmitter::ID = 0;
183 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
184 /// code to the specified MCE object.
185 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
186 JITCodeEmitter &JCE) {
187 return new ARMCodeEmitter(TM, JCE);
190 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
191 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
192 MF.getTarget().getRelocationModel() != Reloc::Static) &&
193 "JIT relocation model must be set to static or default!");
194 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
195 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
196 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
197 Subtarget = &TM.getSubtarget<ARMSubtarget>();
198 MCPEs = &MF.getConstantPool()->getConstants();
200 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202 JTI->Initialize(MF, IsPIC);
203 MMI = &getAnalysis<MachineModuleInfo>();
204 MCE.setModuleInfo(MMI);
207 DEBUG(errs() << "JITTing function '"
208 << MF.getFunction()->getName() << "'\n");
209 MCE.startFunction(MF);
210 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
212 MCE.StartMachineBasicBlock(MBB);
213 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
217 } while (MCE.finishFunction(MF));
222 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
224 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
225 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
226 default: llvm_unreachable("Unknown shift opc!");
227 case ARM_AM::asr: return 2;
228 case ARM_AM::lsl: return 0;
229 case ARM_AM::lsr: return 1;
231 case ARM_AM::rrx: return 3;
236 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
237 /// machine operand requires relocation, record the relocation and return zero.
238 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
239 const MachineOperand &MO,
241 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
242 && "Relocation to this function should be for movt or movw");
245 return static_cast<unsigned>(MO.getImm());
246 else if (MO.isGlobal())
247 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
248 else if (MO.isSymbol())
249 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
251 emitMachineBasicBlock(MO.getMBB(), Reloc);
256 llvm_unreachable("Unsupported operand type for movw/movt");
261 /// getMachineOpValue - Return binary encoding of operand. If the machine
262 /// operand requires relocation, record the relocation and return zero.
263 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
264 const MachineOperand &MO) {
266 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
268 return static_cast<unsigned>(MO.getImm());
269 else if (MO.isGlobal())
270 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
271 else if (MO.isSymbol())
272 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
273 else if (MO.isCPI()) {
274 const TargetInstrDesc &TID = MI.getDesc();
275 // For VFP load, the immediate offset is multiplied by 4.
276 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
277 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
278 emitConstPoolAddress(MO.getIndex(), Reloc);
279 } else if (MO.isJTI())
280 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
282 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
292 /// emitGlobalAddress - Emit the specified address to the code stream.
294 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
295 bool MayNeedFarStub, bool Indirect,
297 MachineRelocation MR = Indirect
298 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
299 const_cast<GlobalValue *>(GV),
300 ACPV, MayNeedFarStub)
301 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
302 const_cast<GlobalValue *>(GV), ACPV,
304 MCE.addRelocation(MR);
307 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
308 /// be emitted to the current location in the function, and allow it to be PC
310 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
311 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
315 /// emitConstPoolAddress - Arrange for the address of an constant pool
316 /// to be emitted to the current location in the function, and allow it to be PC
318 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
319 // Tell JIT emitter we'll resolve the address.
320 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
321 Reloc, CPI, 0, true));
324 /// emitJumpTableAddress - Arrange for the address of a jump table to
325 /// be emitted to the current location in the function, and allow it to be PC
327 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
328 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
329 Reloc, JTIndex, 0, true));
332 /// emitMachineBasicBlock - Emit the specified address basic block.
333 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
334 unsigned Reloc, intptr_t JTBase) {
335 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
339 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
340 DEBUG(errs() << " 0x";
341 errs().write_hex(Binary) << "\n");
342 MCE.emitWordLE(Binary);
345 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
346 DEBUG(errs() << " 0x";
347 errs().write_hex(Binary) << "\n");
348 MCE.emitDWordLE(Binary);
351 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
352 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
354 MCE.processDebugLoc(MI.getDebugLoc(), true);
356 ++NumEmitted; // Keep track of the # of mi's emitted
357 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
359 llvm_unreachable("Unhandled instruction encoding format!");
363 emitPseudoInstruction(MI);
366 case ARMII::DPSoRegFrm:
367 emitDataProcessingInstruction(MI);
371 emitLoadStoreInstruction(MI);
373 case ARMII::LdMiscFrm:
374 case ARMII::StMiscFrm:
375 emitMiscLoadStoreInstruction(MI);
377 case ARMII::LdStMulFrm:
378 emitLoadStoreMultipleInstruction(MI);
381 emitMulFrmInstruction(MI);
384 emitExtendInstruction(MI);
386 case ARMII::ArithMiscFrm:
387 emitMiscArithInstruction(MI);
390 emitBranchInstruction(MI);
392 case ARMII::BrMiscFrm:
393 emitMiscBranchInstruction(MI);
396 case ARMII::VFPUnaryFrm:
397 case ARMII::VFPBinaryFrm:
398 emitVFPArithInstruction(MI);
400 case ARMII::VFPConv1Frm:
401 case ARMII::VFPConv2Frm:
402 case ARMII::VFPConv3Frm:
403 case ARMII::VFPConv4Frm:
404 case ARMII::VFPConv5Frm:
405 emitVFPConversionInstruction(MI);
407 case ARMII::VFPLdStFrm:
408 emitVFPLoadStoreInstruction(MI);
410 case ARMII::VFPLdStMulFrm:
411 emitVFPLoadStoreMultipleInstruction(MI);
413 case ARMII::VFPMiscFrm:
414 emitMiscInstruction(MI);
416 // NEON instructions.
417 case ARMII::NGetLnFrm:
418 emitNEONGetLaneInstruction(MI);
420 case ARMII::N1RegModImmFrm:
421 emitNEON1RegModImmInstruction(MI);
423 case ARMII::N2RegFrm:
424 emitNEON2RegInstruction(MI);
426 case ARMII::N3RegFrm:
427 emitNEON3RegInstruction(MI);
430 MCE.processDebugLoc(MI.getDebugLoc(), false);
433 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
434 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
435 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
436 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
438 // Remember the CONSTPOOL_ENTRY address for later relocation.
439 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
441 // Emit constpool island entry. In most cases, the actual values will be
442 // resolved and relocated after code emission.
443 if (MCPE.isMachineConstantPoolEntry()) {
444 ARMConstantPoolValue *ACPV =
445 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
447 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
448 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
450 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
451 const GlobalValue *GV = ACPV->getGV();
453 Reloc::Model RelocM = TM.getRelocationModel();
454 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
456 Subtarget->GVIsIndirectSymbol(GV, RelocM),
459 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
463 const Constant *CV = MCPE.Val.ConstVal;
466 errs() << " ** Constant pool #" << CPI << " @ "
467 << (void*)MCE.getCurrentPCValue() << " ";
468 if (const Function *F = dyn_cast<Function>(CV))
469 errs() << F->getName();
475 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
476 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
478 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
479 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
481 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
482 if (CFP->getType()->isFloatTy())
483 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
484 else if (CFP->getType()->isDoubleTy())
485 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
487 llvm_unreachable("Unable to handle this constantpool entry!");
490 llvm_unreachable("Unable to handle this constantpool entry!");
495 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
496 const MachineOperand &MO0 = MI.getOperand(0);
497 const MachineOperand &MO1 = MI.getOperand(1);
499 // Emit the 'movw' instruction.
500 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
502 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
504 // Set the conditional execution predicate.
505 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
508 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
510 // Encode imm16 as imm4:imm12
511 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
512 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
515 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
516 // Emit the 'movt' instruction.
517 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
519 // Set the conditional execution predicate.
520 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
523 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
525 // Encode imm16 as imm4:imm1, same as movw above.
526 Binary |= Hi16 & 0xFFF;
527 Binary |= ((Hi16 >> 12) & 0xF) << 16;
531 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
532 const MachineOperand &MO0 = MI.getOperand(0);
533 const MachineOperand &MO1 = MI.getOperand(1);
534 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
535 "Not a valid so_imm value!");
536 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
537 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
539 // Emit the 'mov' instruction.
540 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
542 // Set the conditional execution predicate.
543 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
546 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
549 // Set bit I(25) to identify this is the immediate form of <shifter_op>
550 Binary |= 1 << ARMII::I_BitShift;
551 Binary |= getMachineSoImmOpValue(V1);
554 // Now the 'orr' instruction.
555 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
557 // Set the conditional execution predicate.
558 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
561 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
564 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
567 // Set bit I(25) to identify this is the immediate form of <shifter_op>
568 Binary |= 1 << ARMII::I_BitShift;
569 Binary |= getMachineSoImmOpValue(V2);
573 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
574 // It's basically add r, pc, (LJTI - $+8)
576 const TargetInstrDesc &TID = MI.getDesc();
578 // Emit the 'add' instruction.
579 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
581 // Set the conditional execution predicate
582 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
584 // Encode S bit if MI modifies CPSR.
585 Binary |= getAddrModeSBit(MI, TID);
588 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
590 // Encode Rn which is PC.
591 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
593 // Encode the displacement.
594 Binary |= 1 << ARMII::I_BitShift;
595 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
600 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
601 unsigned Opcode = MI.getDesc().Opcode;
603 // Part of binary is determined by TableGn.
604 unsigned Binary = getBinaryCodeForInstr(MI);
606 // Set the conditional execution predicate
607 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
609 // Encode S bit if MI modifies CPSR.
610 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
611 Binary |= 1 << ARMII::S_BitShift;
613 // Encode register def if there is one.
614 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
616 // Encode the shift operation.
623 case ARM::MOVsrl_flag:
625 Binary |= (0x2 << 4) | (1 << 7);
627 case ARM::MOVsra_flag:
629 Binary |= (0x4 << 4) | (1 << 7);
633 // Encode register Rm.
634 Binary |= getMachineOpValue(MI, 1);
639 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
640 DEBUG(errs() << " ** LPC" << LabelID << " @ "
641 << (void*)MCE.getCurrentPCValue() << '\n');
642 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
645 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
646 unsigned Opcode = MI.getDesc().Opcode;
649 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
650 case TargetOpcode::INLINEASM: {
651 // We allow inline assembler nodes with empty bodies - they can
652 // implicitly define registers, which is ok for JIT.
653 if (MI.getOperand(0).getSymbolName()[0]) {
654 report_fatal_error("JIT does not support inline asm!");
658 case TargetOpcode::DBG_LABEL:
659 case TargetOpcode::EH_LABEL:
660 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
662 case TargetOpcode::IMPLICIT_DEF:
663 case TargetOpcode::KILL:
666 case ARM::CONSTPOOL_ENTRY:
667 emitConstPoolInstruction(MI);
670 // Remember of the address of the PC label for relocation later.
671 addPCLabel(MI.getOperand(2).getImm());
672 // PICADD is just an add instruction that implicitly read pc.
673 emitDataProcessingInstruction(MI, 0, ARM::PC);
680 // Remember of the address of the PC label for relocation later.
681 addPCLabel(MI.getOperand(2).getImm());
682 // These are just load / store instructions that implicitly read pc.
683 emitLoadStoreInstruction(MI, 0, ARM::PC);
690 // Remember of the address of the PC label for relocation later.
691 addPCLabel(MI.getOperand(2).getImm());
692 // These are just load / store instructions that implicitly read pc.
693 emitMiscLoadStoreInstruction(MI, ARM::PC);
698 emitMOVi32immInstruction(MI);
701 case ARM::MOVi2pieces:
702 // Two instructions to materialize a constant.
703 emitMOVi2piecesInstruction(MI);
705 case ARM::LEApcrelJT:
706 // Materialize jumptable address.
707 emitLEApcrelJTInstruction(MI);
710 case ARM::MOVsrl_flag:
711 case ARM::MOVsra_flag:
712 emitPseudoMoveInstruction(MI);
717 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
718 const TargetInstrDesc &TID,
719 const MachineOperand &MO,
721 unsigned Binary = getMachineOpValue(MI, MO);
723 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
724 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
725 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
727 // Encode the shift opcode.
729 unsigned Rs = MO1.getReg();
731 // Set shift operand (bit[7:4]).
736 // RRX - 0110 and bit[11:8] clear.
738 default: llvm_unreachable("Unknown shift opc!");
739 case ARM_AM::lsl: SBits = 0x1; break;
740 case ARM_AM::lsr: SBits = 0x3; break;
741 case ARM_AM::asr: SBits = 0x5; break;
742 case ARM_AM::ror: SBits = 0x7; break;
743 case ARM_AM::rrx: SBits = 0x6; break;
746 // Set shift operand (bit[6:4]).
752 default: llvm_unreachable("Unknown shift opc!");
753 case ARM_AM::lsl: SBits = 0x0; break;
754 case ARM_AM::lsr: SBits = 0x2; break;
755 case ARM_AM::asr: SBits = 0x4; break;
756 case ARM_AM::ror: SBits = 0x6; break;
759 Binary |= SBits << 4;
760 if (SOpc == ARM_AM::rrx)
763 // Encode the shift operation Rs or shift_imm (except rrx).
765 // Encode Rs bit[11:8].
766 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
768 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
771 // Encode shift_imm bit[11:7].
772 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
775 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
776 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
777 assert(SoImmVal != -1 && "Not a valid so_imm value!");
779 // Encode rotate_imm.
780 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
781 << ARMII::SoRotImmShift;
784 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
788 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
789 const TargetInstrDesc &TID) const {
790 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
791 const MachineOperand &MO = MI.getOperand(i-1);
792 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
793 return 1 << ARMII::S_BitShift;
798 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
800 unsigned ImplicitRn) {
801 const TargetInstrDesc &TID = MI.getDesc();
803 // Part of binary is determined by TableGn.
804 unsigned Binary = getBinaryCodeForInstr(MI);
806 // Set the conditional execution predicate
807 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
809 // Encode S bit if MI modifies CPSR.
810 Binary |= getAddrModeSBit(MI, TID);
812 // Encode register def if there is one.
813 unsigned NumDefs = TID.getNumDefs();
816 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
818 // Special handling for implicit use (e.g. PC).
819 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
820 << ARMII::RegRdShift);
822 if (TID.Opcode == ARM::MOVi16) {
823 // Get immediate from MI.
824 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
825 ARM::reloc_arm_movw);
826 // Encode imm which is the same as in emitMOVi32immInstruction().
827 Binary |= Lo16 & 0xFFF;
828 Binary |= ((Lo16 >> 12) & 0xF) << 16;
831 } else if(TID.Opcode == ARM::MOVTi16) {
832 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
833 ARM::reloc_arm_movt) >> 16);
834 Binary |= Hi16 & 0xFFF;
835 Binary |= ((Hi16 >> 12) & 0xF) << 16;
838 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
839 uint32_t v = ~MI.getOperand(2).getImm();
840 int32_t lsb = CountTrailingZeros_32(v);
841 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
842 // Instr{20-16} = msb, Instr{11-7} = lsb
843 Binary |= (msb & 0x1F) << 16;
844 Binary |= (lsb & 0x1F) << 7;
847 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
848 // Encode Rn in Instr{0-3}
849 Binary |= getMachineOpValue(MI, OpIdx++);
851 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
852 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
854 // Instr{20-16} = widthm1, Instr{11-7} = lsb
855 Binary |= (widthm1 & 0x1F) << 16;
856 Binary |= (lsb & 0x1F) << 7;
861 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
862 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
865 // Encode first non-shifter register operand if there is one.
866 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
869 // Special handling for implicit use (e.g. PC).
870 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
871 << ARMII::RegRnShift);
873 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
878 // Encode shifter operand.
879 const MachineOperand &MO = MI.getOperand(OpIdx);
880 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
882 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
887 // Encode register Rm.
888 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
893 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
898 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
900 unsigned ImplicitRn) {
901 const TargetInstrDesc &TID = MI.getDesc();
902 unsigned Form = TID.TSFlags & ARMII::FormMask;
903 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
905 // Part of binary is determined by TableGn.
906 unsigned Binary = getBinaryCodeForInstr(MI);
908 // Set the conditional execution predicate
909 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
913 // Operand 0 of a pre- and post-indexed store is the address base
914 // writeback. Skip it.
915 bool Skipped = false;
916 if (IsPrePost && Form == ARMII::StFrm) {
923 // Special handling for implicit use (e.g. PC).
924 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
925 << ARMII::RegRdShift);
927 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
929 // Set second operand
931 // Special handling for implicit use (e.g. PC).
932 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
933 << ARMII::RegRnShift);
935 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
937 // If this is a two-address operand, skip it. e.g. LDR_PRE.
938 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
941 const MachineOperand &MO2 = MI.getOperand(OpIdx);
942 unsigned AM2Opc = (ImplicitRn == ARM::PC)
943 ? 0 : MI.getOperand(OpIdx+1).getImm();
945 // Set bit U(23) according to sign of immed value (positive or negative).
946 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
948 if (!MO2.getReg()) { // is immediate
949 if (ARM_AM::getAM2Offset(AM2Opc))
950 // Set the value of offset_12 field
951 Binary |= ARM_AM::getAM2Offset(AM2Opc);
956 // Set bit I(25), because this is not in immediate enconding.
957 Binary |= 1 << ARMII::I_BitShift;
958 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
959 // Set bit[3:0] to the corresponding Rm register
960 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
962 // If this instr is in scaled register offset/index instruction, set
963 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
964 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
965 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
966 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
972 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
973 unsigned ImplicitRn) {
974 const TargetInstrDesc &TID = MI.getDesc();
975 unsigned Form = TID.TSFlags & ARMII::FormMask;
976 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
978 // Part of binary is determined by TableGn.
979 unsigned Binary = getBinaryCodeForInstr(MI);
981 // Set the conditional execution predicate
982 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
986 // Operand 0 of a pre- and post-indexed store is the address base
987 // writeback. Skip it.
988 bool Skipped = false;
989 if (IsPrePost && Form == ARMII::StMiscFrm) {
995 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
997 // Skip LDRD and STRD's second operand.
998 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1001 // Set second operand
1003 // Special handling for implicit use (e.g. PC).
1004 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1005 << ARMII::RegRnShift);
1007 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1009 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1010 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1013 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1014 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1015 ? 0 : MI.getOperand(OpIdx+1).getImm();
1017 // Set bit U(23) according to sign of immed value (positive or negative)
1018 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1021 // If this instr is in register offset/index encoding, set bit[3:0]
1022 // to the corresponding Rm register.
1024 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1029 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1030 Binary |= 1 << ARMII::AM3_I_BitShift;
1031 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1033 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1034 Binary |= (ImmOffs & 0xF); // immedL
1040 static unsigned getAddrModeUPBits(unsigned Mode) {
1041 unsigned Binary = 0;
1043 // Set addressing mode by modifying bits U(23) and P(24)
1044 // IA - Increment after - bit U = 1 and bit P = 0
1045 // IB - Increment before - bit U = 1 and bit P = 1
1046 // DA - Decrement after - bit U = 0 and bit P = 0
1047 // DB - Decrement before - bit U = 0 and bit P = 1
1049 default: llvm_unreachable("Unknown addressing sub-mode!");
1050 case ARM_AM::da: break;
1051 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1052 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1053 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1059 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1060 const TargetInstrDesc &TID = MI.getDesc();
1061 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1063 // Part of binary is determined by TableGn.
1064 unsigned Binary = getBinaryCodeForInstr(MI);
1066 // Set the conditional execution predicate
1067 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1069 // Skip operand 0 of an instruction with base register update.
1074 // Set base address operand
1075 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1077 // Set addressing mode by modifying bits U(23) and P(24)
1078 const MachineOperand &MO = MI.getOperand(OpIdx++);
1079 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1083 Binary |= 0x1 << ARMII::W_BitShift;
1086 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1087 const MachineOperand &MO = MI.getOperand(i);
1088 if (!MO.isReg() || MO.isImplicit())
1090 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1091 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1093 Binary |= 0x1 << RegNum;
1099 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1100 const TargetInstrDesc &TID = MI.getDesc();
1102 // Part of binary is determined by TableGn.
1103 unsigned Binary = getBinaryCodeForInstr(MI);
1105 // Set the conditional execution predicate
1106 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1108 // Encode S bit if MI modifies CPSR.
1109 Binary |= getAddrModeSBit(MI, TID);
1111 // 32x32->64bit operations have two destination registers. The number
1112 // of register definitions will tell us if that's what we're dealing with.
1114 if (TID.getNumDefs() == 2)
1115 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1118 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1121 Binary |= getMachineOpValue(MI, OpIdx++);
1124 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1126 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1127 // it as Rn (for multiply, that's in the same offset as RdLo.
1128 if (TID.getNumOperands() > OpIdx &&
1129 !TID.OpInfo[OpIdx].isPredicate() &&
1130 !TID.OpInfo[OpIdx].isOptionalDef())
1131 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1136 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1137 const TargetInstrDesc &TID = MI.getDesc();
1139 // Part of binary is determined by TableGn.
1140 unsigned Binary = getBinaryCodeForInstr(MI);
1142 // Set the conditional execution predicate
1143 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1148 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1150 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1151 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1153 // Two register operand form.
1155 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1158 Binary |= getMachineOpValue(MI, MO2);
1161 Binary |= getMachineOpValue(MI, MO1);
1164 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1165 if (MI.getOperand(OpIdx).isImm() &&
1166 !TID.OpInfo[OpIdx].isPredicate() &&
1167 !TID.OpInfo[OpIdx].isOptionalDef())
1168 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1173 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1174 const TargetInstrDesc &TID = MI.getDesc();
1176 // Part of binary is determined by TableGn.
1177 unsigned Binary = getBinaryCodeForInstr(MI);
1179 // Set the conditional execution predicate
1180 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1185 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1187 const MachineOperand &MO = MI.getOperand(OpIdx++);
1188 if (OpIdx == TID.getNumOperands() ||
1189 TID.OpInfo[OpIdx].isPredicate() ||
1190 TID.OpInfo[OpIdx].isOptionalDef()) {
1191 // Encode Rm and it's done.
1192 Binary |= getMachineOpValue(MI, MO);
1198 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1201 Binary |= getMachineOpValue(MI, OpIdx++);
1203 // Encode shift_imm.
1204 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1205 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1206 Binary |= ShiftAmt << ARMII::ShiftShift;
1211 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1212 const TargetInstrDesc &TID = MI.getDesc();
1214 if (TID.Opcode == ARM::TPsoft) {
1215 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1218 // Part of binary is determined by TableGn.
1219 unsigned Binary = getBinaryCodeForInstr(MI);
1221 // Set the conditional execution predicate
1222 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1224 // Set signed_immed_24 field
1225 Binary |= getMachineOpValue(MI, 0);
1230 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1231 // Remember the base address of the inline jump table.
1232 uintptr_t JTBase = MCE.getCurrentPCValue();
1233 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1234 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1237 // Now emit the jump table entries.
1238 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1239 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1241 // DestBB address - JT base.
1242 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1244 // Absolute DestBB address.
1245 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1250 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1251 const TargetInstrDesc &TID = MI.getDesc();
1253 // Handle jump tables.
1254 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1255 // First emit a ldr pc, [] instruction.
1256 emitDataProcessingInstruction(MI, ARM::PC);
1258 // Then emit the inline jump table.
1260 (TID.Opcode == ARM::BR_JTr)
1261 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1262 emitInlineJumpTable(JTIndex);
1264 } else if (TID.Opcode == ARM::BR_JTm) {
1265 // First emit a ldr pc, [] instruction.
1266 emitLoadStoreInstruction(MI, ARM::PC);
1268 // Then emit the inline jump table.
1269 emitInlineJumpTable(MI.getOperand(3).getIndex());
1273 // Part of binary is determined by TableGn.
1274 unsigned Binary = getBinaryCodeForInstr(MI);
1276 // Set the conditional execution predicate
1277 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1279 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1280 // The return register is LR.
1281 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1283 // otherwise, set the return register
1284 Binary |= getMachineOpValue(MI, 0);
1289 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1290 unsigned RegD = MI.getOperand(OpIdx).getReg();
1291 unsigned Binary = 0;
1292 bool isSPVFP = false;
1293 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1295 Binary |= RegD << ARMII::RegRdShift;
1297 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1298 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1303 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1304 unsigned RegN = MI.getOperand(OpIdx).getReg();
1305 unsigned Binary = 0;
1306 bool isSPVFP = false;
1307 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1309 Binary |= RegN << ARMII::RegRnShift;
1311 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1312 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1317 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1318 unsigned RegM = MI.getOperand(OpIdx).getReg();
1319 unsigned Binary = 0;
1320 bool isSPVFP = false;
1321 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1325 Binary |= ((RegM & 0x1E) >> 1);
1326 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1331 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1332 const TargetInstrDesc &TID = MI.getDesc();
1334 // Part of binary is determined by TableGn.
1335 unsigned Binary = getBinaryCodeForInstr(MI);
1337 // Set the conditional execution predicate
1338 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1341 assert((Binary & ARMII::D_BitShift) == 0 &&
1342 (Binary & ARMII::N_BitShift) == 0 &&
1343 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1346 Binary |= encodeVFPRd(MI, OpIdx++);
1348 // If this is a two-address operand, skip it, e.g. FMACD.
1349 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1353 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1354 Binary |= encodeVFPRn(MI, OpIdx++);
1356 if (OpIdx == TID.getNumOperands() ||
1357 TID.OpInfo[OpIdx].isPredicate() ||
1358 TID.OpInfo[OpIdx].isOptionalDef()) {
1359 // FCMPEZD etc. has only one operand.
1365 Binary |= encodeVFPRm(MI, OpIdx);
1370 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1371 const TargetInstrDesc &TID = MI.getDesc();
1372 unsigned Form = TID.TSFlags & ARMII::FormMask;
1374 // Part of binary is determined by TableGn.
1375 unsigned Binary = getBinaryCodeForInstr(MI);
1377 // Set the conditional execution predicate
1378 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1382 case ARMII::VFPConv1Frm:
1383 case ARMII::VFPConv2Frm:
1384 case ARMII::VFPConv3Frm:
1386 Binary |= encodeVFPRd(MI, 0);
1388 case ARMII::VFPConv4Frm:
1390 Binary |= encodeVFPRn(MI, 0);
1392 case ARMII::VFPConv5Frm:
1394 Binary |= encodeVFPRm(MI, 0);
1400 case ARMII::VFPConv1Frm:
1402 Binary |= encodeVFPRm(MI, 1);
1404 case ARMII::VFPConv2Frm:
1405 case ARMII::VFPConv3Frm:
1407 Binary |= encodeVFPRn(MI, 1);
1409 case ARMII::VFPConv4Frm:
1410 case ARMII::VFPConv5Frm:
1412 Binary |= encodeVFPRd(MI, 1);
1416 if (Form == ARMII::VFPConv5Frm)
1418 Binary |= encodeVFPRn(MI, 2);
1419 else if (Form == ARMII::VFPConv3Frm)
1421 Binary |= encodeVFPRm(MI, 2);
1426 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1427 // Part of binary is determined by TableGn.
1428 unsigned Binary = getBinaryCodeForInstr(MI);
1430 // Set the conditional execution predicate
1431 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1436 Binary |= encodeVFPRd(MI, OpIdx++);
1438 // Encode address base.
1439 const MachineOperand &Base = MI.getOperand(OpIdx++);
1440 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1442 // If there is a non-zero immediate offset, encode it.
1444 const MachineOperand &Offset = MI.getOperand(OpIdx);
1445 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1446 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1447 Binary |= 1 << ARMII::U_BitShift;
1454 // If immediate offset is omitted, default to +0.
1455 Binary |= 1 << ARMII::U_BitShift;
1461 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1462 const TargetInstrDesc &TID = MI.getDesc();
1463 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1465 // Part of binary is determined by TableGn.
1466 unsigned Binary = getBinaryCodeForInstr(MI);
1468 // Set the conditional execution predicate
1469 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1471 // Skip operand 0 of an instruction with base register update.
1476 // Set base address operand
1477 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1479 // Set addressing mode by modifying bits U(23) and P(24)
1480 const MachineOperand &MO = MI.getOperand(OpIdx++);
1481 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1485 Binary |= 0x1 << ARMII::W_BitShift;
1487 // First register is encoded in Dd.
1488 Binary |= encodeVFPRd(MI, OpIdx+2);
1490 // Number of registers are encoded in offset field.
1491 unsigned NumRegs = 1;
1492 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1493 const MachineOperand &MO = MI.getOperand(i);
1494 if (!MO.isReg() || MO.isImplicit())
1498 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1499 // Otherwise, it will be 0, in the case of 32-bit registers.
1501 Binary |= NumRegs * 2;
1508 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1509 unsigned Opcode = MI.getDesc().Opcode;
1510 // Part of binary is determined by TableGn.
1511 unsigned Binary = getBinaryCodeForInstr(MI);
1513 // Set the conditional execution predicate
1514 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1518 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1521 // No further encoding needed.
1526 const MachineOperand &MO0 = MI.getOperand(0);
1528 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1529 << ARMII::RegRdShift;
1534 case ARM::FCONSTS: {
1536 Binary |= encodeVFPRd(MI, 0);
1538 // Encode imm., Table A7-18 VFP modified immediate constants
1539 const MachineOperand &MO1 = MI.getOperand(1);
1540 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1541 .bitcastToAPInt().getHiBits(32).getLimitedValue());
1542 unsigned ModifiedImm;
1544 if(Opcode == ARM::FCONSTS)
1545 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1546 (Imm & 0x03F80000) >> 19; // bcdefgh
1547 else // Opcode == ARM::FCONSTD
1548 ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1549 (Imm & 0x007F0000) >> 16; // bcdefgh
1551 // Insts{19-16} = abcd, Insts{3-0} = efgh
1552 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1553 Binary |= (ModifiedImm & 0xF);
1561 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1562 unsigned RegD = MI.getOperand(OpIdx).getReg();
1563 unsigned Binary = 0;
1564 RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1565 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1566 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1570 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1571 unsigned RegN = MI.getOperand(OpIdx).getReg();
1572 unsigned Binary = 0;
1573 RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1574 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1575 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1579 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1580 unsigned RegM = MI.getOperand(OpIdx).getReg();
1581 unsigned Binary = 0;
1582 RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1583 Binary |= (RegM & 0xf);
1584 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1588 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1589 /// data-processing instruction to the corresponding Thumb encoding.
1590 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1591 assert((Binary & 0xfe000000) == 0xf2000000 &&
1592 "not an ARM NEON data-processing instruction");
1593 unsigned UBit = (Binary >> 24) & 1;
1594 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1597 void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
1598 unsigned Binary = getBinaryCodeForInstr(MI);
1600 // Set the conditional execution predicate
1601 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1603 unsigned RegT = MI.getOperand(0).getReg();
1604 RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1605 Binary |= (RegT << ARMII::RegRdShift);
1606 Binary |= encodeNEONRn(MI, 1);
1609 if ((Binary & (1 << 22)) != 0)
1610 LaneShift = 0; // 8-bit elements
1611 else if ((Binary & (1 << 5)) != 0)
1612 LaneShift = 1; // 16-bit elements
1614 LaneShift = 2; // 32-bit elements
1616 unsigned Lane = MI.getOperand(2).getImm() << LaneShift;
1617 unsigned Opc1 = Lane >> 2;
1618 unsigned Opc2 = Lane & 3;
1619 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1620 Binary |= (Opc1 << 21);
1621 Binary |= (Opc2 << 5);
1626 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1627 unsigned Binary = getBinaryCodeForInstr(MI);
1628 // Destination register is encoded in Dd.
1629 Binary |= encodeNEONRd(MI, 0);
1630 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1631 unsigned Imm = MI.getOperand(1).getImm();
1632 unsigned Op = (Imm >> 12) & 1;
1633 unsigned Cmode = (Imm >> 8) & 0xf;
1634 unsigned I = (Imm >> 7) & 1;
1635 unsigned Imm3 = (Imm >> 4) & 0x7;
1636 unsigned Imm4 = Imm & 0xf;
1637 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1638 if (Subtarget->isThumb())
1639 Binary = convertNEONDataProcToThumb(Binary);
1643 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1644 const TargetInstrDesc &TID = MI.getDesc();
1645 unsigned Binary = getBinaryCodeForInstr(MI);
1646 // Destination register is encoded in Dd; source register in Dm.
1648 Binary |= encodeNEONRd(MI, OpIdx++);
1649 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1651 Binary |= encodeNEONRm(MI, OpIdx);
1652 if (Subtarget->isThumb())
1653 Binary = convertNEONDataProcToThumb(Binary);
1654 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1658 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1659 const TargetInstrDesc &TID = MI.getDesc();
1660 unsigned Binary = getBinaryCodeForInstr(MI);
1661 // Destination register is encoded in Dd; source registers in Dn and Dm.
1663 Binary |= encodeNEONRd(MI, OpIdx++);
1664 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1666 Binary |= encodeNEONRn(MI, OpIdx++);
1667 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1669 Binary |= encodeNEONRm(MI, OpIdx);
1670 if (Subtarget->isThumb())
1671 Binary = convertNEONDataProcToThumb(Binary);
1672 // FIXME: This does not handle VMOVDneon or VMOVQ.
1676 #include "ARMGenCodeEmitter.inc"