1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
105 unsigned getAddrModeSBit(const MachineInstr &MI,
106 const TargetInstrDesc &TID) const;
108 void emitDataProcessingInstruction(const MachineInstr &MI,
109 unsigned ImplicitRd = 0,
110 unsigned ImplicitRn = 0);
112 void emitLoadStoreInstruction(const MachineInstr &MI,
113 unsigned ImplicitRd = 0,
114 unsigned ImplicitRn = 0);
116 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117 unsigned ImplicitRn = 0);
119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121 void emitMulFrmInstruction(const MachineInstr &MI);
123 void emitExtendInstruction(const MachineInstr &MI);
125 void emitMiscArithInstruction(const MachineInstr &MI);
127 void emitSaturateInstruction(const MachineInstr &MI);
129 void emitBranchInstruction(const MachineInstr &MI);
131 void emitInlineJumpTable(unsigned JTIndex);
133 void emitMiscBranchInstruction(const MachineInstr &MI);
135 void emitVFPArithInstruction(const MachineInstr &MI);
137 void emitVFPConversionInstruction(const MachineInstr &MI);
139 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143 void emitNEONLaneInstruction(const MachineInstr &MI);
144 void emitNEONDupInstruction(const MachineInstr &MI);
145 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146 void emitNEON2RegInstruction(const MachineInstr &MI);
147 void emitNEON3RegInstruction(const MachineInstr &MI);
149 /// getMachineOpValue - Return binary encoding of operand. If the machine
150 /// operand requires relocation, record the relocation and return zero.
151 unsigned getMachineOpValue(const MachineInstr &MI,
152 const MachineOperand &MO) const;
153 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
154 return getMachineOpValue(MI, MI.getOperand(OpIdx));
157 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
158 // TableGen'erated getBinaryCodeForInstr() function to encode any
159 // operand values, instead querying getMachineOpValue() directly for
160 // each operand it needs to encode. Thus, any of the new encoder
161 // helper functions can simply return 0 as the values the return
162 // are already handled elsewhere. They are placeholders to allow this
163 // encoder to continue to function until the MC encoder is sufficiently
164 // far along that this one can be eliminated entirely.
165 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
167 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
169 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
171 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
173 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
175 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
176 unsigned Op) const { return 0; }
177 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
180 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
181 /// machine operand requires relocation, record the relocation and return
183 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
186 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
188 unsigned getShiftOp(unsigned Imm) const ;
190 /// Routines that handle operands which add machine relocations which are
191 /// fixed up by the relocation stage.
192 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
193 bool MayNeedFarStub, bool Indirect,
194 intptr_t ACPV = 0) const;
195 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
196 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
197 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
198 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
199 intptr_t JTBase = 0) const;
203 char ARMCodeEmitter::ID = 0;
205 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
206 /// code to the specified MCE object.
207 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
208 JITCodeEmitter &JCE) {
209 return new ARMCodeEmitter(TM, JCE);
212 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
213 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
214 MF.getTarget().getRelocationModel() != Reloc::Static) &&
215 "JIT relocation model must be set to static or default!");
216 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
217 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
218 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
219 Subtarget = &TM.getSubtarget<ARMSubtarget>();
220 MCPEs = &MF.getConstantPool()->getConstants();
222 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
223 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
224 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
225 JTI->Initialize(MF, IsPIC);
226 MMI = &getAnalysis<MachineModuleInfo>();
227 MCE.setModuleInfo(MMI);
230 DEBUG(errs() << "JITTing function '"
231 << MF.getFunction()->getName() << "'\n");
232 MCE.startFunction(MF);
233 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
235 MCE.StartMachineBasicBlock(MBB);
236 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
240 } while (MCE.finishFunction(MF));
245 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
247 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
248 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
249 default: llvm_unreachable("Unknown shift opc!");
250 case ARM_AM::asr: return 2;
251 case ARM_AM::lsl: return 0;
252 case ARM_AM::lsr: return 1;
254 case ARM_AM::rrx: return 3;
259 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
260 /// machine operand requires relocation, record the relocation and return zero.
261 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
262 const MachineOperand &MO,
264 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
265 && "Relocation to this function should be for movt or movw");
268 return static_cast<unsigned>(MO.getImm());
269 else if (MO.isGlobal())
270 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
271 else if (MO.isSymbol())
272 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
274 emitMachineBasicBlock(MO.getMBB(), Reloc);
279 llvm_unreachable("Unsupported operand type for movw/movt");
284 /// getMachineOpValue - Return binary encoding of operand. If the machine
285 /// operand requires relocation, record the relocation and return zero.
286 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
287 const MachineOperand &MO) const {
289 return getARMRegisterNumbering(MO.getReg());
291 return static_cast<unsigned>(MO.getImm());
292 else if (MO.isGlobal())
293 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
294 else if (MO.isSymbol())
295 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
296 else if (MO.isCPI()) {
297 const TargetInstrDesc &TID = MI.getDesc();
298 // For VFP load, the immediate offset is multiplied by 4.
299 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
300 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
301 emitConstPoolAddress(MO.getIndex(), Reloc);
302 } else if (MO.isJTI())
303 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
305 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
315 /// emitGlobalAddress - Emit the specified address to the code stream.
317 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
318 bool MayNeedFarStub, bool Indirect,
319 intptr_t ACPV) const {
320 MachineRelocation MR = Indirect
321 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
322 const_cast<GlobalValue *>(GV),
323 ACPV, MayNeedFarStub)
324 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
325 const_cast<GlobalValue *>(GV), ACPV,
327 MCE.addRelocation(MR);
330 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
331 /// be emitted to the current location in the function, and allow it to be PC
333 void ARMCodeEmitter::
334 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
335 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
339 /// emitConstPoolAddress - Arrange for the address of an constant pool
340 /// to be emitted to the current location in the function, and allow it to be PC
342 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
343 // Tell JIT emitter we'll resolve the address.
344 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
345 Reloc, CPI, 0, true));
348 /// emitJumpTableAddress - Arrange for the address of a jump table to
349 /// be emitted to the current location in the function, and allow it to be PC
351 void ARMCodeEmitter::
352 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
353 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
354 Reloc, JTIndex, 0, true));
357 /// emitMachineBasicBlock - Emit the specified address basic block.
358 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
360 intptr_t JTBase) const {
361 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
365 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
366 DEBUG(errs() << " 0x";
367 errs().write_hex(Binary) << "\n");
368 MCE.emitWordLE(Binary);
371 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
372 DEBUG(errs() << " 0x";
373 errs().write_hex(Binary) << "\n");
374 MCE.emitDWordLE(Binary);
377 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
378 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
380 MCE.processDebugLoc(MI.getDebugLoc(), true);
382 ++NumEmitted; // Keep track of the # of mi's emitted
383 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
385 llvm_unreachable("Unhandled instruction encoding format!");
389 emitPseudoInstruction(MI);
392 case ARMII::DPSoRegFrm:
393 emitDataProcessingInstruction(MI);
397 emitLoadStoreInstruction(MI);
399 case ARMII::LdMiscFrm:
400 case ARMII::StMiscFrm:
401 emitMiscLoadStoreInstruction(MI);
403 case ARMII::LdStMulFrm:
404 emitLoadStoreMultipleInstruction(MI);
407 emitMulFrmInstruction(MI);
410 emitExtendInstruction(MI);
412 case ARMII::ArithMiscFrm:
413 emitMiscArithInstruction(MI);
416 emitSaturateInstruction(MI);
419 emitBranchInstruction(MI);
421 case ARMII::BrMiscFrm:
422 emitMiscBranchInstruction(MI);
425 case ARMII::VFPUnaryFrm:
426 case ARMII::VFPBinaryFrm:
427 emitVFPArithInstruction(MI);
429 case ARMII::VFPConv1Frm:
430 case ARMII::VFPConv2Frm:
431 case ARMII::VFPConv3Frm:
432 case ARMII::VFPConv4Frm:
433 case ARMII::VFPConv5Frm:
434 emitVFPConversionInstruction(MI);
436 case ARMII::VFPLdStFrm:
437 emitVFPLoadStoreInstruction(MI);
439 case ARMII::VFPLdStMulFrm:
440 emitVFPLoadStoreMultipleInstruction(MI);
443 // NEON instructions.
444 case ARMII::NGetLnFrm:
445 case ARMII::NSetLnFrm:
446 emitNEONLaneInstruction(MI);
449 emitNEONDupInstruction(MI);
451 case ARMII::N1RegModImmFrm:
452 emitNEON1RegModImmInstruction(MI);
454 case ARMII::N2RegFrm:
455 emitNEON2RegInstruction(MI);
457 case ARMII::N3RegFrm:
458 emitNEON3RegInstruction(MI);
461 MCE.processDebugLoc(MI.getDebugLoc(), false);
464 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
465 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
466 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
467 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
469 // Remember the CONSTPOOL_ENTRY address for later relocation.
470 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
472 // Emit constpool island entry. In most cases, the actual values will be
473 // resolved and relocated after code emission.
474 if (MCPE.isMachineConstantPoolEntry()) {
475 ARMConstantPoolValue *ACPV =
476 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
478 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
479 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
481 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
482 const GlobalValue *GV = ACPV->getGV();
484 Reloc::Model RelocM = TM.getRelocationModel();
485 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
487 Subtarget->GVIsIndirectSymbol(GV, RelocM),
490 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
494 const Constant *CV = MCPE.Val.ConstVal;
497 errs() << " ** Constant pool #" << CPI << " @ "
498 << (void*)MCE.getCurrentPCValue() << " ";
499 if (const Function *F = dyn_cast<Function>(CV))
500 errs() << F->getName();
506 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
507 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
509 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
510 uint32_t Val = uint32_t(*CI->getValue().getRawData());
512 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
513 if (CFP->getType()->isFloatTy())
514 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
515 else if (CFP->getType()->isDoubleTy())
516 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
518 llvm_unreachable("Unable to handle this constantpool entry!");
521 llvm_unreachable("Unable to handle this constantpool entry!");
526 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
527 const MachineOperand &MO0 = MI.getOperand(0);
528 const MachineOperand &MO1 = MI.getOperand(1);
530 // Emit the 'movw' instruction.
531 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
533 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
535 // Set the conditional execution predicate.
536 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
539 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
541 // Encode imm16 as imm4:imm12
542 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
543 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
546 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
547 // Emit the 'movt' instruction.
548 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
550 // Set the conditional execution predicate.
551 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
554 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
556 // Encode imm16 as imm4:imm1, same as movw above.
557 Binary |= Hi16 & 0xFFF;
558 Binary |= ((Hi16 >> 12) & 0xF) << 16;
562 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
563 const MachineOperand &MO0 = MI.getOperand(0);
564 const MachineOperand &MO1 = MI.getOperand(1);
565 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
566 "Not a valid so_imm value!");
567 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
568 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
570 // Emit the 'mov' instruction.
571 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
573 // Set the conditional execution predicate.
574 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
577 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
580 // Set bit I(25) to identify this is the immediate form of <shifter_op>
581 Binary |= 1 << ARMII::I_BitShift;
582 Binary |= getMachineSoImmOpValue(V1);
585 // Now the 'orr' instruction.
586 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
588 // Set the conditional execution predicate.
589 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
592 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
595 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
598 // Set bit I(25) to identify this is the immediate form of <shifter_op>
599 Binary |= 1 << ARMII::I_BitShift;
600 Binary |= getMachineSoImmOpValue(V2);
604 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
605 // It's basically add r, pc, (LJTI - $+8)
607 const TargetInstrDesc &TID = MI.getDesc();
609 // Emit the 'add' instruction.
610 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
612 // Set the conditional execution predicate
613 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
615 // Encode S bit if MI modifies CPSR.
616 Binary |= getAddrModeSBit(MI, TID);
619 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
621 // Encode Rn which is PC.
622 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
624 // Encode the displacement.
625 Binary |= 1 << ARMII::I_BitShift;
626 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
631 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
632 unsigned Opcode = MI.getDesc().Opcode;
634 // Part of binary is determined by TableGn.
635 unsigned Binary = getBinaryCodeForInstr(MI);
637 // Set the conditional execution predicate
638 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
640 // Encode S bit if MI modifies CPSR.
641 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
642 Binary |= 1 << ARMII::S_BitShift;
644 // Encode register def if there is one.
645 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
647 // Encode the shift operation.
654 case ARM::MOVsrl_flag:
656 Binary |= (0x2 << 4) | (1 << 7);
658 case ARM::MOVsra_flag:
660 Binary |= (0x4 << 4) | (1 << 7);
664 // Encode register Rm.
665 Binary |= getMachineOpValue(MI, 1);
670 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
671 DEBUG(errs() << " ** LPC" << LabelID << " @ "
672 << (void*)MCE.getCurrentPCValue() << '\n');
673 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
676 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
677 unsigned Opcode = MI.getDesc().Opcode;
680 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
684 case ARM::BMOVPCRXr9: {
685 // First emit mov lr, pc
686 unsigned Binary = 0x01a0e00f;
687 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
690 // and then emit the branch.
691 emitMiscBranchInstruction(MI);
694 case TargetOpcode::INLINEASM: {
695 // We allow inline assembler nodes with empty bodies - they can
696 // implicitly define registers, which is ok for JIT.
697 if (MI.getOperand(0).getSymbolName()[0]) {
698 report_fatal_error("JIT does not support inline asm!");
702 case TargetOpcode::PROLOG_LABEL:
703 case TargetOpcode::EH_LABEL:
704 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
706 case TargetOpcode::IMPLICIT_DEF:
707 case TargetOpcode::KILL:
710 case ARM::CONSTPOOL_ENTRY:
711 emitConstPoolInstruction(MI);
714 // Remember of the address of the PC label for relocation later.
715 addPCLabel(MI.getOperand(2).getImm());
716 // PICADD is just an add instruction that implicitly read pc.
717 emitDataProcessingInstruction(MI, 0, ARM::PC);
724 // Remember of the address of the PC label for relocation later.
725 addPCLabel(MI.getOperand(2).getImm());
726 // These are just load / store instructions that implicitly read pc.
727 emitLoadStoreInstruction(MI, 0, ARM::PC);
734 // Remember of the address of the PC label for relocation later.
735 addPCLabel(MI.getOperand(2).getImm());
736 // These are just load / store instructions that implicitly read pc.
737 emitMiscLoadStoreInstruction(MI, ARM::PC);
742 emitMOVi32immInstruction(MI);
745 case ARM::MOVi2pieces:
746 // Two instructions to materialize a constant.
747 emitMOVi2piecesInstruction(MI);
749 case ARM::LEApcrelJT:
750 // Materialize jumptable address.
751 emitLEApcrelJTInstruction(MI);
754 case ARM::MOVsrl_flag:
755 case ARM::MOVsra_flag:
756 emitPseudoMoveInstruction(MI);
761 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
762 const TargetInstrDesc &TID,
763 const MachineOperand &MO,
765 unsigned Binary = getMachineOpValue(MI, MO);
767 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
768 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
769 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
771 // Encode the shift opcode.
773 unsigned Rs = MO1.getReg();
775 // Set shift operand (bit[7:4]).
780 // RRX - 0110 and bit[11:8] clear.
782 default: llvm_unreachable("Unknown shift opc!");
783 case ARM_AM::lsl: SBits = 0x1; break;
784 case ARM_AM::lsr: SBits = 0x3; break;
785 case ARM_AM::asr: SBits = 0x5; break;
786 case ARM_AM::ror: SBits = 0x7; break;
787 case ARM_AM::rrx: SBits = 0x6; break;
790 // Set shift operand (bit[6:4]).
796 default: llvm_unreachable("Unknown shift opc!");
797 case ARM_AM::lsl: SBits = 0x0; break;
798 case ARM_AM::lsr: SBits = 0x2; break;
799 case ARM_AM::asr: SBits = 0x4; break;
800 case ARM_AM::ror: SBits = 0x6; break;
803 Binary |= SBits << 4;
804 if (SOpc == ARM_AM::rrx)
807 // Encode the shift operation Rs or shift_imm (except rrx).
809 // Encode Rs bit[11:8].
810 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
811 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
814 // Encode shift_imm bit[11:7].
815 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
818 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
819 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
820 assert(SoImmVal != -1 && "Not a valid so_imm value!");
822 // Encode rotate_imm.
823 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
824 << ARMII::SoRotImmShift;
827 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
831 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
832 const TargetInstrDesc &TID) const {
833 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
834 const MachineOperand &MO = MI.getOperand(i-1);
835 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
836 return 1 << ARMII::S_BitShift;
841 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
843 unsigned ImplicitRn) {
844 const TargetInstrDesc &TID = MI.getDesc();
846 // Part of binary is determined by TableGn.
847 unsigned Binary = getBinaryCodeForInstr(MI);
849 // Set the conditional execution predicate
850 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
852 // Encode S bit if MI modifies CPSR.
853 Binary |= getAddrModeSBit(MI, TID);
855 // Encode register def if there is one.
856 unsigned NumDefs = TID.getNumDefs();
859 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
861 // Special handling for implicit use (e.g. PC).
862 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
864 if (TID.Opcode == ARM::MOVi16) {
865 // Get immediate from MI.
866 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
867 ARM::reloc_arm_movw);
868 // Encode imm which is the same as in emitMOVi32immInstruction().
869 Binary |= Lo16 & 0xFFF;
870 Binary |= ((Lo16 >> 12) & 0xF) << 16;
873 } else if(TID.Opcode == ARM::MOVTi16) {
874 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
875 ARM::reloc_arm_movt) >> 16);
876 Binary |= Hi16 & 0xFFF;
877 Binary |= ((Hi16 >> 12) & 0xF) << 16;
880 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
881 uint32_t v = ~MI.getOperand(2).getImm();
882 int32_t lsb = CountTrailingZeros_32(v);
883 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
884 // Instr{20-16} = msb, Instr{11-7} = lsb
885 Binary |= (msb & 0x1F) << 16;
886 Binary |= (lsb & 0x1F) << 7;
889 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
890 // Encode Rn in Instr{0-3}
891 Binary |= getMachineOpValue(MI, OpIdx++);
893 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
894 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
896 // Instr{20-16} = widthm1, Instr{11-7} = lsb
897 Binary |= (widthm1 & 0x1F) << 16;
898 Binary |= (lsb & 0x1F) << 7;
903 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
904 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
907 // Encode first non-shifter register operand if there is one.
908 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
911 // Special handling for implicit use (e.g. PC).
912 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
914 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
919 // Encode shifter operand.
920 const MachineOperand &MO = MI.getOperand(OpIdx);
921 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
923 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
928 // Encode register Rm.
929 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
934 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
939 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
941 unsigned ImplicitRn) {
942 const TargetInstrDesc &TID = MI.getDesc();
943 unsigned Form = TID.TSFlags & ARMII::FormMask;
944 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
946 // Part of binary is determined by TableGn.
947 unsigned Binary = getBinaryCodeForInstr(MI);
949 // If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
950 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
951 || MI.getOpcode() == ARM::LDRcp) {
956 // Set the conditional execution predicate
957 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
961 // Operand 0 of a pre- and post-indexed store is the address base
962 // writeback. Skip it.
963 bool Skipped = false;
964 if (IsPrePost && Form == ARMII::StFrm) {
971 // Special handling for implicit use (e.g. PC).
972 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
974 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
976 // Set second operand
978 // Special handling for implicit use (e.g. PC).
979 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
981 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
983 // If this is a two-address operand, skip it. e.g. LDR_PRE.
984 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
987 const MachineOperand &MO2 = MI.getOperand(OpIdx);
988 unsigned AM2Opc = (ImplicitRn == ARM::PC)
989 ? 0 : MI.getOperand(OpIdx+1).getImm();
991 // Set bit U(23) according to sign of immed value (positive or negative).
992 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
994 if (!MO2.getReg()) { // is immediate
995 if (ARM_AM::getAM2Offset(AM2Opc))
996 // Set the value of offset_12 field
997 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1002 // Set bit I(25), because this is not in immediate encoding.
1003 Binary |= 1 << ARMII::I_BitShift;
1004 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1005 // Set bit[3:0] to the corresponding Rm register
1006 Binary |= getARMRegisterNumbering(MO2.getReg());
1008 // If this instr is in scaled register offset/index instruction, set
1009 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1010 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1011 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1012 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1018 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1019 unsigned ImplicitRn) {
1020 const TargetInstrDesc &TID = MI.getDesc();
1021 unsigned Form = TID.TSFlags & ARMII::FormMask;
1022 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1024 // Part of binary is determined by TableGn.
1025 unsigned Binary = getBinaryCodeForInstr(MI);
1027 // Set the conditional execution predicate
1028 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1032 // Operand 0 of a pre- and post-indexed store is the address base
1033 // writeback. Skip it.
1034 bool Skipped = false;
1035 if (IsPrePost && Form == ARMII::StMiscFrm) {
1040 // Set first operand
1041 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1043 // Skip LDRD and STRD's second operand.
1044 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1047 // Set second operand
1049 // Special handling for implicit use (e.g. PC).
1050 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1052 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1054 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1055 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1058 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1059 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1060 ? 0 : MI.getOperand(OpIdx+1).getImm();
1062 // Set bit U(23) according to sign of immed value (positive or negative)
1063 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1066 // If this instr is in register offset/index encoding, set bit[3:0]
1067 // to the corresponding Rm register.
1069 Binary |= getARMRegisterNumbering(MO2.getReg());
1074 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1075 Binary |= 1 << ARMII::AM3_I_BitShift;
1076 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1078 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1079 Binary |= (ImmOffs & 0xF); // immedL
1085 static unsigned getAddrModeUPBits(unsigned Mode) {
1086 unsigned Binary = 0;
1088 // Set addressing mode by modifying bits U(23) and P(24)
1089 // IA - Increment after - bit U = 1 and bit P = 0
1090 // IB - Increment before - bit U = 1 and bit P = 1
1091 // DA - Decrement after - bit U = 0 and bit P = 0
1092 // DB - Decrement before - bit U = 0 and bit P = 1
1094 default: llvm_unreachable("Unknown addressing sub-mode!");
1095 case ARM_AM::da: break;
1096 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1097 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1098 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1104 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1105 const TargetInstrDesc &TID = MI.getDesc();
1106 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1108 // Part of binary is determined by TableGn.
1109 unsigned Binary = getBinaryCodeForInstr(MI);
1111 // Set the conditional execution predicate
1112 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1114 // Skip operand 0 of an instruction with base register update.
1119 // Set base address operand
1120 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1122 // Set addressing mode by modifying bits U(23) and P(24)
1123 const MachineOperand &MO = MI.getOperand(OpIdx++);
1124 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1128 Binary |= 0x1 << ARMII::W_BitShift;
1131 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1132 const MachineOperand &MO = MI.getOperand(i);
1133 if (!MO.isReg() || MO.isImplicit())
1135 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1136 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1138 Binary |= 0x1 << RegNum;
1144 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1145 const TargetInstrDesc &TID = MI.getDesc();
1147 // Part of binary is determined by TableGn.
1148 unsigned Binary = getBinaryCodeForInstr(MI);
1150 // Set the conditional execution predicate
1151 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1153 // Encode S bit if MI modifies CPSR.
1154 Binary |= getAddrModeSBit(MI, TID);
1156 // 32x32->64bit operations have two destination registers. The number
1157 // of register definitions will tell us if that's what we're dealing with.
1159 if (TID.getNumDefs() == 2)
1160 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1163 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1166 Binary |= getMachineOpValue(MI, OpIdx++);
1169 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1171 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1172 // it as Rn (for multiply, that's in the same offset as RdLo.
1173 if (TID.getNumOperands() > OpIdx &&
1174 !TID.OpInfo[OpIdx].isPredicate() &&
1175 !TID.OpInfo[OpIdx].isOptionalDef())
1176 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1181 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1182 const TargetInstrDesc &TID = MI.getDesc();
1184 // Part of binary is determined by TableGn.
1185 unsigned Binary = getBinaryCodeForInstr(MI);
1187 // Set the conditional execution predicate
1188 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1193 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1195 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1196 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1198 // Two register operand form.
1200 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1203 Binary |= getMachineOpValue(MI, MO2);
1206 Binary |= getMachineOpValue(MI, MO1);
1209 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1210 if (MI.getOperand(OpIdx).isImm() &&
1211 !TID.OpInfo[OpIdx].isPredicate() &&
1212 !TID.OpInfo[OpIdx].isOptionalDef())
1213 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1218 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1219 const TargetInstrDesc &TID = MI.getDesc();
1221 // Part of binary is determined by TableGn.
1222 unsigned Binary = getBinaryCodeForInstr(MI);
1224 // Set the conditional execution predicate
1225 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1230 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1232 const MachineOperand &MO = MI.getOperand(OpIdx++);
1233 if (OpIdx == TID.getNumOperands() ||
1234 TID.OpInfo[OpIdx].isPredicate() ||
1235 TID.OpInfo[OpIdx].isOptionalDef()) {
1236 // Encode Rm and it's done.
1237 Binary |= getMachineOpValue(MI, MO);
1243 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1246 Binary |= getMachineOpValue(MI, OpIdx++);
1248 // Encode shift_imm.
1249 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1250 if (TID.Opcode == ARM::PKHTB) {
1251 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1255 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1256 Binary |= ShiftAmt << ARMII::ShiftShift;
1261 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1262 const TargetInstrDesc &TID = MI.getDesc();
1264 // Part of binary is determined by TableGen.
1265 unsigned Binary = getBinaryCodeForInstr(MI);
1267 // Set the conditional execution predicate
1268 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1271 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1273 // Encode saturate bit position.
1274 unsigned Pos = MI.getOperand(1).getImm();
1275 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1277 assert((Pos < 16 || (Pos < 32 &&
1278 TID.Opcode != ARM::SSAT16 &&
1279 TID.Opcode != ARM::USAT16)) &&
1280 "saturate bit position out of range");
1281 Binary |= Pos << 16;
1284 Binary |= getMachineOpValue(MI, 2);
1286 // Encode shift_imm.
1287 if (TID.getNumOperands() == 4) {
1288 unsigned ShiftOp = MI.getOperand(3).getImm();
1289 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1290 if (Opc == ARM_AM::asr)
1292 unsigned ShiftAmt = MI.getOperand(3).getImm();
1293 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1295 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1296 Binary |= ShiftAmt << ARMII::ShiftShift;
1302 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1303 const TargetInstrDesc &TID = MI.getDesc();
1305 if (TID.Opcode == ARM::TPsoft) {
1306 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1309 // Part of binary is determined by TableGn.
1310 unsigned Binary = getBinaryCodeForInstr(MI);
1312 // Set the conditional execution predicate
1313 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1315 // Set signed_immed_24 field
1316 Binary |= getMachineOpValue(MI, 0);
1321 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1322 // Remember the base address of the inline jump table.
1323 uintptr_t JTBase = MCE.getCurrentPCValue();
1324 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1325 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1328 // Now emit the jump table entries.
1329 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1330 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1332 // DestBB address - JT base.
1333 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1335 // Absolute DestBB address.
1336 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1341 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1342 const TargetInstrDesc &TID = MI.getDesc();
1344 // Handle jump tables.
1345 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1346 // First emit a ldr pc, [] instruction.
1347 emitDataProcessingInstruction(MI, ARM::PC);
1349 // Then emit the inline jump table.
1351 (TID.Opcode == ARM::BR_JTr)
1352 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1353 emitInlineJumpTable(JTIndex);
1355 } else if (TID.Opcode == ARM::BR_JTm) {
1356 // First emit a ldr pc, [] instruction.
1357 emitLoadStoreInstruction(MI, ARM::PC);
1359 // Then emit the inline jump table.
1360 emitInlineJumpTable(MI.getOperand(3).getIndex());
1364 // Part of binary is determined by TableGn.
1365 unsigned Binary = getBinaryCodeForInstr(MI);
1367 // Set the conditional execution predicate
1368 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1370 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1371 // The return register is LR.
1372 Binary |= getARMRegisterNumbering(ARM::LR);
1374 // otherwise, set the return register
1375 Binary |= getMachineOpValue(MI, 0);
1380 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1381 unsigned RegD = MI.getOperand(OpIdx).getReg();
1382 unsigned Binary = 0;
1383 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1384 RegD = getARMRegisterNumbering(RegD);
1386 Binary |= RegD << ARMII::RegRdShift;
1388 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1389 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1394 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1395 unsigned RegN = MI.getOperand(OpIdx).getReg();
1396 unsigned Binary = 0;
1397 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1398 RegN = getARMRegisterNumbering(RegN);
1400 Binary |= RegN << ARMII::RegRnShift;
1402 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1403 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1408 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1409 unsigned RegM = MI.getOperand(OpIdx).getReg();
1410 unsigned Binary = 0;
1411 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1412 RegM = getARMRegisterNumbering(RegM);
1416 Binary |= ((RegM & 0x1E) >> 1);
1417 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1422 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1423 const TargetInstrDesc &TID = MI.getDesc();
1425 // Part of binary is determined by TableGn.
1426 unsigned Binary = getBinaryCodeForInstr(MI);
1428 // Set the conditional execution predicate
1429 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1432 assert((Binary & ARMII::D_BitShift) == 0 &&
1433 (Binary & ARMII::N_BitShift) == 0 &&
1434 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1437 Binary |= encodeVFPRd(MI, OpIdx++);
1439 // If this is a two-address operand, skip it, e.g. FMACD.
1440 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1444 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1445 Binary |= encodeVFPRn(MI, OpIdx++);
1447 if (OpIdx == TID.getNumOperands() ||
1448 TID.OpInfo[OpIdx].isPredicate() ||
1449 TID.OpInfo[OpIdx].isOptionalDef()) {
1450 // FCMPEZD etc. has only one operand.
1456 Binary |= encodeVFPRm(MI, OpIdx);
1461 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1462 const TargetInstrDesc &TID = MI.getDesc();
1463 unsigned Form = TID.TSFlags & ARMII::FormMask;
1465 // Part of binary is determined by TableGn.
1466 unsigned Binary = getBinaryCodeForInstr(MI);
1468 // Set the conditional execution predicate
1469 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1473 case ARMII::VFPConv1Frm:
1474 case ARMII::VFPConv2Frm:
1475 case ARMII::VFPConv3Frm:
1477 Binary |= encodeVFPRd(MI, 0);
1479 case ARMII::VFPConv4Frm:
1481 Binary |= encodeVFPRn(MI, 0);
1483 case ARMII::VFPConv5Frm:
1485 Binary |= encodeVFPRm(MI, 0);
1491 case ARMII::VFPConv1Frm:
1493 Binary |= encodeVFPRm(MI, 1);
1495 case ARMII::VFPConv2Frm:
1496 case ARMII::VFPConv3Frm:
1498 Binary |= encodeVFPRn(MI, 1);
1500 case ARMII::VFPConv4Frm:
1501 case ARMII::VFPConv5Frm:
1503 Binary |= encodeVFPRd(MI, 1);
1507 if (Form == ARMII::VFPConv5Frm)
1509 Binary |= encodeVFPRn(MI, 2);
1510 else if (Form == ARMII::VFPConv3Frm)
1512 Binary |= encodeVFPRm(MI, 2);
1517 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1518 // Part of binary is determined by TableGn.
1519 unsigned Binary = getBinaryCodeForInstr(MI);
1521 // Set the conditional execution predicate
1522 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1527 Binary |= encodeVFPRd(MI, OpIdx++);
1529 // Encode address base.
1530 const MachineOperand &Base = MI.getOperand(OpIdx++);
1531 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1533 // If there is a non-zero immediate offset, encode it.
1535 const MachineOperand &Offset = MI.getOperand(OpIdx);
1536 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1537 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1538 Binary |= 1 << ARMII::U_BitShift;
1545 // If immediate offset is omitted, default to +0.
1546 Binary |= 1 << ARMII::U_BitShift;
1552 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1553 const TargetInstrDesc &TID = MI.getDesc();
1554 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1556 // Part of binary is determined by TableGn.
1557 unsigned Binary = getBinaryCodeForInstr(MI);
1559 // Set the conditional execution predicate
1560 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1562 // Skip operand 0 of an instruction with base register update.
1567 // Set base address operand
1568 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1570 // Set addressing mode by modifying bits U(23) and P(24)
1571 const MachineOperand &MO = MI.getOperand(OpIdx++);
1572 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1576 Binary |= 0x1 << ARMII::W_BitShift;
1578 // First register is encoded in Dd.
1579 Binary |= encodeVFPRd(MI, OpIdx+2);
1581 // Count the number of registers.
1582 unsigned NumRegs = 1;
1583 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1584 const MachineOperand &MO = MI.getOperand(i);
1585 if (!MO.isReg() || MO.isImplicit())
1589 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1590 // Otherwise, it will be 0, in the case of 32-bit registers.
1592 Binary |= NumRegs * 2;
1599 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1600 unsigned RegD = MI.getOperand(OpIdx).getReg();
1601 unsigned Binary = 0;
1602 RegD = getARMRegisterNumbering(RegD);
1603 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1604 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1608 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1609 unsigned RegN = MI.getOperand(OpIdx).getReg();
1610 unsigned Binary = 0;
1611 RegN = getARMRegisterNumbering(RegN);
1612 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1613 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1617 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1618 unsigned RegM = MI.getOperand(OpIdx).getReg();
1619 unsigned Binary = 0;
1620 RegM = getARMRegisterNumbering(RegM);
1621 Binary |= (RegM & 0xf);
1622 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1626 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1627 /// data-processing instruction to the corresponding Thumb encoding.
1628 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1629 assert((Binary & 0xfe000000) == 0xf2000000 &&
1630 "not an ARM NEON data-processing instruction");
1631 unsigned UBit = (Binary >> 24) & 1;
1632 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1635 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1636 unsigned Binary = getBinaryCodeForInstr(MI);
1638 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1639 const TargetInstrDesc &TID = MI.getDesc();
1640 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1644 } else { // ARMII::NSetLnFrm
1650 // Set the conditional execution predicate
1651 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1653 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1654 RegT = getARMRegisterNumbering(RegT);
1655 Binary |= (RegT << ARMII::RegRdShift);
1656 Binary |= encodeNEONRn(MI, RegNOpIdx);
1659 if ((Binary & (1 << 22)) != 0)
1660 LaneShift = 0; // 8-bit elements
1661 else if ((Binary & (1 << 5)) != 0)
1662 LaneShift = 1; // 16-bit elements
1664 LaneShift = 2; // 32-bit elements
1666 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1667 unsigned Opc1 = Lane >> 2;
1668 unsigned Opc2 = Lane & 3;
1669 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1670 Binary |= (Opc1 << 21);
1671 Binary |= (Opc2 << 5);
1676 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1677 unsigned Binary = getBinaryCodeForInstr(MI);
1679 // Set the conditional execution predicate
1680 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1682 unsigned RegT = MI.getOperand(1).getReg();
1683 RegT = getARMRegisterNumbering(RegT);
1684 Binary |= (RegT << ARMII::RegRdShift);
1685 Binary |= encodeNEONRn(MI, 0);
1689 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1690 unsigned Binary = getBinaryCodeForInstr(MI);
1691 // Destination register is encoded in Dd.
1692 Binary |= encodeNEONRd(MI, 0);
1693 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1694 unsigned Imm = MI.getOperand(1).getImm();
1695 unsigned Op = (Imm >> 12) & 1;
1696 unsigned Cmode = (Imm >> 8) & 0xf;
1697 unsigned I = (Imm >> 7) & 1;
1698 unsigned Imm3 = (Imm >> 4) & 0x7;
1699 unsigned Imm4 = Imm & 0xf;
1700 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1702 Binary = convertNEONDataProcToThumb(Binary);
1706 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1707 const TargetInstrDesc &TID = MI.getDesc();
1708 unsigned Binary = getBinaryCodeForInstr(MI);
1709 // Destination register is encoded in Dd; source register in Dm.
1711 Binary |= encodeNEONRd(MI, OpIdx++);
1712 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1714 Binary |= encodeNEONRm(MI, OpIdx);
1716 Binary = convertNEONDataProcToThumb(Binary);
1717 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1721 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1722 const TargetInstrDesc &TID = MI.getDesc();
1723 unsigned Binary = getBinaryCodeForInstr(MI);
1724 // Destination register is encoded in Dd; source registers in Dn and Dm.
1726 Binary |= encodeNEONRd(MI, OpIdx++);
1727 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1729 Binary |= encodeNEONRn(MI, OpIdx++);
1730 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1732 Binary |= encodeNEONRm(MI, OpIdx);
1734 Binary = convertNEONDataProcToThumb(Binary);
1735 // FIXME: This does not handle VMOVDneon or VMOVQ.
1739 #include "ARMGenCodeEmitter.inc"