1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
47 class ARMCodeEmitter : public MachineFunctionPass {
49 const ARMInstrInfo *II;
51 const ARMSubtarget *Subtarget;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
79 bool runOnMachineFunction(MachineFunction &MF);
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
85 void emitInstruction(const MachineInstr &MI);
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const TargetInstrDesc &TID,
100 const MachineOperand &MO,
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120 void emitMulFrmInstruction(const MachineInstr &MI);
122 void emitExtendInstruction(const MachineInstr &MI);
124 void emitMiscArithInstruction(const MachineInstr &MI);
126 void emitSaturateInstruction(const MachineInstr &MI);
128 void emitBranchInstruction(const MachineInstr &MI);
130 void emitInlineJumpTable(unsigned JTIndex);
132 void emitMiscBranchInstruction(const MachineInstr &MI);
134 void emitVFPArithInstruction(const MachineInstr &MI);
136 void emitVFPConversionInstruction(const MachineInstr &MI);
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
184 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
186 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
188 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
190 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
192 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
194 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
196 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
198 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
200 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
201 unsigned Op) const { return 0; }
202 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
204 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
207 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
210 // {12} = (U)nsigned (add == '1', sub == '0')
212 const MachineOperand &MO = MI.getOperand(Op);
213 const MachineOperand &MO1 = MI.getOperand(Op + 1);
215 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
218 unsigned Reg = getARMRegisterNumbering(MO.getReg());
219 int32_t Imm12 = MO1.getImm();
221 Binary = Imm12 & 0xfff;
224 Binary |= (Reg << 13);
228 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
232 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
234 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
236 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
238 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
240 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
242 // {12} = (U)nsigned (add == '1', sub == '0')
244 const MachineOperand &MO = MI.getOperand(Op);
245 const MachineOperand &MO1 = MI.getOperand(Op + 1);
247 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
250 unsigned Reg = getARMRegisterNumbering(MO.getReg());
251 int32_t Imm12 = MO1.getImm();
253 // Special value for #-0
254 if (Imm12 == INT32_MIN)
257 // Immediate is always encoded as positive. The 'U' bit controls add vs
265 uint32_t Binary = Imm12 & 0xfff;
268 Binary |= (Reg << 13);
271 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
274 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
277 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
278 /// machine operand requires relocation, record the relocation and return
280 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
283 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
285 unsigned getShiftOp(unsigned Imm) const ;
287 /// Routines that handle operands which add machine relocations which are
288 /// fixed up by the relocation stage.
289 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
290 bool MayNeedFarStub, bool Indirect,
291 intptr_t ACPV = 0) const;
292 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
293 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
294 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
295 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
296 intptr_t JTBase = 0) const;
300 char ARMCodeEmitter::ID = 0;
302 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
303 /// code to the specified MCE object.
304 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
305 JITCodeEmitter &JCE) {
306 return new ARMCodeEmitter(TM, JCE);
309 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
310 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
311 MF.getTarget().getRelocationModel() != Reloc::Static) &&
312 "JIT relocation model must be set to static or default!");
313 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
314 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
315 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
316 Subtarget = &TM.getSubtarget<ARMSubtarget>();
317 MCPEs = &MF.getConstantPool()->getConstants();
319 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
320 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
321 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
322 JTI->Initialize(MF, IsPIC);
323 MMI = &getAnalysis<MachineModuleInfo>();
324 MCE.setModuleInfo(MMI);
327 DEBUG(errs() << "JITTing function '"
328 << MF.getFunction()->getName() << "'\n");
329 MCE.startFunction(MF);
330 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
332 MCE.StartMachineBasicBlock(MBB);
333 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
337 } while (MCE.finishFunction(MF));
342 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
344 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
345 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
346 default: llvm_unreachable("Unknown shift opc!");
347 case ARM_AM::asr: return 2;
348 case ARM_AM::lsl: return 0;
349 case ARM_AM::lsr: return 1;
351 case ARM_AM::rrx: return 3;
356 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
357 /// machine operand requires relocation, record the relocation and return zero.
358 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
359 const MachineOperand &MO,
361 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
362 && "Relocation to this function should be for movt or movw");
365 return static_cast<unsigned>(MO.getImm());
366 else if (MO.isGlobal())
367 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
368 else if (MO.isSymbol())
369 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
371 emitMachineBasicBlock(MO.getMBB(), Reloc);
376 llvm_unreachable("Unsupported operand type for movw/movt");
381 /// getMachineOpValue - Return binary encoding of operand. If the machine
382 /// operand requires relocation, record the relocation and return zero.
383 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
384 const MachineOperand &MO) const {
386 return getARMRegisterNumbering(MO.getReg());
388 return static_cast<unsigned>(MO.getImm());
389 else if (MO.isGlobal())
390 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
391 else if (MO.isSymbol())
392 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
393 else if (MO.isCPI()) {
394 const TargetInstrDesc &TID = MI.getDesc();
395 // For VFP load, the immediate offset is multiplied by 4.
396 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
397 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
398 emitConstPoolAddress(MO.getIndex(), Reloc);
399 } else if (MO.isJTI())
400 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
402 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
404 llvm_unreachable("Unable to encode MachineOperand!");
408 /// emitGlobalAddress - Emit the specified address to the code stream.
410 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
411 bool MayNeedFarStub, bool Indirect,
412 intptr_t ACPV) const {
413 MachineRelocation MR = Indirect
414 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
415 const_cast<GlobalValue *>(GV),
416 ACPV, MayNeedFarStub)
417 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
418 const_cast<GlobalValue *>(GV), ACPV,
420 MCE.addRelocation(MR);
423 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
424 /// be emitted to the current location in the function, and allow it to be PC
426 void ARMCodeEmitter::
427 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
428 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
432 /// emitConstPoolAddress - Arrange for the address of an constant pool
433 /// to be emitted to the current location in the function, and allow it to be PC
435 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
436 // Tell JIT emitter we'll resolve the address.
437 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
438 Reloc, CPI, 0, true));
441 /// emitJumpTableAddress - Arrange for the address of a jump table to
442 /// be emitted to the current location in the function, and allow it to be PC
444 void ARMCodeEmitter::
445 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
446 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
447 Reloc, JTIndex, 0, true));
450 /// emitMachineBasicBlock - Emit the specified address basic block.
451 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
453 intptr_t JTBase) const {
454 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
458 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
459 DEBUG(errs() << " 0x";
460 errs().write_hex(Binary) << "\n");
461 MCE.emitWordLE(Binary);
464 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
465 DEBUG(errs() << " 0x";
466 errs().write_hex(Binary) << "\n");
467 MCE.emitDWordLE(Binary);
470 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
471 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
473 MCE.processDebugLoc(MI.getDebugLoc(), true);
475 ++NumEmitted; // Keep track of the # of mi's emitted
476 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
478 llvm_unreachable("Unhandled instruction encoding format!");
482 if (MI.getOpcode() == ARM::LEApcrelJT) {
483 // Materialize jumptable address.
484 emitLEApcrelJTInstruction(MI);
487 llvm_unreachable("Unhandled instruction encoding!");
490 emitPseudoInstruction(MI);
493 case ARMII::DPSoRegFrm:
494 emitDataProcessingInstruction(MI);
498 emitLoadStoreInstruction(MI);
500 case ARMII::LdMiscFrm:
501 case ARMII::StMiscFrm:
502 emitMiscLoadStoreInstruction(MI);
504 case ARMII::LdStMulFrm:
505 emitLoadStoreMultipleInstruction(MI);
508 emitMulFrmInstruction(MI);
511 emitExtendInstruction(MI);
513 case ARMII::ArithMiscFrm:
514 emitMiscArithInstruction(MI);
517 emitSaturateInstruction(MI);
520 emitBranchInstruction(MI);
522 case ARMII::BrMiscFrm:
523 emitMiscBranchInstruction(MI);
526 case ARMII::VFPUnaryFrm:
527 case ARMII::VFPBinaryFrm:
528 emitVFPArithInstruction(MI);
530 case ARMII::VFPConv1Frm:
531 case ARMII::VFPConv2Frm:
532 case ARMII::VFPConv3Frm:
533 case ARMII::VFPConv4Frm:
534 case ARMII::VFPConv5Frm:
535 emitVFPConversionInstruction(MI);
537 case ARMII::VFPLdStFrm:
538 emitVFPLoadStoreInstruction(MI);
540 case ARMII::VFPLdStMulFrm:
541 emitVFPLoadStoreMultipleInstruction(MI);
544 // NEON instructions.
545 case ARMII::NGetLnFrm:
546 case ARMII::NSetLnFrm:
547 emitNEONLaneInstruction(MI);
550 emitNEONDupInstruction(MI);
552 case ARMII::N1RegModImmFrm:
553 emitNEON1RegModImmInstruction(MI);
555 case ARMII::N2RegFrm:
556 emitNEON2RegInstruction(MI);
558 case ARMII::N3RegFrm:
559 emitNEON3RegInstruction(MI);
562 MCE.processDebugLoc(MI.getDebugLoc(), false);
565 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
566 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
567 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
568 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
570 // Remember the CONSTPOOL_ENTRY address for later relocation.
571 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
573 // Emit constpool island entry. In most cases, the actual values will be
574 // resolved and relocated after code emission.
575 if (MCPE.isMachineConstantPoolEntry()) {
576 ARMConstantPoolValue *ACPV =
577 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
579 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
580 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
582 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
583 const GlobalValue *GV = ACPV->getGV();
585 Reloc::Model RelocM = TM.getRelocationModel();
586 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
588 Subtarget->GVIsIndirectSymbol(GV, RelocM),
591 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
595 const Constant *CV = MCPE.Val.ConstVal;
598 errs() << " ** Constant pool #" << CPI << " @ "
599 << (void*)MCE.getCurrentPCValue() << " ";
600 if (const Function *F = dyn_cast<Function>(CV))
601 errs() << F->getName();
607 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
608 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
610 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
611 uint32_t Val = uint32_t(*CI->getValue().getRawData());
613 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
614 if (CFP->getType()->isFloatTy())
615 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
616 else if (CFP->getType()->isDoubleTy())
617 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
619 llvm_unreachable("Unable to handle this constantpool entry!");
622 llvm_unreachable("Unable to handle this constantpool entry!");
627 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
628 const MachineOperand &MO0 = MI.getOperand(0);
629 const MachineOperand &MO1 = MI.getOperand(1);
631 // Emit the 'movw' instruction.
632 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
634 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
636 // Set the conditional execution predicate.
637 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
640 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
642 // Encode imm16 as imm4:imm12
643 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
644 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
647 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
648 // Emit the 'movt' instruction.
649 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
651 // Set the conditional execution predicate.
652 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
655 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
657 // Encode imm16 as imm4:imm1, same as movw above.
658 Binary |= Hi16 & 0xFFF;
659 Binary |= ((Hi16 >> 12) & 0xF) << 16;
663 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
664 const MachineOperand &MO0 = MI.getOperand(0);
665 const MachineOperand &MO1 = MI.getOperand(1);
666 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
667 "Not a valid so_imm value!");
668 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
669 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
671 // Emit the 'mov' instruction.
672 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
674 // Set the conditional execution predicate.
675 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
678 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
681 // Set bit I(25) to identify this is the immediate form of <shifter_op>
682 Binary |= 1 << ARMII::I_BitShift;
683 Binary |= getMachineSoImmOpValue(V1);
686 // Now the 'orr' instruction.
687 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
689 // Set the conditional execution predicate.
690 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
693 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
696 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
699 // Set bit I(25) to identify this is the immediate form of <shifter_op>
700 Binary |= 1 << ARMII::I_BitShift;
701 Binary |= getMachineSoImmOpValue(V2);
705 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
706 // It's basically add r, pc, (LJTI - $+8)
708 const TargetInstrDesc &TID = MI.getDesc();
710 // Emit the 'add' instruction.
711 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
713 // Set the conditional execution predicate
714 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
716 // Encode S bit if MI modifies CPSR.
717 Binary |= getAddrModeSBit(MI, TID);
720 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
722 // Encode Rn which is PC.
723 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
725 // Encode the displacement.
726 Binary |= 1 << ARMII::I_BitShift;
727 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
732 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
733 unsigned Opcode = MI.getDesc().Opcode;
735 // Part of binary is determined by TableGn.
736 unsigned Binary = getBinaryCodeForInstr(MI);
738 // Set the conditional execution predicate
739 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
741 // Encode S bit if MI modifies CPSR.
742 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
743 Binary |= 1 << ARMII::S_BitShift;
745 // Encode register def if there is one.
746 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
748 // Encode the shift operation.
755 case ARM::MOVsrl_flag:
757 Binary |= (0x2 << 4) | (1 << 7);
759 case ARM::MOVsra_flag:
761 Binary |= (0x4 << 4) | (1 << 7);
765 // Encode register Rm.
766 Binary |= getMachineOpValue(MI, 1);
771 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
772 DEBUG(errs() << " ** LPC" << LabelID << " @ "
773 << (void*)MCE.getCurrentPCValue() << '\n');
774 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
777 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
778 unsigned Opcode = MI.getDesc().Opcode;
781 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
783 case ARM::BMOVPCRX_CALL:
785 case ARM::BMOVPCRXr9_CALL: {
786 // First emit mov lr, pc
787 unsigned Binary = 0x01a0e00f;
788 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
791 // and then emit the branch.
792 emitMiscBranchInstruction(MI);
795 case TargetOpcode::INLINEASM: {
796 // We allow inline assembler nodes with empty bodies - they can
797 // implicitly define registers, which is ok for JIT.
798 if (MI.getOperand(0).getSymbolName()[0]) {
799 report_fatal_error("JIT does not support inline asm!");
803 case TargetOpcode::PROLOG_LABEL:
804 case TargetOpcode::EH_LABEL:
805 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
807 case TargetOpcode::IMPLICIT_DEF:
808 case TargetOpcode::KILL:
811 case ARM::CONSTPOOL_ENTRY:
812 emitConstPoolInstruction(MI);
815 // Remember of the address of the PC label for relocation later.
816 addPCLabel(MI.getOperand(2).getImm());
817 // PICADD is just an add instruction that implicitly read pc.
818 emitDataProcessingInstruction(MI, 0, ARM::PC);
825 // Remember of the address of the PC label for relocation later.
826 addPCLabel(MI.getOperand(2).getImm());
827 // These are just load / store instructions that implicitly read pc.
828 emitLoadStoreInstruction(MI, 0, ARM::PC);
835 // Remember of the address of the PC label for relocation later.
836 addPCLabel(MI.getOperand(2).getImm());
837 // These are just load / store instructions that implicitly read pc.
838 emitMiscLoadStoreInstruction(MI, ARM::PC);
843 // Two instructions to materialize a constant.
844 if (Subtarget->hasV6T2Ops())
845 emitMOVi32immInstruction(MI);
847 emitMOVi2piecesInstruction(MI);
850 case ARM::LEApcrelJT:
851 // Materialize jumptable address.
852 emitLEApcrelJTInstruction(MI);
855 case ARM::MOVsrl_flag:
856 case ARM::MOVsra_flag:
857 emitPseudoMoveInstruction(MI);
862 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
863 const TargetInstrDesc &TID,
864 const MachineOperand &MO,
866 unsigned Binary = getMachineOpValue(MI, MO);
868 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
869 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
870 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
872 // Encode the shift opcode.
874 unsigned Rs = MO1.getReg();
876 // Set shift operand (bit[7:4]).
881 // RRX - 0110 and bit[11:8] clear.
883 default: llvm_unreachable("Unknown shift opc!");
884 case ARM_AM::lsl: SBits = 0x1; break;
885 case ARM_AM::lsr: SBits = 0x3; break;
886 case ARM_AM::asr: SBits = 0x5; break;
887 case ARM_AM::ror: SBits = 0x7; break;
888 case ARM_AM::rrx: SBits = 0x6; break;
891 // Set shift operand (bit[6:4]).
897 default: llvm_unreachable("Unknown shift opc!");
898 case ARM_AM::lsl: SBits = 0x0; break;
899 case ARM_AM::lsr: SBits = 0x2; break;
900 case ARM_AM::asr: SBits = 0x4; break;
901 case ARM_AM::ror: SBits = 0x6; break;
904 Binary |= SBits << 4;
905 if (SOpc == ARM_AM::rrx)
908 // Encode the shift operation Rs or shift_imm (except rrx).
910 // Encode Rs bit[11:8].
911 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
912 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
915 // Encode shift_imm bit[11:7].
916 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
919 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
920 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
921 assert(SoImmVal != -1 && "Not a valid so_imm value!");
923 // Encode rotate_imm.
924 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
925 << ARMII::SoRotImmShift;
928 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
932 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
933 const TargetInstrDesc &TID) const {
934 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
935 const MachineOperand &MO = MI.getOperand(i-1);
936 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
937 return 1 << ARMII::S_BitShift;
942 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
944 unsigned ImplicitRn) {
945 const TargetInstrDesc &TID = MI.getDesc();
947 // Part of binary is determined by TableGn.
948 unsigned Binary = getBinaryCodeForInstr(MI);
950 // Set the conditional execution predicate
951 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
953 // Encode S bit if MI modifies CPSR.
954 Binary |= getAddrModeSBit(MI, TID);
956 // Encode register def if there is one.
957 unsigned NumDefs = TID.getNumDefs();
960 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
962 // Special handling for implicit use (e.g. PC).
963 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
965 if (TID.Opcode == ARM::MOVi16) {
966 // Get immediate from MI.
967 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
968 ARM::reloc_arm_movw);
969 // Encode imm which is the same as in emitMOVi32immInstruction().
970 Binary |= Lo16 & 0xFFF;
971 Binary |= ((Lo16 >> 12) & 0xF) << 16;
974 } else if(TID.Opcode == ARM::MOVTi16) {
975 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
976 ARM::reloc_arm_movt) >> 16);
977 Binary |= Hi16 & 0xFFF;
978 Binary |= ((Hi16 >> 12) & 0xF) << 16;
981 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
982 uint32_t v = ~MI.getOperand(2).getImm();
983 int32_t lsb = CountTrailingZeros_32(v);
984 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
985 // Instr{20-16} = msb, Instr{11-7} = lsb
986 Binary |= (msb & 0x1F) << 16;
987 Binary |= (lsb & 0x1F) << 7;
990 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
991 // Encode Rn in Instr{0-3}
992 Binary |= getMachineOpValue(MI, OpIdx++);
994 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
995 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
997 // Instr{20-16} = widthm1, Instr{11-7} = lsb
998 Binary |= (widthm1 & 0x1F) << 16;
999 Binary |= (lsb & 0x1F) << 7;
1004 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1005 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1008 // Encode first non-shifter register operand if there is one.
1009 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1012 // Special handling for implicit use (e.g. PC).
1013 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1015 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1020 // Encode shifter operand.
1021 const MachineOperand &MO = MI.getOperand(OpIdx);
1022 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1024 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1029 // Encode register Rm.
1030 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1035 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1040 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1041 unsigned ImplicitRd,
1042 unsigned ImplicitRn) {
1043 const TargetInstrDesc &TID = MI.getDesc();
1044 unsigned Form = TID.TSFlags & ARMII::FormMask;
1045 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1047 // Part of binary is determined by TableGn.
1048 unsigned Binary = getBinaryCodeForInstr(MI);
1050 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1051 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1052 MI.getOpcode() == ARM::STRi12) {
1057 // Set the conditional execution predicate
1058 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1062 // Operand 0 of a pre- and post-indexed store is the address base
1063 // writeback. Skip it.
1064 bool Skipped = false;
1065 if (IsPrePost && Form == ARMII::StFrm) {
1070 // Set first operand
1072 // Special handling for implicit use (e.g. PC).
1073 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1075 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1077 // Set second operand
1079 // Special handling for implicit use (e.g. PC).
1080 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1082 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1084 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1085 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1088 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1089 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1090 ? 0 : MI.getOperand(OpIdx+1).getImm();
1092 // Set bit U(23) according to sign of immed value (positive or negative).
1093 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1095 if (!MO2.getReg()) { // is immediate
1096 if (ARM_AM::getAM2Offset(AM2Opc))
1097 // Set the value of offset_12 field
1098 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1103 // Set bit I(25), because this is not in immediate encoding.
1104 Binary |= 1 << ARMII::I_BitShift;
1105 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1106 // Set bit[3:0] to the corresponding Rm register
1107 Binary |= getARMRegisterNumbering(MO2.getReg());
1109 // If this instr is in scaled register offset/index instruction, set
1110 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1111 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1112 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1113 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1119 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1120 unsigned ImplicitRn) {
1121 const TargetInstrDesc &TID = MI.getDesc();
1122 unsigned Form = TID.TSFlags & ARMII::FormMask;
1123 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1125 // Part of binary is determined by TableGn.
1126 unsigned Binary = getBinaryCodeForInstr(MI);
1128 // Set the conditional execution predicate
1129 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1133 // Operand 0 of a pre- and post-indexed store is the address base
1134 // writeback. Skip it.
1135 bool Skipped = false;
1136 if (IsPrePost && Form == ARMII::StMiscFrm) {
1141 // Set first operand
1142 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1144 // Skip LDRD and STRD's second operand.
1145 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1148 // Set second operand
1150 // Special handling for implicit use (e.g. PC).
1151 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1153 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1155 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1156 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1159 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1160 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1161 ? 0 : MI.getOperand(OpIdx+1).getImm();
1163 // Set bit U(23) according to sign of immed value (positive or negative)
1164 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1167 // If this instr is in register offset/index encoding, set bit[3:0]
1168 // to the corresponding Rm register.
1170 Binary |= getARMRegisterNumbering(MO2.getReg());
1175 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1176 Binary |= 1 << ARMII::AM3_I_BitShift;
1177 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1179 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1180 Binary |= (ImmOffs & 0xF); // immedL
1186 static unsigned getAddrModeUPBits(unsigned Mode) {
1187 unsigned Binary = 0;
1189 // Set addressing mode by modifying bits U(23) and P(24)
1190 // IA - Increment after - bit U = 1 and bit P = 0
1191 // IB - Increment before - bit U = 1 and bit P = 1
1192 // DA - Decrement after - bit U = 0 and bit P = 0
1193 // DB - Decrement before - bit U = 0 and bit P = 1
1195 default: llvm_unreachable("Unknown addressing sub-mode!");
1196 case ARM_AM::da: break;
1197 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1198 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1199 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1205 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1206 const TargetInstrDesc &TID = MI.getDesc();
1207 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1209 // Part of binary is determined by TableGn.
1210 unsigned Binary = getBinaryCodeForInstr(MI);
1212 // Set the conditional execution predicate
1213 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1215 // Skip operand 0 of an instruction with base register update.
1220 // Set base address operand
1221 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1223 // Set addressing mode by modifying bits U(23) and P(24)
1224 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1225 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1229 Binary |= 0x1 << ARMII::W_BitShift;
1232 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1233 const MachineOperand &MO = MI.getOperand(i);
1234 if (!MO.isReg() || MO.isImplicit())
1236 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1237 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1239 Binary |= 0x1 << RegNum;
1245 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1246 const TargetInstrDesc &TID = MI.getDesc();
1248 // Part of binary is determined by TableGn.
1249 unsigned Binary = getBinaryCodeForInstr(MI);
1251 // Set the conditional execution predicate
1252 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1254 // Encode S bit if MI modifies CPSR.
1255 Binary |= getAddrModeSBit(MI, TID);
1257 // 32x32->64bit operations have two destination registers. The number
1258 // of register definitions will tell us if that's what we're dealing with.
1260 if (TID.getNumDefs() == 2)
1261 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1264 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1267 Binary |= getMachineOpValue(MI, OpIdx++);
1270 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1272 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1273 // it as Rn (for multiply, that's in the same offset as RdLo.
1274 if (TID.getNumOperands() > OpIdx &&
1275 !TID.OpInfo[OpIdx].isPredicate() &&
1276 !TID.OpInfo[OpIdx].isOptionalDef())
1277 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1282 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1283 const TargetInstrDesc &TID = MI.getDesc();
1285 // Part of binary is determined by TableGn.
1286 unsigned Binary = getBinaryCodeForInstr(MI);
1288 // Set the conditional execution predicate
1289 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1294 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1296 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1297 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1299 // Two register operand form.
1301 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1304 Binary |= getMachineOpValue(MI, MO2);
1307 Binary |= getMachineOpValue(MI, MO1);
1310 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1311 if (MI.getOperand(OpIdx).isImm() &&
1312 !TID.OpInfo[OpIdx].isPredicate() &&
1313 !TID.OpInfo[OpIdx].isOptionalDef())
1314 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1319 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1320 const TargetInstrDesc &TID = MI.getDesc();
1322 // Part of binary is determined by TableGn.
1323 unsigned Binary = getBinaryCodeForInstr(MI);
1325 // Set the conditional execution predicate
1326 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1331 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1333 const MachineOperand &MO = MI.getOperand(OpIdx++);
1334 if (OpIdx == TID.getNumOperands() ||
1335 TID.OpInfo[OpIdx].isPredicate() ||
1336 TID.OpInfo[OpIdx].isOptionalDef()) {
1337 // Encode Rm and it's done.
1338 Binary |= getMachineOpValue(MI, MO);
1344 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1347 Binary |= getMachineOpValue(MI, OpIdx++);
1349 // Encode shift_imm.
1350 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1351 if (TID.Opcode == ARM::PKHTB) {
1352 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1356 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1357 Binary |= ShiftAmt << ARMII::ShiftShift;
1362 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1363 const TargetInstrDesc &TID = MI.getDesc();
1365 // Part of binary is determined by TableGen.
1366 unsigned Binary = getBinaryCodeForInstr(MI);
1368 // Set the conditional execution predicate
1369 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1372 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1374 // Encode saturate bit position.
1375 unsigned Pos = MI.getOperand(1).getImm();
1376 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1378 assert((Pos < 16 || (Pos < 32 &&
1379 TID.Opcode != ARM::SSAT16 &&
1380 TID.Opcode != ARM::USAT16)) &&
1381 "saturate bit position out of range");
1382 Binary |= Pos << 16;
1385 Binary |= getMachineOpValue(MI, 2);
1387 // Encode shift_imm.
1388 if (TID.getNumOperands() == 4) {
1389 unsigned ShiftOp = MI.getOperand(3).getImm();
1390 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1391 if (Opc == ARM_AM::asr)
1393 unsigned ShiftAmt = MI.getOperand(3).getImm();
1394 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1396 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1397 Binary |= ShiftAmt << ARMII::ShiftShift;
1403 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1404 const TargetInstrDesc &TID = MI.getDesc();
1406 if (TID.Opcode == ARM::TPsoft) {
1407 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1410 // Part of binary is determined by TableGn.
1411 unsigned Binary = getBinaryCodeForInstr(MI);
1413 // Set the conditional execution predicate
1414 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1416 // Set signed_immed_24 field
1417 Binary |= getMachineOpValue(MI, 0);
1422 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1423 // Remember the base address of the inline jump table.
1424 uintptr_t JTBase = MCE.getCurrentPCValue();
1425 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1426 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1429 // Now emit the jump table entries.
1430 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1431 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1433 // DestBB address - JT base.
1434 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1436 // Absolute DestBB address.
1437 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1442 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1443 const TargetInstrDesc &TID = MI.getDesc();
1445 // Handle jump tables.
1446 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1447 // First emit a ldr pc, [] instruction.
1448 emitDataProcessingInstruction(MI, ARM::PC);
1450 // Then emit the inline jump table.
1452 (TID.Opcode == ARM::BR_JTr)
1453 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1454 emitInlineJumpTable(JTIndex);
1456 } else if (TID.Opcode == ARM::BR_JTm) {
1457 // First emit a ldr pc, [] instruction.
1458 emitLoadStoreInstruction(MI, ARM::PC);
1460 // Then emit the inline jump table.
1461 emitInlineJumpTable(MI.getOperand(3).getIndex());
1465 // Part of binary is determined by TableGn.
1466 unsigned Binary = getBinaryCodeForInstr(MI);
1468 // Set the conditional execution predicate
1469 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1471 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1472 // The return register is LR.
1473 Binary |= getARMRegisterNumbering(ARM::LR);
1475 // otherwise, set the return register
1476 Binary |= getMachineOpValue(MI, 0);
1481 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1482 unsigned RegD = MI.getOperand(OpIdx).getReg();
1483 unsigned Binary = 0;
1484 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1485 RegD = getARMRegisterNumbering(RegD);
1487 Binary |= RegD << ARMII::RegRdShift;
1489 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1490 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1495 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1496 unsigned RegN = MI.getOperand(OpIdx).getReg();
1497 unsigned Binary = 0;
1498 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1499 RegN = getARMRegisterNumbering(RegN);
1501 Binary |= RegN << ARMII::RegRnShift;
1503 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1504 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1509 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1510 unsigned RegM = MI.getOperand(OpIdx).getReg();
1511 unsigned Binary = 0;
1512 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1513 RegM = getARMRegisterNumbering(RegM);
1517 Binary |= ((RegM & 0x1E) >> 1);
1518 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1523 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1524 const TargetInstrDesc &TID = MI.getDesc();
1526 // Part of binary is determined by TableGn.
1527 unsigned Binary = getBinaryCodeForInstr(MI);
1529 // Set the conditional execution predicate
1530 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1533 assert((Binary & ARMII::D_BitShift) == 0 &&
1534 (Binary & ARMII::N_BitShift) == 0 &&
1535 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1538 Binary |= encodeVFPRd(MI, OpIdx++);
1540 // If this is a two-address operand, skip it, e.g. FMACD.
1541 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1545 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1546 Binary |= encodeVFPRn(MI, OpIdx++);
1548 if (OpIdx == TID.getNumOperands() ||
1549 TID.OpInfo[OpIdx].isPredicate() ||
1550 TID.OpInfo[OpIdx].isOptionalDef()) {
1551 // FCMPEZD etc. has only one operand.
1557 Binary |= encodeVFPRm(MI, OpIdx);
1562 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1563 const TargetInstrDesc &TID = MI.getDesc();
1564 unsigned Form = TID.TSFlags & ARMII::FormMask;
1566 // Part of binary is determined by TableGn.
1567 unsigned Binary = getBinaryCodeForInstr(MI);
1569 // Set the conditional execution predicate
1570 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1574 case ARMII::VFPConv1Frm:
1575 case ARMII::VFPConv2Frm:
1576 case ARMII::VFPConv3Frm:
1578 Binary |= encodeVFPRd(MI, 0);
1580 case ARMII::VFPConv4Frm:
1582 Binary |= encodeVFPRn(MI, 0);
1584 case ARMII::VFPConv5Frm:
1586 Binary |= encodeVFPRm(MI, 0);
1592 case ARMII::VFPConv1Frm:
1594 Binary |= encodeVFPRm(MI, 1);
1596 case ARMII::VFPConv2Frm:
1597 case ARMII::VFPConv3Frm:
1599 Binary |= encodeVFPRn(MI, 1);
1601 case ARMII::VFPConv4Frm:
1602 case ARMII::VFPConv5Frm:
1604 Binary |= encodeVFPRd(MI, 1);
1608 if (Form == ARMII::VFPConv5Frm)
1610 Binary |= encodeVFPRn(MI, 2);
1611 else if (Form == ARMII::VFPConv3Frm)
1613 Binary |= encodeVFPRm(MI, 2);
1618 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1619 // Part of binary is determined by TableGn.
1620 unsigned Binary = getBinaryCodeForInstr(MI);
1622 // Set the conditional execution predicate
1623 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1628 Binary |= encodeVFPRd(MI, OpIdx++);
1630 // Encode address base.
1631 const MachineOperand &Base = MI.getOperand(OpIdx++);
1632 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1634 // If there is a non-zero immediate offset, encode it.
1636 const MachineOperand &Offset = MI.getOperand(OpIdx);
1637 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1638 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1639 Binary |= 1 << ARMII::U_BitShift;
1646 // If immediate offset is omitted, default to +0.
1647 Binary |= 1 << ARMII::U_BitShift;
1653 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1654 const TargetInstrDesc &TID = MI.getDesc();
1655 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1657 // Part of binary is determined by TableGn.
1658 unsigned Binary = getBinaryCodeForInstr(MI);
1660 // Set the conditional execution predicate
1661 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1663 // Skip operand 0 of an instruction with base register update.
1668 // Set base address operand
1669 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1671 // Set addressing mode by modifying bits U(23) and P(24)
1672 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1673 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1677 Binary |= 0x1 << ARMII::W_BitShift;
1679 // First register is encoded in Dd.
1680 Binary |= encodeVFPRd(MI, OpIdx+2);
1682 // Count the number of registers.
1683 unsigned NumRegs = 1;
1684 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1685 const MachineOperand &MO = MI.getOperand(i);
1686 if (!MO.isReg() || MO.isImplicit())
1690 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1691 // Otherwise, it will be 0, in the case of 32-bit registers.
1693 Binary |= NumRegs * 2;
1700 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1701 unsigned RegD = MI.getOperand(OpIdx).getReg();
1702 unsigned Binary = 0;
1703 RegD = getARMRegisterNumbering(RegD);
1704 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1705 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1709 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1710 unsigned RegN = MI.getOperand(OpIdx).getReg();
1711 unsigned Binary = 0;
1712 RegN = getARMRegisterNumbering(RegN);
1713 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1714 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1718 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1719 unsigned RegM = MI.getOperand(OpIdx).getReg();
1720 unsigned Binary = 0;
1721 RegM = getARMRegisterNumbering(RegM);
1722 Binary |= (RegM & 0xf);
1723 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1727 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1728 /// data-processing instruction to the corresponding Thumb encoding.
1729 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1730 assert((Binary & 0xfe000000) == 0xf2000000 &&
1731 "not an ARM NEON data-processing instruction");
1732 unsigned UBit = (Binary >> 24) & 1;
1733 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1736 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1737 unsigned Binary = getBinaryCodeForInstr(MI);
1739 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1740 const TargetInstrDesc &TID = MI.getDesc();
1741 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1745 } else { // ARMII::NSetLnFrm
1751 // Set the conditional execution predicate
1752 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1754 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1755 RegT = getARMRegisterNumbering(RegT);
1756 Binary |= (RegT << ARMII::RegRdShift);
1757 Binary |= encodeNEONRn(MI, RegNOpIdx);
1760 if ((Binary & (1 << 22)) != 0)
1761 LaneShift = 0; // 8-bit elements
1762 else if ((Binary & (1 << 5)) != 0)
1763 LaneShift = 1; // 16-bit elements
1765 LaneShift = 2; // 32-bit elements
1767 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1768 unsigned Opc1 = Lane >> 2;
1769 unsigned Opc2 = Lane & 3;
1770 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1771 Binary |= (Opc1 << 21);
1772 Binary |= (Opc2 << 5);
1777 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1778 unsigned Binary = getBinaryCodeForInstr(MI);
1780 // Set the conditional execution predicate
1781 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1783 unsigned RegT = MI.getOperand(1).getReg();
1784 RegT = getARMRegisterNumbering(RegT);
1785 Binary |= (RegT << ARMII::RegRdShift);
1786 Binary |= encodeNEONRn(MI, 0);
1790 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1791 unsigned Binary = getBinaryCodeForInstr(MI);
1792 // Destination register is encoded in Dd.
1793 Binary |= encodeNEONRd(MI, 0);
1794 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1795 unsigned Imm = MI.getOperand(1).getImm();
1796 unsigned Op = (Imm >> 12) & 1;
1797 unsigned Cmode = (Imm >> 8) & 0xf;
1798 unsigned I = (Imm >> 7) & 1;
1799 unsigned Imm3 = (Imm >> 4) & 0x7;
1800 unsigned Imm4 = Imm & 0xf;
1801 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1803 Binary = convertNEONDataProcToThumb(Binary);
1807 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1808 const TargetInstrDesc &TID = MI.getDesc();
1809 unsigned Binary = getBinaryCodeForInstr(MI);
1810 // Destination register is encoded in Dd; source register in Dm.
1812 Binary |= encodeNEONRd(MI, OpIdx++);
1813 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1815 Binary |= encodeNEONRm(MI, OpIdx);
1817 Binary = convertNEONDataProcToThumb(Binary);
1818 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1822 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1823 const TargetInstrDesc &TID = MI.getDesc();
1824 unsigned Binary = getBinaryCodeForInstr(MI);
1825 // Destination register is encoded in Dd; source registers in Dn and Dm.
1827 Binary |= encodeNEONRd(MI, OpIdx++);
1828 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1830 Binary |= encodeNEONRn(MI, OpIdx++);
1831 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1833 Binary |= encodeNEONRm(MI, OpIdx);
1835 Binary = convertNEONDataProcToThumb(Binary);
1836 // FIXME: This does not handle VMOVDneon or VMOVQ.
1840 #include "ARMGenCodeEmitter.inc"