1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59 public ARMCodeEmitter {
61 const ARMInstrInfo *II;
65 const std::vector<MachineConstantPoolEntry> *MCPEs;
66 const std::vector<MachineJumpTableEntry> *MJTEs;
71 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
72 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
73 MCE(mce), MCPEs(0), MJTEs(0),
74 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
75 Emitter(TargetMachine &tm, CodeEmitter &mce,
76 const ARMInstrInfo &ii, const TargetData &td)
77 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
78 MCE(mce), MCPEs(0), MJTEs(0),
79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
81 bool runOnMachineFunction(MachineFunction &MF);
83 virtual const char *getPassName() const {
84 return "ARM Machine Code Emitter";
87 void emitInstruction(const MachineInstr &MI);
91 void emitWordLE(unsigned Binary);
93 void emitDWordLE(uint64_t Binary);
95 void emitConstPoolInstruction(const MachineInstr &MI);
97 void emitMOVi2piecesInstruction(const MachineInstr &MI);
99 void emitLEApcrelJTInstruction(const MachineInstr &MI);
101 void emitPseudoMoveInstruction(const MachineInstr &MI);
103 void addPCLabel(unsigned LabelID);
105 void emitPseudoInstruction(const MachineInstr &MI);
107 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
108 const TargetInstrDesc &TID,
109 const MachineOperand &MO,
112 unsigned getMachineSoImmOpValue(unsigned SoImm);
114 unsigned getAddrModeSBit(const MachineInstr &MI,
115 const TargetInstrDesc &TID) const;
117 void emitDataProcessingInstruction(const MachineInstr &MI,
118 unsigned ImplicitRd = 0,
119 unsigned ImplicitRn = 0);
121 void emitLoadStoreInstruction(const MachineInstr &MI,
122 unsigned ImplicitRd = 0,
123 unsigned ImplicitRn = 0);
125 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
126 unsigned ImplicitRn = 0);
128 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
130 void emitMulFrmInstruction(const MachineInstr &MI);
132 void emitExtendInstruction(const MachineInstr &MI);
134 void emitMiscArithInstruction(const MachineInstr &MI);
136 void emitBranchInstruction(const MachineInstr &MI);
138 void emitInlineJumpTable(unsigned JTIndex);
140 void emitMiscBranchInstruction(const MachineInstr &MI);
142 void emitVFPArithInstruction(const MachineInstr &MI);
144 void emitVFPConversionInstruction(const MachineInstr &MI);
146 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
148 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
150 void emitMiscInstruction(const MachineInstr &MI);
152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
154 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
161 unsigned getShiftOp(unsigned Imm) const ;
163 /// Routines that handle operands which add machine relocations which are
164 /// fixed up by the relocation stage.
165 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166 bool NeedStub, intptr_t ACPV = 0);
167 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171 intptr_t JTBase = 0);
173 template <class CodeEmitter>
174 char Emitter<CodeEmitter>::ID = 0;
177 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
178 /// to the specified MCE object.
180 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
181 MachineCodeEmitter &MCE) {
182 return new Emitter<MachineCodeEmitter>(TM, MCE);
184 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
185 JITCodeEmitter &JCE) {
186 return new Emitter<JITCodeEmitter>(TM, JCE);
188 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
189 ObjectCodeEmitter &OCE) {
190 return new Emitter<ObjectCodeEmitter>(TM, OCE);
193 template<class CodeEmitter>
194 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
195 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196 MF.getTarget().getRelocationModel() != Reloc::Static) &&
197 "JIT relocation model must be set to static or default!");
198 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
199 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
200 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
201 MCPEs = &MF.getConstantPool()->getConstants();
202 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204 JTI->Initialize(MF, IsPIC);
207 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
208 MCE.startFunction(MF);
209 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211 MCE.StartMachineBasicBlock(MBB);
212 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
216 } while (MCE.finishFunction(MF));
221 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223 template<class CodeEmitter>
224 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
225 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
226 default: llvm_unreachable("Unknown shift opc!");
227 case ARM_AM::asr: return 2;
228 case ARM_AM::lsl: return 0;
229 case ARM_AM::lsr: return 1;
231 case ARM_AM::rrx: return 3;
236 /// getMachineOpValue - Return binary encoding of operand. If the machine
237 /// operand requires relocation, record the relocation and return zero.
238 template<class CodeEmitter>
239 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
240 const MachineOperand &MO) {
242 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
244 return static_cast<unsigned>(MO.getImm());
245 else if (MO.isGlobal())
246 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
247 else if (MO.isSymbol())
248 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
249 else if (MO.isCPI()) {
250 const TargetInstrDesc &TID = MI.getDesc();
251 // For VFP load, the immediate offset is multiplied by 4.
252 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
253 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
254 emitConstPoolAddress(MO.getIndex(), Reloc);
255 } else if (MO.isJTI())
256 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
258 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
268 /// emitGlobalAddress - Emit the specified address to the code stream.
270 template<class CodeEmitter>
271 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
272 bool NeedStub, intptr_t ACPV) {
273 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
274 GV, ACPV, NeedStub));
277 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
278 /// be emitted to the current location in the function, and allow it to be PC
280 template<class CodeEmitter>
281 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
283 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
287 /// emitConstPoolAddress - Arrange for the address of an constant pool
288 /// to be emitted to the current location in the function, and allow it to be PC
290 template<class CodeEmitter>
291 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
293 // Tell JIT emitter we'll resolve the address.
294 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
295 Reloc, CPI, 0, true));
298 /// emitJumpTableAddress - Arrange for the address of a jump table to
299 /// be emitted to the current location in the function, and allow it to be PC
301 template<class CodeEmitter>
302 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
304 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
305 Reloc, JTIndex, 0, true));
308 /// emitMachineBasicBlock - Emit the specified address basic block.
309 template<class CodeEmitter>
310 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
311 unsigned Reloc, intptr_t JTBase) {
312 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
316 template<class CodeEmitter>
317 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
319 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
320 << Binary << std::dec << "\n";
322 MCE.emitWordLE(Binary);
325 template<class CodeEmitter>
326 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
328 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
329 << (unsigned)Binary << std::dec << "\n";
330 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
331 << (unsigned)(Binary >> 32) << std::dec << "\n";
333 MCE.emitDWordLE(Binary);
336 template<class CodeEmitter>
337 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
338 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
340 MCE.processDebugLoc(MI.getDebugLoc());
342 NumEmitted++; // Keep track of the # of mi's emitted
343 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
345 llvm_unreachable("Unhandled instruction encoding format!");
349 emitPseudoInstruction(MI);
352 case ARMII::DPSoRegFrm:
353 emitDataProcessingInstruction(MI);
357 emitLoadStoreInstruction(MI);
359 case ARMII::LdMiscFrm:
360 case ARMII::StMiscFrm:
361 emitMiscLoadStoreInstruction(MI);
363 case ARMII::LdStMulFrm:
364 emitLoadStoreMultipleInstruction(MI);
367 emitMulFrmInstruction(MI);
370 emitExtendInstruction(MI);
372 case ARMII::ArithMiscFrm:
373 emitMiscArithInstruction(MI);
376 emitBranchInstruction(MI);
378 case ARMII::BrMiscFrm:
379 emitMiscBranchInstruction(MI);
382 case ARMII::VFPUnaryFrm:
383 case ARMII::VFPBinaryFrm:
384 emitVFPArithInstruction(MI);
386 case ARMII::VFPConv1Frm:
387 case ARMII::VFPConv2Frm:
388 case ARMII::VFPConv3Frm:
389 case ARMII::VFPConv4Frm:
390 case ARMII::VFPConv5Frm:
391 emitVFPConversionInstruction(MI);
393 case ARMII::VFPLdStFrm:
394 emitVFPLoadStoreInstruction(MI);
396 case ARMII::VFPLdStMulFrm:
397 emitVFPLoadStoreMultipleInstruction(MI);
399 case ARMII::VFPMiscFrm:
400 emitMiscInstruction(MI);
405 template<class CodeEmitter>
406 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
407 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
408 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
409 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
411 // Remember the CONSTPOOL_ENTRY address for later relocation.
412 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
414 // Emit constpool island entry. In most cases, the actual values will be
415 // resolved and relocated after code emission.
416 if (MCPE.isMachineConstantPoolEntry()) {
417 ARMConstantPoolValue *ACPV =
418 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
420 DOUT << " ** ARM constant pool #" << CPI << " @ "
421 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
423 GlobalValue *GV = ACPV->getGV();
425 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
426 if (ACPV->isNonLazyPointer())
427 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
428 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
429 (intptr_t)ACPV, false));
431 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
432 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
434 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
435 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
439 Constant *CV = MCPE.Val.ConstVal;
442 DOUT << " ** Constant pool #" << CPI << " @ "
443 << (void*)MCE.getCurrentPCValue() << " ";
444 if (const Function *F = dyn_cast<Function>(CV))
445 DOUT << F->getName();
451 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
452 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
454 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
455 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
457 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
458 if (CFP->getType() == Type::FloatTy)
459 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
460 else if (CFP->getType() == Type::DoubleTy)
461 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
463 llvm_unreachable("Unable to handle this constantpool entry!");
466 llvm_unreachable("Unable to handle this constantpool entry!");
471 template<class CodeEmitter>
472 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
473 const MachineOperand &MO0 = MI.getOperand(0);
474 const MachineOperand &MO1 = MI.getOperand(1);
475 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
476 "Not a valid so_imm value!");
477 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
478 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
480 // Emit the 'mov' instruction.
481 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
483 // Set the conditional execution predicate.
484 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
487 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
490 // Set bit I(25) to identify this is the immediate form of <shifter_op>
491 Binary |= 1 << ARMII::I_BitShift;
492 Binary |= getMachineSoImmOpValue(V1);
495 // Now the 'orr' instruction.
496 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
498 // Set the conditional execution predicate.
499 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
502 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
505 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
508 // Set bit I(25) to identify this is the immediate form of <shifter_op>
509 Binary |= 1 << ARMII::I_BitShift;
510 Binary |= getMachineSoImmOpValue(V2);
514 template<class CodeEmitter>
515 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
516 // It's basically add r, pc, (LJTI - $+8)
518 const TargetInstrDesc &TID = MI.getDesc();
520 // Emit the 'add' instruction.
521 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
523 // Set the conditional execution predicate
524 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
526 // Encode S bit if MI modifies CPSR.
527 Binary |= getAddrModeSBit(MI, TID);
530 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
532 // Encode Rn which is PC.
533 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
535 // Encode the displacement.
536 Binary |= 1 << ARMII::I_BitShift;
537 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
542 template<class CodeEmitter>
543 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
544 unsigned Opcode = MI.getDesc().Opcode;
546 // Part of binary is determined by TableGn.
547 unsigned Binary = getBinaryCodeForInstr(MI);
549 // Set the conditional execution predicate
550 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
552 // Encode S bit if MI modifies CPSR.
553 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
554 Binary |= 1 << ARMII::S_BitShift;
556 // Encode register def if there is one.
557 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
559 // Encode the shift operation.
566 case ARM::MOVsrl_flag:
568 Binary |= (0x2 << 4) | (1 << 7);
570 case ARM::MOVsra_flag:
572 Binary |= (0x4 << 4) | (1 << 7);
576 // Encode register Rm.
577 Binary |= getMachineOpValue(MI, 1);
582 template<class CodeEmitter>
583 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
584 DOUT << " ** LPC" << LabelID << " @ "
585 << (void*)MCE.getCurrentPCValue() << '\n';
586 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
589 template<class CodeEmitter>
590 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
591 unsigned Opcode = MI.getDesc().Opcode;
594 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
595 case TargetInstrInfo::INLINEASM: {
596 // We allow inline assembler nodes with empty bodies - they can
597 // implicitly define registers, which is ok for JIT.
598 if (MI.getOperand(0).getSymbolName()[0]) {
599 llvm_report_error("JIT does not support inline asm!");
603 case TargetInstrInfo::DBG_LABEL:
604 case TargetInstrInfo::EH_LABEL:
605 MCE.emitLabel(MI.getOperand(0).getImm());
607 case TargetInstrInfo::IMPLICIT_DEF:
608 case TargetInstrInfo::DECLARE:
612 case ARM::CONSTPOOL_ENTRY:
613 emitConstPoolInstruction(MI);
616 // Remember of the address of the PC label for relocation later.
617 addPCLabel(MI.getOperand(2).getImm());
618 // PICADD is just an add instruction that implicitly read pc.
619 emitDataProcessingInstruction(MI, 0, ARM::PC);
626 // Remember of the address of the PC label for relocation later.
627 addPCLabel(MI.getOperand(2).getImm());
628 // These are just load / store instructions that implicitly read pc.
629 emitLoadStoreInstruction(MI, 0, ARM::PC);
636 // Remember of the address of the PC label for relocation later.
637 addPCLabel(MI.getOperand(2).getImm());
638 // These are just load / store instructions that implicitly read pc.
639 emitMiscLoadStoreInstruction(MI, ARM::PC);
642 case ARM::MOVi2pieces:
643 // Two instructions to materialize a constant.
644 emitMOVi2piecesInstruction(MI);
646 case ARM::LEApcrelJT:
647 // Materialize jumptable address.
648 emitLEApcrelJTInstruction(MI);
651 case ARM::MOVsrl_flag:
652 case ARM::MOVsra_flag:
653 emitPseudoMoveInstruction(MI);
658 template<class CodeEmitter>
659 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
660 const MachineInstr &MI,
661 const TargetInstrDesc &TID,
662 const MachineOperand &MO,
664 unsigned Binary = getMachineOpValue(MI, MO);
666 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
667 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
668 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
670 // Encode the shift opcode.
672 unsigned Rs = MO1.getReg();
674 // Set shift operand (bit[7:4]).
679 // RRX - 0110 and bit[11:8] clear.
681 default: llvm_unreachable("Unknown shift opc!");
682 case ARM_AM::lsl: SBits = 0x1; break;
683 case ARM_AM::lsr: SBits = 0x3; break;
684 case ARM_AM::asr: SBits = 0x5; break;
685 case ARM_AM::ror: SBits = 0x7; break;
686 case ARM_AM::rrx: SBits = 0x6; break;
689 // Set shift operand (bit[6:4]).
695 default: llvm_unreachable("Unknown shift opc!");
696 case ARM_AM::lsl: SBits = 0x0; break;
697 case ARM_AM::lsr: SBits = 0x2; break;
698 case ARM_AM::asr: SBits = 0x4; break;
699 case ARM_AM::ror: SBits = 0x6; break;
702 Binary |= SBits << 4;
703 if (SOpc == ARM_AM::rrx)
706 // Encode the shift operation Rs or shift_imm (except rrx).
708 // Encode Rs bit[11:8].
709 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
711 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
714 // Encode shift_imm bit[11:7].
715 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
718 template<class CodeEmitter>
719 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
720 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
721 assert(SoImmVal != -1 && "Not a valid so_imm value!");
723 // Encode rotate_imm.
724 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
725 << ARMII::SoRotImmShift;
728 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
732 template<class CodeEmitter>
733 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
734 const TargetInstrDesc &TID) const {
735 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
736 const MachineOperand &MO = MI.getOperand(i-1);
737 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
738 return 1 << ARMII::S_BitShift;
743 template<class CodeEmitter>
744 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
745 const MachineInstr &MI,
747 unsigned ImplicitRn) {
748 const TargetInstrDesc &TID = MI.getDesc();
750 if (TID.Opcode == ARM::BFC) {
751 llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
754 // Part of binary is determined by TableGn.
755 unsigned Binary = getBinaryCodeForInstr(MI);
757 // Set the conditional execution predicate
758 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
760 // Encode S bit if MI modifies CPSR.
761 Binary |= getAddrModeSBit(MI, TID);
763 // Encode register def if there is one.
764 unsigned NumDefs = TID.getNumDefs();
767 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
769 // Special handling for implicit use (e.g. PC).
770 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
771 << ARMII::RegRdShift);
773 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
774 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
777 // Encode first non-shifter register operand if there is one.
778 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
781 // Special handling for implicit use (e.g. PC).
782 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
783 << ARMII::RegRnShift);
785 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
790 // Encode shifter operand.
791 const MachineOperand &MO = MI.getOperand(OpIdx);
792 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
794 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
799 // Encode register Rm.
800 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
805 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
810 template<class CodeEmitter>
811 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
812 const MachineInstr &MI,
814 unsigned ImplicitRn) {
815 const TargetInstrDesc &TID = MI.getDesc();
816 unsigned Form = TID.TSFlags & ARMII::FormMask;
817 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
819 // Part of binary is determined by TableGn.
820 unsigned Binary = getBinaryCodeForInstr(MI);
822 // Set the conditional execution predicate
823 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
827 // Operand 0 of a pre- and post-indexed store is the address base
828 // writeback. Skip it.
829 bool Skipped = false;
830 if (IsPrePost && Form == ARMII::StFrm) {
837 // Special handling for implicit use (e.g. PC).
838 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
839 << ARMII::RegRdShift);
841 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
843 // Set second operand
845 // Special handling for implicit use (e.g. PC).
846 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
847 << ARMII::RegRnShift);
849 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
851 // If this is a two-address operand, skip it. e.g. LDR_PRE.
852 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
855 const MachineOperand &MO2 = MI.getOperand(OpIdx);
856 unsigned AM2Opc = (ImplicitRn == ARM::PC)
857 ? 0 : MI.getOperand(OpIdx+1).getImm();
859 // Set bit U(23) according to sign of immed value (positive or negative).
860 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
862 if (!MO2.getReg()) { // is immediate
863 if (ARM_AM::getAM2Offset(AM2Opc))
864 // Set the value of offset_12 field
865 Binary |= ARM_AM::getAM2Offset(AM2Opc);
870 // Set bit I(25), because this is not in immediate enconding.
871 Binary |= 1 << ARMII::I_BitShift;
872 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
873 // Set bit[3:0] to the corresponding Rm register
874 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
876 // If this instr is in scaled register offset/index instruction, set
877 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
878 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
879 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
880 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
886 template<class CodeEmitter>
887 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
888 unsigned ImplicitRn) {
889 const TargetInstrDesc &TID = MI.getDesc();
890 unsigned Form = TID.TSFlags & ARMII::FormMask;
891 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
893 // Part of binary is determined by TableGn.
894 unsigned Binary = getBinaryCodeForInstr(MI);
896 // Set the conditional execution predicate
897 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
901 // Operand 0 of a pre- and post-indexed store is the address base
902 // writeback. Skip it.
903 bool Skipped = false;
904 if (IsPrePost && Form == ARMII::StMiscFrm) {
910 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
912 // Skip LDRD and STRD's second operand.
913 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
916 // Set second operand
918 // Special handling for implicit use (e.g. PC).
919 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
920 << ARMII::RegRnShift);
922 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
924 // If this is a two-address operand, skip it. e.g. LDRH_POST.
925 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
928 const MachineOperand &MO2 = MI.getOperand(OpIdx);
929 unsigned AM3Opc = (ImplicitRn == ARM::PC)
930 ? 0 : MI.getOperand(OpIdx+1).getImm();
932 // Set bit U(23) according to sign of immed value (positive or negative)
933 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
936 // If this instr is in register offset/index encoding, set bit[3:0]
937 // to the corresponding Rm register.
939 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
944 // This instr is in immediate offset/index encoding, set bit 22 to 1.
945 Binary |= 1 << ARMII::AM3_I_BitShift;
946 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
948 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
949 Binary |= (ImmOffs & 0xF); // immedL
955 static unsigned getAddrModeUPBits(unsigned Mode) {
958 // Set addressing mode by modifying bits U(23) and P(24)
959 // IA - Increment after - bit U = 1 and bit P = 0
960 // IB - Increment before - bit U = 1 and bit P = 1
961 // DA - Decrement after - bit U = 0 and bit P = 0
962 // DB - Decrement before - bit U = 0 and bit P = 1
964 default: llvm_unreachable("Unknown addressing sub-mode!");
965 case ARM_AM::da: break;
966 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
967 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
968 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
974 template<class CodeEmitter>
975 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
976 const MachineInstr &MI) {
977 // Part of binary is determined by TableGn.
978 unsigned Binary = getBinaryCodeForInstr(MI);
980 // Set the conditional execution predicate
981 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
983 // Set base address operand
984 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
986 // Set addressing mode by modifying bits U(23) and P(24)
987 const MachineOperand &MO = MI.getOperand(1);
988 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
991 if (ARM_AM::getAM4WBFlag(MO.getImm()))
992 Binary |= 0x1 << ARMII::W_BitShift;
995 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
996 const MachineOperand &MO = MI.getOperand(i);
997 if (!MO.isReg() || MO.isImplicit())
999 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1000 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1002 Binary |= 0x1 << RegNum;
1008 template<class CodeEmitter>
1009 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1010 const TargetInstrDesc &TID = MI.getDesc();
1012 // Part of binary is determined by TableGn.
1013 unsigned Binary = getBinaryCodeForInstr(MI);
1015 // Set the conditional execution predicate
1016 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1018 // Encode S bit if MI modifies CPSR.
1019 Binary |= getAddrModeSBit(MI, TID);
1021 // 32x32->64bit operations have two destination registers. The number
1022 // of register definitions will tell us if that's what we're dealing with.
1024 if (TID.getNumDefs() == 2)
1025 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1028 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1031 Binary |= getMachineOpValue(MI, OpIdx++);
1034 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1036 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1037 // it as Rn (for multiply, that's in the same offset as RdLo.
1038 if (TID.getNumOperands() > OpIdx &&
1039 !TID.OpInfo[OpIdx].isPredicate() &&
1040 !TID.OpInfo[OpIdx].isOptionalDef())
1041 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1046 template<class CodeEmitter>
1047 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1048 const TargetInstrDesc &TID = MI.getDesc();
1050 // Part of binary is determined by TableGn.
1051 unsigned Binary = getBinaryCodeForInstr(MI);
1053 // Set the conditional execution predicate
1054 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1059 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1061 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1062 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1064 // Two register operand form.
1066 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1069 Binary |= getMachineOpValue(MI, MO2);
1072 Binary |= getMachineOpValue(MI, MO1);
1075 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1076 if (MI.getOperand(OpIdx).isImm() &&
1077 !TID.OpInfo[OpIdx].isPredicate() &&
1078 !TID.OpInfo[OpIdx].isOptionalDef())
1079 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1084 template<class CodeEmitter>
1085 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1086 const TargetInstrDesc &TID = MI.getDesc();
1088 // Part of binary is determined by TableGn.
1089 unsigned Binary = getBinaryCodeForInstr(MI);
1091 // Set the conditional execution predicate
1092 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1097 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1099 const MachineOperand &MO = MI.getOperand(OpIdx++);
1100 if (OpIdx == TID.getNumOperands() ||
1101 TID.OpInfo[OpIdx].isPredicate() ||
1102 TID.OpInfo[OpIdx].isOptionalDef()) {
1103 // Encode Rm and it's done.
1104 Binary |= getMachineOpValue(MI, MO);
1110 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1113 Binary |= getMachineOpValue(MI, OpIdx++);
1115 // Encode shift_imm.
1116 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1117 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1118 Binary |= ShiftAmt << ARMII::ShiftShift;
1123 template<class CodeEmitter>
1124 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1125 const TargetInstrDesc &TID = MI.getDesc();
1127 if (TID.Opcode == ARM::TPsoft) {
1128 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1131 // Part of binary is determined by TableGn.
1132 unsigned Binary = getBinaryCodeForInstr(MI);
1134 // Set the conditional execution predicate
1135 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1137 // Set signed_immed_24 field
1138 Binary |= getMachineOpValue(MI, 0);
1143 template<class CodeEmitter>
1144 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1145 // Remember the base address of the inline jump table.
1146 uintptr_t JTBase = MCE.getCurrentPCValue();
1147 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1148 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1150 // Now emit the jump table entries.
1151 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1152 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1154 // DestBB address - JT base.
1155 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1157 // Absolute DestBB address.
1158 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1163 template<class CodeEmitter>
1164 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1165 const TargetInstrDesc &TID = MI.getDesc();
1167 // Handle jump tables.
1168 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1169 TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1170 // First emit a ldr pc, [] instruction.
1171 emitDataProcessingInstruction(MI, ARM::PC);
1173 // Then emit the inline jump table.
1175 (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1176 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1177 emitInlineJumpTable(JTIndex);
1179 } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1180 // First emit a ldr pc, [] instruction.
1181 emitLoadStoreInstruction(MI, ARM::PC);
1183 // Then emit the inline jump table.
1184 emitInlineJumpTable(MI.getOperand(3).getIndex());
1188 // Part of binary is determined by TableGn.
1189 unsigned Binary = getBinaryCodeForInstr(MI);
1191 // Set the conditional execution predicate
1192 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1194 if (TID.Opcode == ARM::BX_RET)
1195 // The return register is LR.
1196 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1198 // otherwise, set the return register
1199 Binary |= getMachineOpValue(MI, 0);
1204 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1205 unsigned RegD = MI.getOperand(OpIdx).getReg();
1206 unsigned Binary = 0;
1207 bool isSPVFP = false;
1208 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1210 Binary |= RegD << ARMII::RegRdShift;
1212 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1213 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1218 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1219 unsigned RegN = MI.getOperand(OpIdx).getReg();
1220 unsigned Binary = 0;
1221 bool isSPVFP = false;
1222 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1224 Binary |= RegN << ARMII::RegRnShift;
1226 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1227 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1232 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1233 unsigned RegM = MI.getOperand(OpIdx).getReg();
1234 unsigned Binary = 0;
1235 bool isSPVFP = false;
1236 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1240 Binary |= ((RegM & 0x1E) >> 1);
1241 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1246 template<class CodeEmitter>
1247 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1248 const TargetInstrDesc &TID = MI.getDesc();
1250 // Part of binary is determined by TableGn.
1251 unsigned Binary = getBinaryCodeForInstr(MI);
1253 // Set the conditional execution predicate
1254 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1257 assert((Binary & ARMII::D_BitShift) == 0 &&
1258 (Binary & ARMII::N_BitShift) == 0 &&
1259 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1262 Binary |= encodeVFPRd(MI, OpIdx++);
1264 // If this is a two-address operand, skip it, e.g. FMACD.
1265 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1269 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1270 Binary |= encodeVFPRn(MI, OpIdx++);
1272 if (OpIdx == TID.getNumOperands() ||
1273 TID.OpInfo[OpIdx].isPredicate() ||
1274 TID.OpInfo[OpIdx].isOptionalDef()) {
1275 // FCMPEZD etc. has only one operand.
1281 Binary |= encodeVFPRm(MI, OpIdx);
1286 template<class CodeEmitter>
1287 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1288 const MachineInstr &MI) {
1289 const TargetInstrDesc &TID = MI.getDesc();
1290 unsigned Form = TID.TSFlags & ARMII::FormMask;
1292 // Part of binary is determined by TableGn.
1293 unsigned Binary = getBinaryCodeForInstr(MI);
1295 // Set the conditional execution predicate
1296 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1300 case ARMII::VFPConv1Frm:
1301 case ARMII::VFPConv2Frm:
1302 case ARMII::VFPConv3Frm:
1304 Binary |= encodeVFPRd(MI, 0);
1306 case ARMII::VFPConv4Frm:
1308 Binary |= encodeVFPRn(MI, 0);
1310 case ARMII::VFPConv5Frm:
1312 Binary |= encodeVFPRm(MI, 0);
1318 case ARMII::VFPConv1Frm:
1320 Binary |= encodeVFPRm(MI, 1);
1322 case ARMII::VFPConv2Frm:
1323 case ARMII::VFPConv3Frm:
1325 Binary |= encodeVFPRn(MI, 1);
1327 case ARMII::VFPConv4Frm:
1328 case ARMII::VFPConv5Frm:
1330 Binary |= encodeVFPRd(MI, 1);
1334 if (Form == ARMII::VFPConv5Frm)
1336 Binary |= encodeVFPRn(MI, 2);
1337 else if (Form == ARMII::VFPConv3Frm)
1339 Binary |= encodeVFPRm(MI, 2);
1344 template<class CodeEmitter>
1345 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1346 // Part of binary is determined by TableGn.
1347 unsigned Binary = getBinaryCodeForInstr(MI);
1349 // Set the conditional execution predicate
1350 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1355 Binary |= encodeVFPRd(MI, OpIdx++);
1357 // Encode address base.
1358 const MachineOperand &Base = MI.getOperand(OpIdx++);
1359 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1361 // If there is a non-zero immediate offset, encode it.
1363 const MachineOperand &Offset = MI.getOperand(OpIdx);
1364 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1365 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1366 Binary |= 1 << ARMII::U_BitShift;
1373 // If immediate offset is omitted, default to +0.
1374 Binary |= 1 << ARMII::U_BitShift;
1379 template<class CodeEmitter>
1380 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1381 const MachineInstr &MI) {
1382 // Part of binary is determined by TableGn.
1383 unsigned Binary = getBinaryCodeForInstr(MI);
1385 // Set the conditional execution predicate
1386 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1388 // Set base address operand
1389 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1391 // Set addressing mode by modifying bits U(23) and P(24)
1392 const MachineOperand &MO = MI.getOperand(1);
1393 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1396 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1397 Binary |= 0x1 << ARMII::W_BitShift;
1399 // First register is encoded in Dd.
1400 Binary |= encodeVFPRd(MI, 4);
1402 // Number of registers are encoded in offset field.
1403 unsigned NumRegs = 1;
1404 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1405 const MachineOperand &MO = MI.getOperand(i);
1406 if (!MO.isReg() || MO.isImplicit())
1410 Binary |= NumRegs * 2;
1415 template<class CodeEmitter>
1416 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1417 // Part of binary is determined by TableGn.
1418 unsigned Binary = getBinaryCodeForInstr(MI);
1420 // Set the conditional execution predicate
1421 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1426 #include "ARMGenCodeEmitter.inc"