1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "jit"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMRelocations.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/JITCodeEmitter.h"
29 #include "llvm/CodeGen/ObjectCodeEmitter.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(NumEmitted, "Number of machine instructions emitted");
49 class ARMCodeEmitter {
51 /// getBinaryCodeForInstr - This function, generated by the
52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53 /// machine instructions.
54 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
57 template<class CodeEmitter>
58 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59 public ARMCodeEmitter {
61 const ARMInstrInfo *II;
65 const std::vector<MachineConstantPoolEntry> *MCPEs;
66 const std::vector<MachineJumpTableEntry> *MJTEs;
71 explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
72 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
73 MCE(mce), MCPEs(0), MJTEs(0),
74 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
75 Emitter(TargetMachine &tm, CodeEmitter &mce,
76 const ARMInstrInfo &ii, const TargetData &td)
77 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
78 MCE(mce), MCPEs(0), MJTEs(0),
79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
81 bool runOnMachineFunction(MachineFunction &MF);
83 virtual const char *getPassName() const {
84 return "ARM Machine Code Emitter";
87 void emitInstruction(const MachineInstr &MI);
91 void emitWordLE(unsigned Binary);
93 void emitDWordLE(uint64_t Binary);
95 void emitConstPoolInstruction(const MachineInstr &MI);
97 void emitMOVi2piecesInstruction(const MachineInstr &MI);
99 void emitLEApcrelJTInstruction(const MachineInstr &MI);
101 void emitPseudoMoveInstruction(const MachineInstr &MI);
103 void addPCLabel(unsigned LabelID);
105 void emitPseudoInstruction(const MachineInstr &MI);
107 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
108 const TargetInstrDesc &TID,
109 const MachineOperand &MO,
112 unsigned getMachineSoImmOpValue(unsigned SoImm);
114 unsigned getAddrModeSBit(const MachineInstr &MI,
115 const TargetInstrDesc &TID) const;
117 void emitDataProcessingInstruction(const MachineInstr &MI,
118 unsigned ImplicitRd = 0,
119 unsigned ImplicitRn = 0);
121 void emitLoadStoreInstruction(const MachineInstr &MI,
122 unsigned ImplicitRd = 0,
123 unsigned ImplicitRn = 0);
125 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
126 unsigned ImplicitRn = 0);
128 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
130 void emitMulFrmInstruction(const MachineInstr &MI);
132 void emitExtendInstruction(const MachineInstr &MI);
134 void emitMiscArithInstruction(const MachineInstr &MI);
136 void emitBranchInstruction(const MachineInstr &MI);
138 void emitInlineJumpTable(unsigned JTIndex);
140 void emitMiscBranchInstruction(const MachineInstr &MI);
142 void emitVFPArithInstruction(const MachineInstr &MI);
144 void emitVFPConversionInstruction(const MachineInstr &MI);
146 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
148 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
150 void emitMiscInstruction(const MachineInstr &MI);
152 /// getMachineOpValue - Return binary encoding of operand. If the machine
153 /// operand requires relocation, record the relocation and return zero.
154 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
156 return getMachineOpValue(MI, MI.getOperand(OpIdx));
159 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
161 unsigned getShiftOp(unsigned Imm) const ;
163 /// Routines that handle operands which add machine relocations which are
164 /// fixed up by the relocation stage.
165 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166 bool NeedStub, intptr_t ACPV = 0);
167 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168 void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171 intptr_t JTBase = 0);
173 template <class CodeEmitter>
174 char Emitter<CodeEmitter>::ID = 0;
177 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
178 /// to the specified MCE object.
180 FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
181 MachineCodeEmitter &MCE) {
182 return new Emitter<MachineCodeEmitter>(TM, MCE);
184 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
185 JITCodeEmitter &JCE) {
186 return new Emitter<JITCodeEmitter>(TM, JCE);
188 FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
189 ObjectCodeEmitter &OCE) {
190 return new Emitter<ObjectCodeEmitter>(TM, OCE);
193 template<class CodeEmitter>
194 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
195 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196 MF.getTarget().getRelocationModel() != Reloc::Static) &&
197 "JIT relocation model must be set to static or default!");
198 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
199 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
200 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
201 MCPEs = &MF.getConstantPool()->getConstants();
202 MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204 JTI->Initialize(MF, IsPIC);
207 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
208 MCE.startFunction(MF);
209 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211 MCE.StartMachineBasicBlock(MBB);
212 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
216 } while (MCE.finishFunction(MF));
221 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223 template<class CodeEmitter>
224 unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
225 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
226 default: llvm_unreachable("Unknown shift opc!");
227 case ARM_AM::asr: return 2;
228 case ARM_AM::lsl: return 0;
229 case ARM_AM::lsr: return 1;
231 case ARM_AM::rrx: return 3;
236 /// getMachineOpValue - Return binary encoding of operand. If the machine
237 /// operand requires relocation, record the relocation and return zero.
238 template<class CodeEmitter>
239 unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
240 const MachineOperand &MO) {
242 return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
244 return static_cast<unsigned>(MO.getImm());
245 else if (MO.isGlobal())
246 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
247 else if (MO.isSymbol())
248 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
249 else if (MO.isCPI()) {
250 const TargetInstrDesc &TID = MI.getDesc();
251 // For VFP load, the immediate offset is multiplied by 4.
252 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
253 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
254 emitConstPoolAddress(MO.getIndex(), Reloc);
255 } else if (MO.isJTI())
256 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
258 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
268 /// emitGlobalAddress - Emit the specified address to the code stream.
270 template<class CodeEmitter>
271 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
272 bool NeedStub, intptr_t ACPV) {
273 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
274 GV, ACPV, NeedStub));
277 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
278 /// be emitted to the current location in the function, and allow it to be PC
280 template<class CodeEmitter>
281 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
283 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
287 /// emitConstPoolAddress - Arrange for the address of an constant pool
288 /// to be emitted to the current location in the function, and allow it to be PC
290 template<class CodeEmitter>
291 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
293 // Tell JIT emitter we'll resolve the address.
294 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
295 Reloc, CPI, 0, true));
298 /// emitJumpTableAddress - Arrange for the address of a jump table to
299 /// be emitted to the current location in the function, and allow it to be PC
301 template<class CodeEmitter>
302 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
304 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
305 Reloc, JTIndex, 0, true));
308 /// emitMachineBasicBlock - Emit the specified address basic block.
309 template<class CodeEmitter>
310 void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
311 unsigned Reloc, intptr_t JTBase) {
312 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
316 template<class CodeEmitter>
317 void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
319 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
320 << Binary << std::dec << "\n";
322 MCE.emitWordLE(Binary);
325 template<class CodeEmitter>
326 void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
328 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
329 << (unsigned)Binary << std::dec << "\n";
330 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
331 << (unsigned)(Binary >> 32) << std::dec << "\n";
333 MCE.emitDWordLE(Binary);
336 template<class CodeEmitter>
337 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
338 DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
340 NumEmitted++; // Keep track of the # of mi's emitted
341 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
343 llvm_unreachable("Unhandled instruction encoding format!");
347 emitPseudoInstruction(MI);
350 case ARMII::DPSoRegFrm:
351 emitDataProcessingInstruction(MI);
355 emitLoadStoreInstruction(MI);
357 case ARMII::LdMiscFrm:
358 case ARMII::StMiscFrm:
359 emitMiscLoadStoreInstruction(MI);
361 case ARMII::LdStMulFrm:
362 emitLoadStoreMultipleInstruction(MI);
365 emitMulFrmInstruction(MI);
368 emitExtendInstruction(MI);
370 case ARMII::ArithMiscFrm:
371 emitMiscArithInstruction(MI);
374 emitBranchInstruction(MI);
376 case ARMII::BrMiscFrm:
377 emitMiscBranchInstruction(MI);
380 case ARMII::VFPUnaryFrm:
381 case ARMII::VFPBinaryFrm:
382 emitVFPArithInstruction(MI);
384 case ARMII::VFPConv1Frm:
385 case ARMII::VFPConv2Frm:
386 case ARMII::VFPConv3Frm:
387 case ARMII::VFPConv4Frm:
388 case ARMII::VFPConv5Frm:
389 emitVFPConversionInstruction(MI);
391 case ARMII::VFPLdStFrm:
392 emitVFPLoadStoreInstruction(MI);
394 case ARMII::VFPLdStMulFrm:
395 emitVFPLoadStoreMultipleInstruction(MI);
397 case ARMII::VFPMiscFrm:
398 emitMiscInstruction(MI);
403 template<class CodeEmitter>
404 void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
405 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
406 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
407 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
409 // Remember the CONSTPOOL_ENTRY address for later relocation.
410 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
412 // Emit constpool island entry. In most cases, the actual values will be
413 // resolved and relocated after code emission.
414 if (MCPE.isMachineConstantPoolEntry()) {
415 ARMConstantPoolValue *ACPV =
416 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
418 DOUT << " ** ARM constant pool #" << CPI << " @ "
419 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
421 GlobalValue *GV = ACPV->getGV();
423 assert(!ACPV->isStub() && "Don't know how to deal this yet!");
424 if (ACPV->isNonLazyPointer())
425 MCE.addRelocation(MachineRelocation::getIndirectSymbol(
426 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
427 (intptr_t)ACPV, false));
429 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
430 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
432 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
433 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
437 Constant *CV = MCPE.Val.ConstVal;
440 DOUT << " ** Constant pool #" << CPI << " @ "
441 << (void*)MCE.getCurrentPCValue() << " ";
442 if (const Function *F = dyn_cast<Function>(CV))
443 DOUT << F->getName();
449 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
450 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
452 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
453 uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
455 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
456 if (CFP->getType() == Type::FloatTy)
457 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
458 else if (CFP->getType() == Type::DoubleTy)
459 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
461 llvm_unreachable("Unable to handle this constantpool entry!");
464 llvm_unreachable("Unable to handle this constantpool entry!");
469 template<class CodeEmitter>
470 void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
471 const MachineOperand &MO0 = MI.getOperand(0);
472 const MachineOperand &MO1 = MI.getOperand(1);
473 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
474 "Not a valid so_imm value!");
475 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
476 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
478 // Emit the 'mov' instruction.
479 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
481 // Set the conditional execution predicate.
482 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
485 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
488 // Set bit I(25) to identify this is the immediate form of <shifter_op>
489 Binary |= 1 << ARMII::I_BitShift;
490 Binary |= getMachineSoImmOpValue(V1);
493 // Now the 'orr' instruction.
494 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
496 // Set the conditional execution predicate.
497 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
500 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
503 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
506 // Set bit I(25) to identify this is the immediate form of <shifter_op>
507 Binary |= 1 << ARMII::I_BitShift;
508 Binary |= getMachineSoImmOpValue(V2);
512 template<class CodeEmitter>
513 void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
514 // It's basically add r, pc, (LJTI - $+8)
516 const TargetInstrDesc &TID = MI.getDesc();
518 // Emit the 'add' instruction.
519 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
521 // Set the conditional execution predicate
522 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
524 // Encode S bit if MI modifies CPSR.
525 Binary |= getAddrModeSBit(MI, TID);
528 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
530 // Encode Rn which is PC.
531 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
533 // Encode the displacement.
534 Binary |= 1 << ARMII::I_BitShift;
535 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
540 template<class CodeEmitter>
541 void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
542 unsigned Opcode = MI.getDesc().Opcode;
544 // Part of binary is determined by TableGn.
545 unsigned Binary = getBinaryCodeForInstr(MI);
547 // Set the conditional execution predicate
548 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
550 // Encode S bit if MI modifies CPSR.
551 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
552 Binary |= 1 << ARMII::S_BitShift;
554 // Encode register def if there is one.
555 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
557 // Encode the shift operation.
564 case ARM::MOVsrl_flag:
566 Binary |= (0x2 << 4) | (1 << 7);
568 case ARM::MOVsra_flag:
570 Binary |= (0x4 << 4) | (1 << 7);
574 // Encode register Rm.
575 Binary |= getMachineOpValue(MI, 1);
580 template<class CodeEmitter>
581 void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
582 DOUT << " ** LPC" << LabelID << " @ "
583 << (void*)MCE.getCurrentPCValue() << '\n';
584 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
587 template<class CodeEmitter>
588 void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
589 unsigned Opcode = MI.getDesc().Opcode;
592 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
593 case TargetInstrInfo::INLINEASM: {
594 // We allow inline assembler nodes with empty bodies - they can
595 // implicitly define registers, which is ok for JIT.
596 if (MI.getOperand(0).getSymbolName()[0]) {
597 llvm_report_error("JIT does not support inline asm!");
601 case TargetInstrInfo::DBG_LABEL:
602 case TargetInstrInfo::EH_LABEL:
603 MCE.emitLabel(MI.getOperand(0).getImm());
605 case TargetInstrInfo::IMPLICIT_DEF:
606 case TargetInstrInfo::DECLARE:
610 case ARM::CONSTPOOL_ENTRY:
611 emitConstPoolInstruction(MI);
614 // Remember of the address of the PC label for relocation later.
615 addPCLabel(MI.getOperand(2).getImm());
616 // PICADD is just an add instruction that implicitly read pc.
617 emitDataProcessingInstruction(MI, 0, ARM::PC);
624 // Remember of the address of the PC label for relocation later.
625 addPCLabel(MI.getOperand(2).getImm());
626 // These are just load / store instructions that implicitly read pc.
627 emitLoadStoreInstruction(MI, 0, ARM::PC);
634 // Remember of the address of the PC label for relocation later.
635 addPCLabel(MI.getOperand(2).getImm());
636 // These are just load / store instructions that implicitly read pc.
637 emitMiscLoadStoreInstruction(MI, ARM::PC);
640 case ARM::MOVi2pieces:
641 // Two instructions to materialize a constant.
642 emitMOVi2piecesInstruction(MI);
644 case ARM::LEApcrelJT:
645 // Materialize jumptable address.
646 emitLEApcrelJTInstruction(MI);
649 case ARM::MOVsrl_flag:
650 case ARM::MOVsra_flag:
651 emitPseudoMoveInstruction(MI);
656 template<class CodeEmitter>
657 unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
658 const MachineInstr &MI,
659 const TargetInstrDesc &TID,
660 const MachineOperand &MO,
662 unsigned Binary = getMachineOpValue(MI, MO);
664 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
665 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
666 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
668 // Encode the shift opcode.
670 unsigned Rs = MO1.getReg();
672 // Set shift operand (bit[7:4]).
677 // RRX - 0110 and bit[11:8] clear.
679 default: llvm_unreachable("Unknown shift opc!");
680 case ARM_AM::lsl: SBits = 0x1; break;
681 case ARM_AM::lsr: SBits = 0x3; break;
682 case ARM_AM::asr: SBits = 0x5; break;
683 case ARM_AM::ror: SBits = 0x7; break;
684 case ARM_AM::rrx: SBits = 0x6; break;
687 // Set shift operand (bit[6:4]).
693 default: llvm_unreachable("Unknown shift opc!");
694 case ARM_AM::lsl: SBits = 0x0; break;
695 case ARM_AM::lsr: SBits = 0x2; break;
696 case ARM_AM::asr: SBits = 0x4; break;
697 case ARM_AM::ror: SBits = 0x6; break;
700 Binary |= SBits << 4;
701 if (SOpc == ARM_AM::rrx)
704 // Encode the shift operation Rs or shift_imm (except rrx).
706 // Encode Rs bit[11:8].
707 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
709 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
712 // Encode shift_imm bit[11:7].
713 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
716 template<class CodeEmitter>
717 unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
718 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
719 assert(SoImmVal != -1 && "Not a valid so_imm value!");
721 // Encode rotate_imm.
722 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
723 << ARMII::SoRotImmShift;
726 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
730 template<class CodeEmitter>
731 unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
732 const TargetInstrDesc &TID) const {
733 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
734 const MachineOperand &MO = MI.getOperand(i-1);
735 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
736 return 1 << ARMII::S_BitShift;
741 template<class CodeEmitter>
742 void Emitter<CodeEmitter>::emitDataProcessingInstruction(
743 const MachineInstr &MI,
745 unsigned ImplicitRn) {
746 const TargetInstrDesc &TID = MI.getDesc();
748 if (TID.Opcode == ARM::BFC) {
749 llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
752 // Part of binary is determined by TableGn.
753 unsigned Binary = getBinaryCodeForInstr(MI);
755 // Set the conditional execution predicate
756 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
758 // Encode S bit if MI modifies CPSR.
759 Binary |= getAddrModeSBit(MI, TID);
761 // Encode register def if there is one.
762 unsigned NumDefs = TID.getNumDefs();
765 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
767 // Special handling for implicit use (e.g. PC).
768 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
769 << ARMII::RegRdShift);
771 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
772 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
775 // Encode first non-shifter register operand if there is one.
776 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
779 // Special handling for implicit use (e.g. PC).
780 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
781 << ARMII::RegRnShift);
783 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
788 // Encode shifter operand.
789 const MachineOperand &MO = MI.getOperand(OpIdx);
790 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
792 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
797 // Encode register Rm.
798 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
803 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
808 template<class CodeEmitter>
809 void Emitter<CodeEmitter>::emitLoadStoreInstruction(
810 const MachineInstr &MI,
812 unsigned ImplicitRn) {
813 const TargetInstrDesc &TID = MI.getDesc();
814 unsigned Form = TID.TSFlags & ARMII::FormMask;
815 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
817 // Part of binary is determined by TableGn.
818 unsigned Binary = getBinaryCodeForInstr(MI);
820 // Set the conditional execution predicate
821 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
825 // Operand 0 of a pre- and post-indexed store is the address base
826 // writeback. Skip it.
827 bool Skipped = false;
828 if (IsPrePost && Form == ARMII::StFrm) {
835 // Special handling for implicit use (e.g. PC).
836 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
837 << ARMII::RegRdShift);
839 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
841 // Set second operand
843 // Special handling for implicit use (e.g. PC).
844 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
845 << ARMII::RegRnShift);
847 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
849 // If this is a two-address operand, skip it. e.g. LDR_PRE.
850 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
853 const MachineOperand &MO2 = MI.getOperand(OpIdx);
854 unsigned AM2Opc = (ImplicitRn == ARM::PC)
855 ? 0 : MI.getOperand(OpIdx+1).getImm();
857 // Set bit U(23) according to sign of immed value (positive or negative).
858 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
860 if (!MO2.getReg()) { // is immediate
861 if (ARM_AM::getAM2Offset(AM2Opc))
862 // Set the value of offset_12 field
863 Binary |= ARM_AM::getAM2Offset(AM2Opc);
868 // Set bit I(25), because this is not in immediate enconding.
869 Binary |= 1 << ARMII::I_BitShift;
870 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
871 // Set bit[3:0] to the corresponding Rm register
872 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
874 // If this instr is in scaled register offset/index instruction, set
875 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
876 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
877 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
878 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
884 template<class CodeEmitter>
885 void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
886 unsigned ImplicitRn) {
887 const TargetInstrDesc &TID = MI.getDesc();
888 unsigned Form = TID.TSFlags & ARMII::FormMask;
889 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
891 // Part of binary is determined by TableGn.
892 unsigned Binary = getBinaryCodeForInstr(MI);
894 // Set the conditional execution predicate
895 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
899 // Operand 0 of a pre- and post-indexed store is the address base
900 // writeback. Skip it.
901 bool Skipped = false;
902 if (IsPrePost && Form == ARMII::StMiscFrm) {
908 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
910 // Skip LDRD and STRD's second operand.
911 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
914 // Set second operand
916 // Special handling for implicit use (e.g. PC).
917 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
918 << ARMII::RegRnShift);
920 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
922 // If this is a two-address operand, skip it. e.g. LDRH_POST.
923 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
926 const MachineOperand &MO2 = MI.getOperand(OpIdx);
927 unsigned AM3Opc = (ImplicitRn == ARM::PC)
928 ? 0 : MI.getOperand(OpIdx+1).getImm();
930 // Set bit U(23) according to sign of immed value (positive or negative)
931 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
934 // If this instr is in register offset/index encoding, set bit[3:0]
935 // to the corresponding Rm register.
937 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
942 // This instr is in immediate offset/index encoding, set bit 22 to 1.
943 Binary |= 1 << ARMII::AM3_I_BitShift;
944 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
946 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
947 Binary |= (ImmOffs & 0xF); // immedL
953 static unsigned getAddrModeUPBits(unsigned Mode) {
956 // Set addressing mode by modifying bits U(23) and P(24)
957 // IA - Increment after - bit U = 1 and bit P = 0
958 // IB - Increment before - bit U = 1 and bit P = 1
959 // DA - Decrement after - bit U = 0 and bit P = 0
960 // DB - Decrement before - bit U = 0 and bit P = 1
962 default: llvm_unreachable("Unknown addressing sub-mode!");
963 case ARM_AM::da: break;
964 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
965 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
966 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
972 template<class CodeEmitter>
973 void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
974 const MachineInstr &MI) {
975 // Part of binary is determined by TableGn.
976 unsigned Binary = getBinaryCodeForInstr(MI);
978 // Set the conditional execution predicate
979 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
981 // Set base address operand
982 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
984 // Set addressing mode by modifying bits U(23) and P(24)
985 const MachineOperand &MO = MI.getOperand(1);
986 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
989 if (ARM_AM::getAM4WBFlag(MO.getImm()))
990 Binary |= 0x1 << ARMII::W_BitShift;
993 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
994 const MachineOperand &MO = MI.getOperand(i);
995 if (!MO.isReg() || MO.isImplicit())
997 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
998 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1000 Binary |= 0x1 << RegNum;
1006 template<class CodeEmitter>
1007 void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1008 const TargetInstrDesc &TID = MI.getDesc();
1010 // Part of binary is determined by TableGn.
1011 unsigned Binary = getBinaryCodeForInstr(MI);
1013 // Set the conditional execution predicate
1014 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1016 // Encode S bit if MI modifies CPSR.
1017 Binary |= getAddrModeSBit(MI, TID);
1019 // 32x32->64bit operations have two destination registers. The number
1020 // of register definitions will tell us if that's what we're dealing with.
1022 if (TID.getNumDefs() == 2)
1023 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1026 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1029 Binary |= getMachineOpValue(MI, OpIdx++);
1032 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1034 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1035 // it as Rn (for multiply, that's in the same offset as RdLo.
1036 if (TID.getNumOperands() > OpIdx &&
1037 !TID.OpInfo[OpIdx].isPredicate() &&
1038 !TID.OpInfo[OpIdx].isOptionalDef())
1039 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1044 template<class CodeEmitter>
1045 void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1046 const TargetInstrDesc &TID = MI.getDesc();
1048 // Part of binary is determined by TableGn.
1049 unsigned Binary = getBinaryCodeForInstr(MI);
1051 // Set the conditional execution predicate
1052 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1057 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1059 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1060 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1062 // Two register operand form.
1064 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1067 Binary |= getMachineOpValue(MI, MO2);
1070 Binary |= getMachineOpValue(MI, MO1);
1073 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1074 if (MI.getOperand(OpIdx).isImm() &&
1075 !TID.OpInfo[OpIdx].isPredicate() &&
1076 !TID.OpInfo[OpIdx].isOptionalDef())
1077 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1082 template<class CodeEmitter>
1083 void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1084 const TargetInstrDesc &TID = MI.getDesc();
1086 // Part of binary is determined by TableGn.
1087 unsigned Binary = getBinaryCodeForInstr(MI);
1089 // Set the conditional execution predicate
1090 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1095 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1097 const MachineOperand &MO = MI.getOperand(OpIdx++);
1098 if (OpIdx == TID.getNumOperands() ||
1099 TID.OpInfo[OpIdx].isPredicate() ||
1100 TID.OpInfo[OpIdx].isOptionalDef()) {
1101 // Encode Rm and it's done.
1102 Binary |= getMachineOpValue(MI, MO);
1108 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1111 Binary |= getMachineOpValue(MI, OpIdx++);
1113 // Encode shift_imm.
1114 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1115 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1116 Binary |= ShiftAmt << ARMII::ShiftShift;
1121 template<class CodeEmitter>
1122 void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1123 const TargetInstrDesc &TID = MI.getDesc();
1125 if (TID.Opcode == ARM::TPsoft) {
1126 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1129 // Part of binary is determined by TableGn.
1130 unsigned Binary = getBinaryCodeForInstr(MI);
1132 // Set the conditional execution predicate
1133 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1135 // Set signed_immed_24 field
1136 Binary |= getMachineOpValue(MI, 0);
1141 template<class CodeEmitter>
1142 void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1143 // Remember the base address of the inline jump table.
1144 uintptr_t JTBase = MCE.getCurrentPCValue();
1145 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1146 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1148 // Now emit the jump table entries.
1149 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1150 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1152 // DestBB address - JT base.
1153 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1155 // Absolute DestBB address.
1156 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1161 template<class CodeEmitter>
1162 void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1163 const TargetInstrDesc &TID = MI.getDesc();
1165 // Handle jump tables.
1166 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1167 TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1168 // First emit a ldr pc, [] instruction.
1169 emitDataProcessingInstruction(MI, ARM::PC);
1171 // Then emit the inline jump table.
1173 (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1174 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1175 emitInlineJumpTable(JTIndex);
1177 } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1178 // First emit a ldr pc, [] instruction.
1179 emitLoadStoreInstruction(MI, ARM::PC);
1181 // Then emit the inline jump table.
1182 emitInlineJumpTable(MI.getOperand(3).getIndex());
1186 // Part of binary is determined by TableGn.
1187 unsigned Binary = getBinaryCodeForInstr(MI);
1189 // Set the conditional execution predicate
1190 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1192 if (TID.Opcode == ARM::BX_RET)
1193 // The return register is LR.
1194 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1196 // otherwise, set the return register
1197 Binary |= getMachineOpValue(MI, 0);
1202 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1203 unsigned RegD = MI.getOperand(OpIdx).getReg();
1204 unsigned Binary = 0;
1205 bool isSPVFP = false;
1206 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1208 Binary |= RegD << ARMII::RegRdShift;
1210 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1211 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1216 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1217 unsigned RegN = MI.getOperand(OpIdx).getReg();
1218 unsigned Binary = 0;
1219 bool isSPVFP = false;
1220 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1222 Binary |= RegN << ARMII::RegRnShift;
1224 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1225 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1230 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1231 unsigned RegM = MI.getOperand(OpIdx).getReg();
1232 unsigned Binary = 0;
1233 bool isSPVFP = false;
1234 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1238 Binary |= ((RegM & 0x1E) >> 1);
1239 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1244 template<class CodeEmitter>
1245 void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1246 const TargetInstrDesc &TID = MI.getDesc();
1248 // Part of binary is determined by TableGn.
1249 unsigned Binary = getBinaryCodeForInstr(MI);
1251 // Set the conditional execution predicate
1252 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1255 assert((Binary & ARMII::D_BitShift) == 0 &&
1256 (Binary & ARMII::N_BitShift) == 0 &&
1257 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1260 Binary |= encodeVFPRd(MI, OpIdx++);
1262 // If this is a two-address operand, skip it, e.g. FMACD.
1263 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1267 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1268 Binary |= encodeVFPRn(MI, OpIdx++);
1270 if (OpIdx == TID.getNumOperands() ||
1271 TID.OpInfo[OpIdx].isPredicate() ||
1272 TID.OpInfo[OpIdx].isOptionalDef()) {
1273 // FCMPEZD etc. has only one operand.
1279 Binary |= encodeVFPRm(MI, OpIdx);
1284 template<class CodeEmitter>
1285 void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1286 const MachineInstr &MI) {
1287 const TargetInstrDesc &TID = MI.getDesc();
1288 unsigned Form = TID.TSFlags & ARMII::FormMask;
1290 // Part of binary is determined by TableGn.
1291 unsigned Binary = getBinaryCodeForInstr(MI);
1293 // Set the conditional execution predicate
1294 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1298 case ARMII::VFPConv1Frm:
1299 case ARMII::VFPConv2Frm:
1300 case ARMII::VFPConv3Frm:
1302 Binary |= encodeVFPRd(MI, 0);
1304 case ARMII::VFPConv4Frm:
1306 Binary |= encodeVFPRn(MI, 0);
1308 case ARMII::VFPConv5Frm:
1310 Binary |= encodeVFPRm(MI, 0);
1316 case ARMII::VFPConv1Frm:
1318 Binary |= encodeVFPRm(MI, 1);
1320 case ARMII::VFPConv2Frm:
1321 case ARMII::VFPConv3Frm:
1323 Binary |= encodeVFPRn(MI, 1);
1325 case ARMII::VFPConv4Frm:
1326 case ARMII::VFPConv5Frm:
1328 Binary |= encodeVFPRd(MI, 1);
1332 if (Form == ARMII::VFPConv5Frm)
1334 Binary |= encodeVFPRn(MI, 2);
1335 else if (Form == ARMII::VFPConv3Frm)
1337 Binary |= encodeVFPRm(MI, 2);
1342 template<class CodeEmitter>
1343 void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1344 // Part of binary is determined by TableGn.
1345 unsigned Binary = getBinaryCodeForInstr(MI);
1347 // Set the conditional execution predicate
1348 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1353 Binary |= encodeVFPRd(MI, OpIdx++);
1355 // Encode address base.
1356 const MachineOperand &Base = MI.getOperand(OpIdx++);
1357 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1359 // If there is a non-zero immediate offset, encode it.
1361 const MachineOperand &Offset = MI.getOperand(OpIdx);
1362 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1363 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1364 Binary |= 1 << ARMII::U_BitShift;
1371 // If immediate offset is omitted, default to +0.
1372 Binary |= 1 << ARMII::U_BitShift;
1377 template<class CodeEmitter>
1378 void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1379 const MachineInstr &MI) {
1380 // Part of binary is determined by TableGn.
1381 unsigned Binary = getBinaryCodeForInstr(MI);
1383 // Set the conditional execution predicate
1384 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1386 // Set base address operand
1387 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1389 // Set addressing mode by modifying bits U(23) and P(24)
1390 const MachineOperand &MO = MI.getOperand(1);
1391 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1394 if (ARM_AM::getAM5WBFlag(MO.getImm()))
1395 Binary |= 0x1 << ARMII::W_BitShift;
1397 // First register is encoded in Dd.
1398 Binary |= encodeVFPRd(MI, 4);
1400 // Number of registers are encoded in offset field.
1401 unsigned NumRegs = 1;
1402 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1403 const MachineOperand &MO = MI.getOperand(i);
1404 if (!MO.isReg() || MO.isImplicit())
1408 Binary |= NumRegs * 2;
1413 template<class CodeEmitter>
1414 void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1415 // Part of binary is determined by TableGn.
1416 unsigned Binary = getBinaryCodeForInstr(MI);
1418 // Set the conditional execution predicate
1419 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1424 #include "ARMGenCodeEmitter.inc"