1 //===-- ARMConstantIslandPass.cpp - ARM constant islands ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
17 #include "ARMMachineFunctionInfo.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "Thumb2InstrInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineJumpTableInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/Format.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
38 #define DEBUG_TYPE "arm-cp-islands"
40 STATISTIC(NumCPEs, "Number of constpool entries");
41 STATISTIC(NumSplit, "Number of uncond branches inserted");
42 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
43 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
44 STATISTIC(NumTBs, "Number of table branches generated");
45 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
46 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
47 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
48 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
49 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
53 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
54 cl::desc("Adjust basic block layout to better use TB[BH]"));
56 // FIXME: This option should be removed once it has received sufficient testing.
58 AlignConstantIslands("arm-align-constant-islands", cl::Hidden, cl::init(true),
59 cl::desc("Align constant islands in code"));
61 /// UnknownPadding - Return the worst case padding that could result from
62 /// unknown offset bits. This does not include alignment padding caused by
63 /// known offset bits.
65 /// @param LogAlign log2(alignment)
66 /// @param KnownBits Number of known low offset bits.
67 static inline unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits) {
68 if (KnownBits < LogAlign)
69 return (1u << LogAlign) - (1u << KnownBits);
74 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
75 /// requires constant pool entries to be scattered among the instructions
76 /// inside a function. To do this, it completely ignores the normal LLVM
77 /// constant pool; instead, it places constants wherever it feels like with
78 /// special instructions.
80 /// The terminology used in this pass includes:
81 /// Islands - Clumps of constants placed in the function.
82 /// Water - Potential places where an island could be formed.
83 /// CPE - A constant pool entry that has been placed somewhere, which
84 /// tracks a list of users.
85 class ARMConstantIslands : public MachineFunctionPass {
86 /// BasicBlockInfo - Information about the offset and size of a single
88 struct BasicBlockInfo {
89 /// Offset - Distance from the beginning of the function to the beginning
90 /// of this basic block.
92 /// Offsets are computed assuming worst case padding before an aligned
93 /// block. This means that subtracting basic block offsets always gives a
94 /// conservative estimate of the real distance which may be smaller.
96 /// Because worst case padding is used, the computed offset of an aligned
97 /// block may not actually be aligned.
100 /// Size - Size of the basic block in bytes. If the block contains
101 /// inline assembly, this is a worst case estimate.
103 /// The size does not include any alignment padding whether from the
104 /// beginning of the block, or from an aligned jump table at the end.
107 /// KnownBits - The number of low bits in Offset that are known to be
108 /// exact. The remaining bits of Offset are an upper bound.
111 /// Unalign - When non-zero, the block contains instructions (inline asm)
112 /// of unknown size. The real size may be smaller than Size bytes by a
113 /// multiple of 1 << Unalign.
116 /// PostAlign - When non-zero, the block terminator contains a .align
117 /// directive, so the end of the block is aligned to 1 << PostAlign
121 BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0),
124 /// Compute the number of known offset bits internally to this block.
125 /// This number should be used to predict worst case padding when
126 /// splitting the block.
127 unsigned internalKnownBits() const {
128 unsigned Bits = Unalign ? Unalign : KnownBits;
129 // If the block size isn't a multiple of the known bits, assume the
130 // worst case padding.
131 if (Size & ((1u << Bits) - 1))
132 Bits = countTrailingZeros(Size);
136 /// Compute the offset immediately following this block. If LogAlign is
137 /// specified, return the offset the successor block will get if it has
139 unsigned postOffset(unsigned LogAlign = 0) const {
140 unsigned PO = Offset + Size;
141 unsigned LA = std::max(unsigned(PostAlign), LogAlign);
144 // Add alignment padding from the terminator.
145 return PO + UnknownPadding(LA, internalKnownBits());
148 /// Compute the number of known low bits of postOffset. If this block
149 /// contains inline asm, the number of known bits drops to the
150 /// instruction alignment. An aligned terminator may increase the number
152 /// If LogAlign is given, also consider the alignment of the next block.
153 unsigned postKnownBits(unsigned LogAlign = 0) const {
154 return std::max(std::max(unsigned(PostAlign), LogAlign),
155 internalKnownBits());
159 std::vector<BasicBlockInfo> BBInfo;
161 /// WaterList - A sorted list of basic blocks where islands could be placed
162 /// (i.e. blocks that don't fall through to the following block, due
163 /// to a return, unreachable, or unconditional branch).
164 std::vector<MachineBasicBlock*> WaterList;
166 /// NewWaterList - The subset of WaterList that was created since the
167 /// previous iteration by inserting unconditional branches.
168 SmallSet<MachineBasicBlock*, 4> NewWaterList;
170 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
172 /// CPUser - One user of a constant pool, keeping the machine instruction
173 /// pointer, the constant pool being referenced, and the max displacement
174 /// allowed from the instruction to the CP. The HighWaterMark records the
175 /// highest basic block where a new CPEntry can be placed. To ensure this
176 /// pass terminates, the CP entries are initially placed at the end of the
177 /// function and then move monotonically to lower addresses. The
178 /// exception to this rule is when the current CP entry for a particular
179 /// CPUser is out of range, but there is another CP entry for the same
180 /// constant value in range. We want to use the existing in-range CP
181 /// entry, but if it later moves out of range, the search for new water
182 /// should resume where it left off. The HighWaterMark is used to record
187 MachineBasicBlock *HighWaterMark;
194 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
195 bool neg, bool soimm)
196 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
197 KnownAlignment(false) {
198 HighWaterMark = CPEMI->getParent();
200 /// getMaxDisp - Returns the maximum displacement supported by MI.
201 /// Correct for unknown alignment.
202 /// Conservatively subtract 2 bytes to handle weird alignment effects.
203 unsigned getMaxDisp() const {
204 return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
208 /// CPUsers - Keep track of all of the machine instructions that use various
209 /// constant pools and their max displacement.
210 std::vector<CPUser> CPUsers;
212 /// CPEntry - One per constant pool entry, keeping the machine instruction
213 /// pointer, the constpool index, and the number of CPUser's which
214 /// reference this entry.
219 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
220 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
223 /// CPEntries - Keep track of all of the constant pool entry machine
224 /// instructions. For each original constpool index (i.e. those that
225 /// existed upon entry to this pass), it keeps a vector of entries.
226 /// Original elements are cloned as we go along; the clones are
227 /// put in the vector of the original element, but have distinct CPIs.
228 std::vector<std::vector<CPEntry> > CPEntries;
230 /// ImmBranch - One per immediate branch, keeping the machine instruction
231 /// pointer, conditional or unconditional, the max displacement,
232 /// and (if isCond is true) the corresponding unconditional branch
236 unsigned MaxDisp : 31;
239 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
240 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
243 /// ImmBranches - Keep track of all the immediate branch instructions.
245 std::vector<ImmBranch> ImmBranches;
247 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
249 SmallVector<MachineInstr*, 4> PushPopMIs;
251 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
252 SmallVector<MachineInstr*, 4> T2JumpTables;
254 /// HasFarJump - True if any far jump instruction has been emitted during
255 /// the branch fix up pass.
259 MachineConstantPool *MCP;
260 const ARMBaseInstrInfo *TII;
261 const ARMSubtarget *STI;
262 ARMFunctionInfo *AFI;
268 ARMConstantIslands() : MachineFunctionPass(ID) {}
270 bool runOnMachineFunction(MachineFunction &MF) override;
272 const char *getPassName() const override {
273 return "ARM constant island placement and branch shortening pass";
277 void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
278 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
279 unsigned getCPELogAlign(const MachineInstr *CPEMI);
280 void scanFunctionJumpTables();
281 void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
282 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
283 void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
284 void adjustBBOffsetsAfter(MachineBasicBlock *BB);
285 bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
286 int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
287 bool findAvailableWater(CPUser&U, unsigned UserOffset,
288 water_iterator &WaterIter);
289 void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
290 MachineBasicBlock *&NewMBB);
291 bool handleConstantPoolUser(unsigned CPUserIndex);
292 void removeDeadCPEMI(MachineInstr *CPEMI);
293 bool removeUnusedCPEntries();
294 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
295 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
296 bool DoDump = false);
297 bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
298 CPUser &U, unsigned &Growth);
299 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
300 bool fixupImmediateBr(ImmBranch &Br);
301 bool fixupConditionalBr(ImmBranch &Br);
302 bool fixupUnconditionalBr(ImmBranch &Br);
303 bool undoLRSpillRestore();
304 bool mayOptimizeThumb2Instruction(const MachineInstr *MI) const;
305 bool optimizeThumb2Instructions();
306 bool optimizeThumb2Branches();
307 bool reorderThumb2JumpTables();
308 bool optimizeThumb2JumpTables();
309 MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB,
310 MachineBasicBlock *JTBB);
312 void computeBlockSize(MachineBasicBlock *MBB);
313 unsigned getOffsetOf(MachineInstr *MI) const;
314 unsigned getUserOffset(CPUser&) const;
318 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
319 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
320 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
322 return isOffsetInRange(UserOffset, TrialOffset,
323 U.getMaxDisp(), U.NegOk, U.IsSoImm);
326 char ARMConstantIslands::ID = 0;
329 /// verify - check BBOffsets, BBSizes, alignment of islands
330 void ARMConstantIslands::verify() {
332 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
334 MachineBasicBlock *MBB = MBBI;
335 unsigned MBBId = MBB->getNumber();
336 assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
338 DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
339 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
340 CPUser &U = CPUsers[i];
341 unsigned UserOffset = getUserOffset(U);
342 // Verify offset using the real max displacement without the safety
344 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk,
345 /* DoDump = */ true)) {
346 DEBUG(dbgs() << "OK\n");
349 DEBUG(dbgs() << "Out of range.\n");
352 llvm_unreachable("Constant pool entry out of range!");
357 /// print block size and offset information - debugging
358 void ARMConstantIslands::dumpBBs() {
360 for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
361 const BasicBlockInfo &BBI = BBInfo[J];
362 dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
363 << " kb=" << unsigned(BBI.KnownBits)
364 << " ua=" << unsigned(BBI.Unalign)
365 << " pa=" << unsigned(BBI.PostAlign)
366 << format(" size=%#x\n", BBInfo[J].Size);
371 /// createARMConstantIslandPass - returns an instance of the constpool
373 FunctionPass *llvm::createARMConstantIslandPass() {
374 return new ARMConstantIslands();
377 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
379 MCP = mf.getConstantPool();
381 DEBUG(dbgs() << "***** ARMConstantIslands: "
382 << MCP->getConstants().size() << " CP entries, aligned to "
383 << MCP->getConstantPoolAlignment() << " bytes *****\n");
385 TII = (const ARMBaseInstrInfo *)MF->getTarget()
388 AFI = MF->getInfo<ARMFunctionInfo>();
389 STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
391 isThumb = AFI->isThumbFunction();
392 isThumb1 = AFI->isThumb1OnlyFunction();
393 isThumb2 = AFI->isThumb2Function();
397 // This pass invalidates liveness information when it splits basic blocks.
398 MF->getRegInfo().invalidateLiveness();
400 // Renumber all of the machine basic blocks in the function, guaranteeing that
401 // the numbers agree with the position of the block in the function.
402 MF->RenumberBlocks();
404 // Try to reorder and otherwise adjust the block layout to make good use
405 // of the TB[BH] instructions.
406 bool MadeChange = false;
407 if (isThumb2 && AdjustJumpTableBlocks) {
408 scanFunctionJumpTables();
409 MadeChange |= reorderThumb2JumpTables();
410 // Data is out of date, so clear it. It'll be re-computed later.
411 T2JumpTables.clear();
412 // Blocks may have shifted around. Keep the numbering up to date.
413 MF->RenumberBlocks();
416 // Thumb1 functions containing constant pools get 4-byte alignment.
417 // This is so we can keep exact track of where the alignment padding goes.
419 // ARM and Thumb2 functions need to be 4-byte aligned.
421 MF->ensureAlignment(2); // 2 = log2(4)
423 // Perform the initial placement of the constant pool entries. To start with,
424 // we put them all at the end of the function.
425 std::vector<MachineInstr*> CPEMIs;
427 doInitialPlacement(CPEMIs);
429 /// The next UID to take is the first unused one.
430 AFI->initPICLabelUId(CPEMIs.size());
432 // Do the initial scan of the function, building up information about the
433 // sizes of each block, the location of all the water, and finding all of the
434 // constant pool users.
435 initializeFunctionInfo(CPEMIs);
440 /// Remove dead constant pool entries.
441 MadeChange |= removeUnusedCPEntries();
443 // Iteratively place constant pool entries and fix up branches until there
445 unsigned NoCPIters = 0, NoBRIters = 0;
447 DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
448 bool CPChange = false;
449 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
450 CPChange |= handleConstantPoolUser(i);
451 if (CPChange && ++NoCPIters > 30)
452 report_fatal_error("Constant Island pass failed to converge!");
455 // Clear NewWaterList now. If we split a block for branches, it should
456 // appear as "new water" for the next iteration of constant pool placement.
457 NewWaterList.clear();
459 DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
460 bool BRChange = false;
461 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
462 BRChange |= fixupImmediateBr(ImmBranches[i]);
463 if (BRChange && ++NoBRIters > 30)
464 report_fatal_error("Branch Fix Up pass failed to converge!");
467 if (!CPChange && !BRChange)
472 // Shrink 32-bit Thumb2 branch, load, and store instructions.
473 if (isThumb2 && !STI->prefers32BitThumb())
474 MadeChange |= optimizeThumb2Instructions();
476 // After a while, this might be made debug-only, but it is not expensive.
479 // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
480 // undo the spill / restore of LR if possible.
481 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
482 MadeChange |= undoLRSpillRestore();
484 // Save the mapping between original and cloned constpool entries.
485 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
486 for (unsigned j = 0, je = CPEntries[i].size(); j != je; ++j) {
487 const CPEntry & CPE = CPEntries[i][j];
488 AFI->recordCPEClone(i, CPE.CPI);
492 DEBUG(dbgs() << '\n'; dumpBBs());
500 T2JumpTables.clear();
505 /// doInitialPlacement - Perform the initial placement of the constant pool
506 /// entries. To start with, we put them all at the end of the function.
508 ARMConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) {
509 // Create the basic block to hold the CPE's.
510 MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
513 // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
514 unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
516 // Mark the basic block as required by the const-pool.
517 // If AlignConstantIslands isn't set, use 4-byte alignment for everything.
518 BB->setAlignment(AlignConstantIslands ? MaxAlign : 2);
520 // The function needs to be as aligned as the basic blocks. The linker may
521 // move functions around based on their alignment.
522 MF->ensureAlignment(BB->getAlignment());
524 // Order the entries in BB by descending alignment. That ensures correct
525 // alignment of all entries as long as BB is sufficiently aligned. Keep
526 // track of the insertion point for each alignment. We are going to bucket
527 // sort the entries as they are created.
528 SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
530 // Add all of the constants from the constant pool to the end block, use an
531 // identity mapping of CPI's to CPE's.
532 const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
534 const DataLayout &TD = *MF->getSubtarget().getDataLayout();
535 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
536 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
537 assert(Size >= 4 && "Too small constant pool entry");
538 unsigned Align = CPs[i].getAlignment();
539 assert(isPowerOf2_32(Align) && "Invalid alignment");
540 // Verify that all constant pool entries are a multiple of their alignment.
541 // If not, we would have to pad them out so that instructions stay aligned.
542 assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
544 // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
545 unsigned LogAlign = Log2_32(Align);
546 MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
547 MachineInstr *CPEMI =
548 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
549 .addImm(i).addConstantPoolIndex(i).addImm(Size);
550 CPEMIs.push_back(CPEMI);
552 // Ensure that future entries with higher alignment get inserted before
553 // CPEMI. This is bucket sort with iterators.
554 for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
555 if (InsPoint[a] == InsAt)
558 // Add a new CPEntry, but no corresponding CPUser yet.
559 std::vector<CPEntry> CPEs;
560 CPEs.push_back(CPEntry(CPEMI, i));
561 CPEntries.push_back(CPEs);
563 DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
564 << Size << ", align = " << Align <<'\n');
569 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
570 /// into the block immediately after it.
571 static bool BBHasFallthrough(MachineBasicBlock *MBB) {
572 // Get the next machine basic block in the function.
573 MachineFunction::iterator MBBI = MBB;
574 // Can't fall off end of function.
575 if (std::next(MBBI) == MBB->getParent()->end())
578 MachineBasicBlock *NextBB = std::next(MBBI);
579 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
580 E = MBB->succ_end(); I != E; ++I)
587 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
588 /// look up the corresponding CPEntry.
589 ARMConstantIslands::CPEntry
590 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
591 const MachineInstr *CPEMI) {
592 std::vector<CPEntry> &CPEs = CPEntries[CPI];
593 // Number of entries per constpool index should be small, just do a
595 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
596 if (CPEs[i].CPEMI == CPEMI)
602 /// getCPELogAlign - Returns the required alignment of the constant pool entry
603 /// represented by CPEMI. Alignment is measured in log2(bytes) units.
604 unsigned ARMConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) {
605 assert(CPEMI && CPEMI->getOpcode() == ARM::CONSTPOOL_ENTRY);
607 // Everything is 4-byte aligned unless AlignConstantIslands is set.
608 if (!AlignConstantIslands)
611 unsigned CPI = CPEMI->getOperand(1).getIndex();
612 assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
613 unsigned Align = MCP->getConstants()[CPI].getAlignment();
614 assert(isPowerOf2_32(Align) && "Invalid CPE alignment");
615 return Log2_32(Align);
618 /// scanFunctionJumpTables - Do a scan of the function, building up
619 /// information about the sizes of each block and the locations of all
621 void ARMConstantIslands::scanFunctionJumpTables() {
622 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
624 MachineBasicBlock &MBB = *MBBI;
626 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
628 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
629 T2JumpTables.push_back(I);
633 /// initializeFunctionInfo - Do the initial scan of the function, building up
634 /// information about the sizes of each block, the location of all the water,
635 /// and finding all of the constant pool users.
636 void ARMConstantIslands::
637 initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
639 BBInfo.resize(MF->getNumBlockIDs());
641 // First thing, compute the size of all basic blocks, and see if the function
642 // has any inline assembly in it. If so, we have to be conservative about
643 // alignment assumptions, as we don't know for sure the size of any
644 // instructions in the inline assembly.
645 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
648 // The known bits of the entry block offset are determined by the function
650 BBInfo.front().KnownBits = MF->getAlignment();
652 // Compute block offsets and known bits.
653 adjustBBOffsetsAfter(MF->begin());
655 // Now go back through the instructions and build up our data structures.
656 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
658 MachineBasicBlock &MBB = *MBBI;
660 // If this block doesn't fall through into the next MBB, then this is
661 // 'water' that a constant pool island could be placed.
662 if (!BBHasFallthrough(&MBB))
663 WaterList.push_back(&MBB);
665 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
667 if (I->isDebugValue())
670 int Opc = I->getOpcode();
678 continue; // Ignore other JT branches
680 T2JumpTables.push_back(I);
681 continue; // Does not get an entry in ImmBranches
712 // Record this immediate branch.
713 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
714 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
717 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
718 PushPopMIs.push_back(I);
720 if (Opc == ARM::CONSTPOOL_ENTRY)
723 // Scan the instructions for constant pool operands.
724 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
725 if (I->getOperand(op).isCPI()) {
726 // We found one. The addressing mode tells us the max displacement
727 // from the PC that this instruction permits.
729 // Basic size info comes from the TSFlags field.
733 bool IsSoImm = false;
737 llvm_unreachable("Unknown addressing mode for CP reference!");
739 // Taking the address of a CP entry.
741 // This takes a SoImm, which is 8 bit immediate rotated. We'll
742 // pretend the maximum offset is 255 * 4. Since each instruction
743 // 4 byte wide, this is always correct. We'll check for other
744 // displacements that fits in a SoImm as well.
750 case ARM::t2LEApcrel:
763 Bits = 12; // +-offset_12
769 Scale = 4; // +(offset_8*4)
775 Scale = 4; // +-(offset_8*4)
780 // Remember that this is a user of a CP entry.
781 unsigned CPI = I->getOperand(op).getIndex();
782 MachineInstr *CPEMI = CPEMIs[CPI];
783 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
784 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
786 // Increment corresponding CPEntry reference count.
787 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
788 assert(CPE && "Cannot find a corresponding CPEntry!");
791 // Instructions can only use one CP entry, don't bother scanning the
792 // rest of the operands.
799 /// computeBlockSize - Compute the size and some alignment information for MBB.
800 /// This function updates BBInfo directly.
801 void ARMConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {
802 BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
807 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
809 BBI.Size += TII->GetInstSizeInBytes(I);
810 // For inline asm, GetInstSizeInBytes returns a conservative estimate.
811 // The actual size may be smaller, but still a multiple of the instr size.
812 if (I->isInlineAsm())
813 BBI.Unalign = isThumb ? 1 : 2;
814 // Also consider instructions that may be shrunk later.
815 else if (isThumb && mayOptimizeThumb2Instruction(I))
819 // tBR_JTr contains a .align 2 directive.
820 if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) {
822 MBB->getParent()->ensureAlignment(2);
826 /// getOffsetOf - Return the current offset of the specified machine instruction
827 /// from the start of the function. This offset changes as stuff is moved
828 /// around inside the function.
829 unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
830 MachineBasicBlock *MBB = MI->getParent();
832 // The offset is composed of two things: the sum of the sizes of all MBB's
833 // before this instruction's block, and the offset from the start of the block
835 unsigned Offset = BBInfo[MBB->getNumber()].Offset;
837 // Sum instructions before MI in MBB.
838 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
839 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
840 Offset += TII->GetInstSizeInBytes(I);
845 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
847 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
848 const MachineBasicBlock *RHS) {
849 return LHS->getNumber() < RHS->getNumber();
852 /// updateForInsertedWaterBlock - When a block is newly inserted into the
853 /// machine function, it upsets all of the block numbers. Renumber the blocks
854 /// and update the arrays that parallel this numbering.
855 void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
856 // Renumber the MBB's to keep them consecutive.
857 NewBB->getParent()->RenumberBlocks(NewBB);
859 // Insert an entry into BBInfo to align it properly with the (newly
860 // renumbered) block numbers.
861 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
863 // Next, update WaterList. Specifically, we need to add NewMBB as having
864 // available water after it.
866 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
868 WaterList.insert(IP, NewBB);
872 /// Split the basic block containing MI into two blocks, which are joined by
873 /// an unconditional branch. Update data structures and renumber blocks to
874 /// account for this change and returns the newly created block.
875 MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
876 MachineBasicBlock *OrigBB = MI->getParent();
878 // Create a new MBB for the code after the OrigBB.
879 MachineBasicBlock *NewBB =
880 MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
881 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
882 MF->insert(MBBI, NewBB);
884 // Splice the instructions starting with MI over to NewBB.
885 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
887 // Add an unconditional branch from OrigBB to NewBB.
888 // Note the new unconditional branch is not being recorded.
889 // There doesn't seem to be meaningful DebugInfo available; this doesn't
890 // correspond to anything in the source.
891 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
893 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
895 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB)
896 .addImm(ARMCC::AL).addReg(0);
899 // Update the CFG. All succs of OrigBB are now succs of NewBB.
900 NewBB->transferSuccessors(OrigBB);
902 // OrigBB branches to NewBB.
903 OrigBB->addSuccessor(NewBB);
905 // Update internal data structures to account for the newly inserted MBB.
906 // This is almost the same as updateForInsertedWaterBlock, except that
907 // the Water goes after OrigBB, not NewBB.
908 MF->RenumberBlocks(NewBB);
910 // Insert an entry into BBInfo to align it properly with the (newly
911 // renumbered) block numbers.
912 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
914 // Next, update WaterList. Specifically, we need to add OrigMBB as having
915 // available water after it (but not if it's already there, which happens
916 // when splitting before a conditional branch that is followed by an
917 // unconditional branch - in that case we want to insert NewBB).
919 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
921 MachineBasicBlock* WaterBB = *IP;
922 if (WaterBB == OrigBB)
923 WaterList.insert(std::next(IP), NewBB);
925 WaterList.insert(IP, OrigBB);
926 NewWaterList.insert(OrigBB);
928 // Figure out how large the OrigBB is. As the first half of the original
929 // block, it cannot contain a tablejump. The size includes
930 // the new jump we added. (It should be possible to do this without
931 // recounting everything, but it's very confusing, and this is rarely
933 computeBlockSize(OrigBB);
935 // Figure out how large the NewMBB is. As the second half of the original
936 // block, it may contain a tablejump.
937 computeBlockSize(NewBB);
939 // All BBOffsets following these blocks must be modified.
940 adjustBBOffsetsAfter(OrigBB);
945 /// getUserOffset - Compute the offset of U.MI as seen by the hardware
946 /// displacement computation. Update U.KnownAlignment to match its current
947 /// basic block location.
948 unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
949 unsigned UserOffset = getOffsetOf(U.MI);
950 const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
951 unsigned KnownBits = BBI.internalKnownBits();
953 // The value read from PC is offset from the actual instruction address.
954 UserOffset += (isThumb ? 4 : 8);
956 // Because of inline assembly, we may not know the alignment (mod 4) of U.MI.
957 // Make sure U.getMaxDisp() returns a constrained range.
958 U.KnownAlignment = (KnownBits >= 2);
960 // On Thumb, offsets==2 mod 4 are rounded down by the hardware for
961 // purposes of the displacement computation; compensate for that here.
962 // For unknown alignments, getMaxDisp() constrains the range instead.
963 if (isThumb && U.KnownAlignment)
969 /// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
970 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
971 /// constant pool entry).
972 /// UserOffset is computed by getUserOffset above to include PC adjustments. If
973 /// the mod 4 alignment of UserOffset is not known, the uncertainty must be
974 /// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
975 bool ARMConstantIslands::isOffsetInRange(unsigned UserOffset,
976 unsigned TrialOffset, unsigned MaxDisp,
977 bool NegativeOK, bool IsSoImm) {
978 if (UserOffset <= TrialOffset) {
979 // User before the Trial.
980 if (TrialOffset - UserOffset <= MaxDisp)
982 // FIXME: Make use full range of soimm values.
983 } else if (NegativeOK) {
984 if (UserOffset - TrialOffset <= MaxDisp)
986 // FIXME: Make use full range of soimm values.
991 /// isWaterInRange - Returns true if a CPE placed after the specified
992 /// Water (a basic block) will be in range for the specific MI.
994 /// Compute how much the function will grow by inserting a CPE after Water.
995 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
996 MachineBasicBlock* Water, CPUser &U,
998 unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
999 unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
1000 unsigned NextBlockOffset, NextBlockAlignment;
1001 MachineFunction::const_iterator NextBlock = Water;
1002 if (++NextBlock == MF->end()) {
1003 NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
1004 NextBlockAlignment = 0;
1006 NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
1007 NextBlockAlignment = NextBlock->getAlignment();
1009 unsigned Size = U.CPEMI->getOperand(2).getImm();
1010 unsigned CPEEnd = CPEOffset + Size;
1012 // The CPE may be able to hide in the alignment padding before the next
1013 // block. It may also cause more padding to be required if it is more aligned
1014 // that the next block.
1015 if (CPEEnd > NextBlockOffset) {
1016 Growth = CPEEnd - NextBlockOffset;
1017 // Compute the padding that would go at the end of the CPE to align the next
1019 Growth += OffsetToAlignment(CPEEnd, 1u << NextBlockAlignment);
1021 // If the CPE is to be inserted before the instruction, that will raise
1022 // the offset of the instruction. Also account for unknown alignment padding
1023 // in blocks between CPE and the user.
1024 if (CPEOffset < UserOffset)
1025 UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
1027 // CPE fits in existing padding.
1030 return isOffsetInRange(UserOffset, CPEOffset, U);
1033 /// isCPEntryInRange - Returns true if the distance between specific MI and
1034 /// specific ConstPool entry instruction can fit in MI's displacement field.
1035 bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
1036 MachineInstr *CPEMI, unsigned MaxDisp,
1037 bool NegOk, bool DoDump) {
1038 unsigned CPEOffset = getOffsetOf(CPEMI);
1042 unsigned Block = MI->getParent()->getNumber();
1043 const BasicBlockInfo &BBI = BBInfo[Block];
1044 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1045 << " max delta=" << MaxDisp
1046 << format(" insn address=%#x", UserOffset)
1047 << " in BB#" << Block << ": "
1048 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1049 << format("CPE address=%#x offset=%+d: ", CPEOffset,
1050 int(CPEOffset-UserOffset));
1054 return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
1058 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
1059 /// unconditionally branches to its only successor.
1060 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
1061 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
1064 MachineBasicBlock *Succ = *MBB->succ_begin();
1065 MachineBasicBlock *Pred = *MBB->pred_begin();
1066 MachineInstr *PredMI = &Pred->back();
1067 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1068 || PredMI->getOpcode() == ARM::t2B)
1069 return PredMI->getOperand(0).getMBB() == Succ;
1074 void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
1075 unsigned BBNum = BB->getNumber();
1076 for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
1077 // Get the offset and known bits at the end of the layout predecessor.
1078 // Include the alignment of the current block.
1079 unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
1080 unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
1081 unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
1083 // This is where block i begins. Stop if the offset is already correct,
1084 // and we have updated 2 blocks. This is the maximum number of blocks
1085 // changed before calling this function.
1086 if (i > BBNum + 2 &&
1087 BBInfo[i].Offset == Offset &&
1088 BBInfo[i].KnownBits == KnownBits)
1091 BBInfo[i].Offset = Offset;
1092 BBInfo[i].KnownBits = KnownBits;
1096 /// decrementCPEReferenceCount - find the constant pool entry with index CPI
1097 /// and instruction CPEMI, and decrement its refcount. If the refcount
1098 /// becomes 0 remove the entry and instruction. Returns true if we removed
1099 /// the entry, false if we didn't.
1101 bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
1102 MachineInstr *CPEMI) {
1103 // Find the old entry. Eliminate it if it is no longer used.
1104 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
1105 assert(CPE && "Unexpected!");
1106 if (--CPE->RefCount == 0) {
1107 removeDeadCPEMI(CPEMI);
1108 CPE->CPEMI = nullptr;
1115 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
1116 /// if not, see if an in-range clone of the CPE is in range, and if so,
1117 /// change the data structures so the user references the clone. Returns:
1118 /// 0 = no existing entry found
1119 /// 1 = entry found, and there were no code insertions or deletions
1120 /// 2 = entry found, and there were code insertions or deletions
1121 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
1123 MachineInstr *UserMI = U.MI;
1124 MachineInstr *CPEMI = U.CPEMI;
1126 // Check to see if the CPE is already in-range.
1127 if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
1129 DEBUG(dbgs() << "In range\n");
1133 // No. Look for previously created clones of the CPE that are in range.
1134 unsigned CPI = CPEMI->getOperand(1).getIndex();
1135 std::vector<CPEntry> &CPEs = CPEntries[CPI];
1136 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
1137 // We already tried this one
1138 if (CPEs[i].CPEMI == CPEMI)
1140 // Removing CPEs can leave empty entries, skip
1141 if (CPEs[i].CPEMI == nullptr)
1143 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
1145 DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
1146 << CPEs[i].CPI << "\n");
1147 // Point the CPUser node to the replacement
1148 U.CPEMI = CPEs[i].CPEMI;
1149 // Change the CPI in the instruction operand to refer to the clone.
1150 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
1151 if (UserMI->getOperand(j).isCPI()) {
1152 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1155 // Adjust the refcount of the clone...
1157 // ...and the original. If we didn't remove the old entry, none of the
1158 // addresses changed, so we don't need another pass.
1159 return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
1165 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1166 /// the specific unconditional branch instruction.
1167 static inline unsigned getUnconditionalBrDisp(int Opc) {
1170 return ((1<<10)-1)*2;
1172 return ((1<<23)-1)*2;
1177 return ((1<<23)-1)*4;
1180 /// findAvailableWater - Look for an existing entry in the WaterList in which
1181 /// we can place the CPE referenced from U so it's within range of U's MI.
1182 /// Returns true if found, false if not. If it returns true, WaterIter
1183 /// is set to the WaterList entry. For Thumb, prefer water that will not
1184 /// introduce padding to water that will. To ensure that this pass
1185 /// terminates, the CPE location for a particular CPUser is only allowed to
1186 /// move to a lower address, so search backward from the end of the list and
1187 /// prefer the first water that is in range.
1188 bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
1189 water_iterator &WaterIter) {
1190 if (WaterList.empty())
1193 unsigned BestGrowth = ~0u;
1194 for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
1196 MachineBasicBlock* WaterBB = *IP;
1197 // Check if water is in range and is either at a lower address than the
1198 // current "high water mark" or a new water block that was created since
1199 // the previous iteration by inserting an unconditional branch. In the
1200 // latter case, we want to allow resetting the high water mark back to
1201 // this new water since we haven't seen it before. Inserting branches
1202 // should be relatively uncommon and when it does happen, we want to be
1203 // sure to take advantage of it for all the CPEs near that block, so that
1204 // we don't insert more branches than necessary.
1206 if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
1207 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1208 NewWaterList.count(WaterBB)) && Growth < BestGrowth) {
1209 // This is the least amount of required padding seen so far.
1210 BestGrowth = Growth;
1212 DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
1213 << " Growth=" << Growth << '\n');
1215 // Keep looking unless it is perfect.
1216 if (BestGrowth == 0)
1222 return BestGrowth != ~0u;
1225 /// createNewWater - No existing WaterList entry will work for
1226 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1227 /// block is used if in range, and the conditional branch munged so control
1228 /// flow is correct. Otherwise the block is split to create a hole with an
1229 /// unconditional branch around it. In either case NewMBB is set to a
1230 /// block following which the new island can be inserted (the WaterList
1231 /// is not adjusted).
1232 void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
1233 unsigned UserOffset,
1234 MachineBasicBlock *&NewMBB) {
1235 CPUser &U = CPUsers[CPUserIndex];
1236 MachineInstr *UserMI = U.MI;
1237 MachineInstr *CPEMI = U.CPEMI;
1238 unsigned CPELogAlign = getCPELogAlign(CPEMI);
1239 MachineBasicBlock *UserMBB = UserMI->getParent();
1240 const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
1242 // If the block does not end in an unconditional branch already, and if the
1243 // end of the block is within range, make new water there. (The addition
1244 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1245 // Thumb2, 2 on Thumb1.
1246 if (BBHasFallthrough(UserMBB)) {
1247 // Size of branch to insert.
1248 unsigned Delta = isThumb1 ? 2 : 4;
1249 // Compute the offset where the CPE will begin.
1250 unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
1252 if (isOffsetInRange(UserOffset, CPEOffset, U)) {
1253 DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
1254 << format(", expected CPE offset %#x\n", CPEOffset));
1255 NewMBB = std::next(MachineFunction::iterator(UserMBB));
1256 // Add an unconditional branch from UserMBB to fallthrough block. Record
1257 // it for branch lengthening; this new branch will not get out of range,
1258 // but if the preceding conditional branch is out of range, the targets
1259 // will be exchanged, and the altered branch may be out of range, so the
1260 // machinery has to know about it.
1261 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1263 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1265 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB)
1266 .addImm(ARMCC::AL).addReg(0);
1267 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1268 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1269 MaxDisp, false, UncondBr));
1270 BBInfo[UserMBB->getNumber()].Size += Delta;
1271 adjustBBOffsetsAfter(UserMBB);
1276 // What a big block. Find a place within the block to split it. This is a
1277 // little tricky on Thumb1 since instructions are 2 bytes and constant pool
1278 // entries are 4 bytes: if instruction I references island CPE, and
1279 // instruction I+1 references CPE', it will not work well to put CPE as far
1280 // forward as possible, since then CPE' cannot immediately follow it (that
1281 // location is 2 bytes farther away from I+1 than CPE was from I) and we'd
1282 // need to create a new island. So, we make a first guess, then walk through
1283 // the instructions between the one currently being looked at and the
1284 // possible insertion point, and make sure any other instructions that
1285 // reference CPEs will be able to use the same island area; if not, we back
1286 // up the insertion point.
1288 // Try to split the block so it's fully aligned. Compute the latest split
1289 // point where we can add a 4-byte branch instruction, and then align to
1290 // LogAlign which is the largest possible alignment in the function.
1291 unsigned LogAlign = MF->getAlignment();
1292 assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
1293 unsigned KnownBits = UserBBI.internalKnownBits();
1294 unsigned UPad = UnknownPadding(LogAlign, KnownBits);
1295 unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
1296 DEBUG(dbgs() << format("Split in middle of big block before %#x",
1299 // The 4 in the following is for the unconditional branch we'll be inserting
1300 // (allows for long branch on Thumb1). Alignment of the island is handled
1301 // inside isOffsetInRange.
1302 BaseInsertOffset -= 4;
1304 DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
1305 << " la=" << LogAlign
1306 << " kb=" << KnownBits
1307 << " up=" << UPad << '\n');
1309 // This could point off the end of the block if we've already got constant
1310 // pool entries following this block; only the last one is in the water list.
1311 // Back past any possible branches (allow for a conditional and a maximally
1312 // long unconditional).
1313 if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
1314 BaseInsertOffset = UserBBI.postOffset() - UPad - 8;
1315 DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
1317 unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
1318 CPEMI->getOperand(2).getImm();
1319 MachineBasicBlock::iterator MI = UserMI;
1321 unsigned CPUIndex = CPUserIndex+1;
1322 unsigned NumCPUsers = CPUsers.size();
1323 MachineInstr *LastIT = nullptr;
1324 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1325 Offset < BaseInsertOffset;
1326 Offset += TII->GetInstSizeInBytes(MI), MI = std::next(MI)) {
1327 assert(MI != UserMBB->end() && "Fell off end of block");
1328 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
1329 CPUser &U = CPUsers[CPUIndex];
1330 if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
1331 // Shift intertion point by one unit of alignment so it is within reach.
1332 BaseInsertOffset -= 1u << LogAlign;
1333 EndInsertOffset -= 1u << LogAlign;
1335 // This is overly conservative, as we don't account for CPEMIs being
1336 // reused within the block, but it doesn't matter much. Also assume CPEs
1337 // are added in order with alignment padding. We may eventually be able
1338 // to pack the aligned CPEs better.
1339 EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1343 // Remember the last IT instruction.
1344 if (MI->getOpcode() == ARM::t2IT)
1350 // Avoid splitting an IT block.
1352 unsigned PredReg = 0;
1353 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
1354 if (CC != ARMCC::AL)
1357 NewMBB = splitBlockBeforeInstr(MI);
1360 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
1361 /// is out-of-range. If so, pick up the constant pool value and move it some
1362 /// place in-range. Return true if we changed any addresses (thus must run
1363 /// another pass of branch lengthening), false otherwise.
1364 bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
1365 CPUser &U = CPUsers[CPUserIndex];
1366 MachineInstr *UserMI = U.MI;
1367 MachineInstr *CPEMI = U.CPEMI;
1368 unsigned CPI = CPEMI->getOperand(1).getIndex();
1369 unsigned Size = CPEMI->getOperand(2).getImm();
1370 // Compute this only once, it's expensive.
1371 unsigned UserOffset = getUserOffset(U);
1373 // See if the current entry is within range, or there is a clone of it
1375 int result = findInRangeCPEntry(U, UserOffset);
1376 if (result==1) return false;
1377 else if (result==2) return true;
1379 // No existing clone of this CPE is within range.
1380 // We will be generating a new clone. Get a UID for it.
1381 unsigned ID = AFI->createPICLabelUId();
1383 // Look for water where we can place this CPE.
1384 MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
1385 MachineBasicBlock *NewMBB;
1387 if (findAvailableWater(U, UserOffset, IP)) {
1388 DEBUG(dbgs() << "Found water in range\n");
1389 MachineBasicBlock *WaterBB = *IP;
1391 // If the original WaterList entry was "new water" on this iteration,
1392 // propagate that to the new island. This is just keeping NewWaterList
1393 // updated to match the WaterList, which will be updated below.
1394 if (NewWaterList.erase(WaterBB))
1395 NewWaterList.insert(NewIsland);
1397 // The new CPE goes before the following block (NewMBB).
1398 NewMBB = std::next(MachineFunction::iterator(WaterBB));
1402 DEBUG(dbgs() << "No water found\n");
1403 createNewWater(CPUserIndex, UserOffset, NewMBB);
1405 // splitBlockBeforeInstr adds to WaterList, which is important when it is
1406 // called while handling branches so that the water will be seen on the
1407 // next iteration for constant pools, but in this context, we don't want
1408 // it. Check for this so it will be removed from the WaterList.
1409 // Also remove any entry from NewWaterList.
1410 MachineBasicBlock *WaterBB = std::prev(MachineFunction::iterator(NewMBB));
1411 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
1412 if (IP != WaterList.end())
1413 NewWaterList.erase(WaterBB);
1415 // We are adding new water. Update NewWaterList.
1416 NewWaterList.insert(NewIsland);
1419 // Remove the original WaterList entry; we want subsequent insertions in
1420 // this vicinity to go after the one we're about to insert. This
1421 // considerably reduces the number of times we have to move the same CPE
1422 // more than once and is also important to ensure the algorithm terminates.
1423 if (IP != WaterList.end())
1424 WaterList.erase(IP);
1426 // Okay, we know we can put an island before NewMBB now, do it!
1427 MF->insert(NewMBB, NewIsland);
1429 // Update internal data structures to account for the newly inserted MBB.
1430 updateForInsertedWaterBlock(NewIsland);
1432 // Decrement the old entry, and remove it if refcount becomes 0.
1433 decrementCPEReferenceCount(CPI, CPEMI);
1435 // Now that we have an island to add the CPE to, clone the original CPE and
1436 // add it to the island.
1437 U.HighWaterMark = NewIsland;
1438 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
1439 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
1440 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1443 // Mark the basic block as aligned as required by the const-pool entry.
1444 NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
1446 // Increase the size of the island block to account for the new entry.
1447 BBInfo[NewIsland->getNumber()].Size += Size;
1448 adjustBBOffsetsAfter(std::prev(MachineFunction::iterator(NewIsland)));
1450 // Finally, change the CPI in the instruction operand to be ID.
1451 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1452 if (UserMI->getOperand(i).isCPI()) {
1453 UserMI->getOperand(i).setIndex(ID);
1457 DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
1458 << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
1463 /// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
1464 /// sizes and offsets of impacted basic blocks.
1465 void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
1466 MachineBasicBlock *CPEBB = CPEMI->getParent();
1467 unsigned Size = CPEMI->getOperand(2).getImm();
1468 CPEMI->eraseFromParent();
1469 BBInfo[CPEBB->getNumber()].Size -= Size;
1470 // All succeeding offsets have the current size value added in, fix this.
1471 if (CPEBB->empty()) {
1472 BBInfo[CPEBB->getNumber()].Size = 0;
1474 // This block no longer needs to be aligned.
1475 CPEBB->setAlignment(0);
1477 // Entries are sorted by descending alignment, so realign from the front.
1478 CPEBB->setAlignment(getCPELogAlign(CPEBB->begin()));
1480 adjustBBOffsetsAfter(CPEBB);
1481 // An island has only one predecessor BB and one successor BB. Check if
1482 // this BB's predecessor jumps directly to this BB's successor. This
1483 // shouldn't happen currently.
1484 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1485 // FIXME: remove the empty blocks after all the work is done?
1488 /// removeUnusedCPEntries - Remove constant pool entries whose refcounts
1490 bool ARMConstantIslands::removeUnusedCPEntries() {
1491 unsigned MadeChange = false;
1492 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1493 std::vector<CPEntry> &CPEs = CPEntries[i];
1494 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1495 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1496 removeDeadCPEMI(CPEs[j].CPEMI);
1497 CPEs[j].CPEMI = nullptr;
1505 /// isBBInRange - Returns true if the distance between specific MI and
1506 /// specific BB can fit in MI's displacement field.
1507 bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1509 unsigned PCAdj = isThumb ? 4 : 8;
1510 unsigned BrOffset = getOffsetOf(MI) + PCAdj;
1511 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1513 DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
1514 << " from BB#" << MI->getParent()->getNumber()
1515 << " max delta=" << MaxDisp
1516 << " from " << getOffsetOf(MI) << " to " << DestOffset
1517 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1519 if (BrOffset <= DestOffset) {
1520 // Branch before the Dest.
1521 if (DestOffset-BrOffset <= MaxDisp)
1524 if (BrOffset-DestOffset <= MaxDisp)
1530 /// fixupImmediateBr - Fix up an immediate branch whose destination is too far
1531 /// away to fit in its displacement field.
1532 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1533 MachineInstr *MI = Br.MI;
1534 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1536 // Check to see if the DestBB is already in-range.
1537 if (isBBInRange(MI, DestBB, Br.MaxDisp))
1541 return fixupUnconditionalBr(Br);
1542 return fixupConditionalBr(Br);
1545 /// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
1546 /// too far away to fit in its displacement field. If the LR register has been
1547 /// spilled in the epilogue, then we can use BL to implement a far jump.
1548 /// Otherwise, add an intermediate branch instruction to a branch.
1550 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1551 MachineInstr *MI = Br.MI;
1552 MachineBasicBlock *MBB = MI->getParent();
1554 llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
1556 // Use BL to implement far jump.
1557 Br.MaxDisp = (1 << 21) * 2;
1558 MI->setDesc(TII->get(ARM::tBfar));
1559 BBInfo[MBB->getNumber()].Size += 2;
1560 adjustBBOffsetsAfter(MBB);
1564 DEBUG(dbgs() << " Changed B to long jump " << *MI);
1569 /// fixupConditionalBr - Fix up a conditional branch whose destination is too
1570 /// far away to fit in its displacement field. It is converted to an inverse
1571 /// conditional branch + an unconditional branch to the destination.
1573 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1574 MachineInstr *MI = Br.MI;
1575 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1577 // Add an unconditional branch to the destination and invert the branch
1578 // condition to jump over it:
1584 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1585 CC = ARMCC::getOppositeCondition(CC);
1586 unsigned CCReg = MI->getOperand(2).getReg();
1588 // If the branch is at the end of its MBB and that has a fall-through block,
1589 // direct the updated conditional branch to the fall-through block. Otherwise,
1590 // split the MBB before the next instruction.
1591 MachineBasicBlock *MBB = MI->getParent();
1592 MachineInstr *BMI = &MBB->back();
1593 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1597 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
1598 BMI->getOpcode() == Br.UncondBr) {
1599 // Last MI in the BB is an unconditional branch. Can we simply invert the
1600 // condition and swap destinations:
1606 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1607 if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
1608 DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
1610 BMI->getOperand(0).setMBB(DestBB);
1611 MI->getOperand(0).setMBB(NewDest);
1612 MI->getOperand(1).setImm(CC);
1619 splitBlockBeforeInstr(MI);
1620 // No need for the branch to the next block. We're adding an unconditional
1621 // branch to the destination.
1622 int delta = TII->GetInstSizeInBytes(&MBB->back());
1623 BBInfo[MBB->getNumber()].Size -= delta;
1624 MBB->back().eraseFromParent();
1625 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
1627 MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
1629 DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
1630 << " also invert condition and change dest. to BB#"
1631 << NextBB->getNumber() << "\n");
1633 // Insert a new conditional branch and a new unconditional branch.
1634 // Also update the ImmBranch as well as adding a new entry for the new branch.
1635 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1636 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1637 Br.MI = &MBB->back();
1638 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
1640 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
1641 .addImm(ARMCC::AL).addReg(0);
1643 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1644 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
1645 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1646 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1648 // Remove the old conditional branch. It may or may not still be in MBB.
1649 BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
1650 MI->eraseFromParent();
1651 adjustBBOffsetsAfter(MBB);
1655 /// undoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1656 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1657 /// to do this if tBfar is not used.
1658 bool ARMConstantIslands::undoLRSpillRestore() {
1659 bool MadeChange = false;
1660 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1661 MachineInstr *MI = PushPopMIs[i];
1662 // First two operands are predicates.
1663 if (MI->getOpcode() == ARM::tPOP_RET &&
1664 MI->getOperand(2).getReg() == ARM::PC &&
1665 MI->getNumExplicitOperands() == 3) {
1666 // Create the new insn and copy the predicate from the old.
1667 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1668 .addOperand(MI->getOperand(0))
1669 .addOperand(MI->getOperand(1));
1670 MI->eraseFromParent();
1677 // mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions
1678 // below may shrink MI.
1680 ARMConstantIslands::mayOptimizeThumb2Instruction(const MachineInstr *MI) const {
1681 switch(MI->getOpcode()) {
1682 // optimizeThumb2Instructions.
1683 case ARM::t2LEApcrel:
1685 // optimizeThumb2Branches.
1689 // optimizeThumb2JumpTables.
1696 bool ARMConstantIslands::optimizeThumb2Instructions() {
1697 bool MadeChange = false;
1699 // Shrink ADR and LDR from constantpool.
1700 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1701 CPUser &U = CPUsers[i];
1702 unsigned Opcode = U.MI->getOpcode();
1703 unsigned NewOpc = 0;
1708 case ARM::t2LEApcrel:
1709 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1710 NewOpc = ARM::tLEApcrel;
1716 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1717 NewOpc = ARM::tLDRpci;
1727 unsigned UserOffset = getUserOffset(U);
1728 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1730 // Be conservative with inline asm.
1731 if (!U.KnownAlignment)
1734 // FIXME: Check if offset is multiple of scale if scale is not 4.
1735 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1736 DEBUG(dbgs() << "Shrink: " << *U.MI);
1737 U.MI->setDesc(TII->get(NewOpc));
1738 MachineBasicBlock *MBB = U.MI->getParent();
1739 BBInfo[MBB->getNumber()].Size -= 2;
1740 adjustBBOffsetsAfter(MBB);
1746 MadeChange |= optimizeThumb2Branches();
1747 MadeChange |= optimizeThumb2JumpTables();
1751 bool ARMConstantIslands::optimizeThumb2Branches() {
1752 bool MadeChange = false;
1754 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
1755 ImmBranch &Br = ImmBranches[i];
1756 unsigned Opcode = Br.MI->getOpcode();
1757 unsigned NewOpc = 0;
1775 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1776 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1777 if (isBBInRange(Br.MI, DestBB, MaxOffs)) {
1778 DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1779 Br.MI->setDesc(TII->get(NewOpc));
1780 MachineBasicBlock *MBB = Br.MI->getParent();
1781 BBInfo[MBB->getNumber()].Size -= 2;
1782 adjustBBOffsetsAfter(MBB);
1788 Opcode = Br.MI->getOpcode();
1789 if (Opcode != ARM::tBcc)
1792 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1793 // so this transformation is not safe.
1794 if (!Br.MI->killsRegister(ARM::CPSR))
1798 unsigned PredReg = 0;
1799 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);
1800 if (Pred == ARMCC::EQ)
1802 else if (Pred == ARMCC::NE)
1803 NewOpc = ARM::tCBNZ;
1806 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1807 // Check if the distance is within 126. Subtract starting offset by 2
1808 // because the cmp will be eliminated.
1809 unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;
1810 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1811 if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1812 MachineBasicBlock::iterator CmpMI = Br.MI;
1813 if (CmpMI != Br.MI->getParent()->begin()) {
1815 if (CmpMI->getOpcode() == ARM::tCMPi8) {
1816 unsigned Reg = CmpMI->getOperand(0).getReg();
1817 Pred = getInstrPredicate(CmpMI, PredReg);
1818 if (Pred == ARMCC::AL &&
1819 CmpMI->getOperand(1).getImm() == 0 &&
1820 isARMLowRegister(Reg)) {
1821 MachineBasicBlock *MBB = Br.MI->getParent();
1822 DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);
1823 MachineInstr *NewBR =
1824 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1825 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1826 CmpMI->eraseFromParent();
1827 Br.MI->eraseFromParent();
1829 BBInfo[MBB->getNumber()].Size -= 2;
1830 adjustBBOffsetsAfter(MBB);
1842 /// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
1843 /// jumptables when it's possible.
1844 bool ARMConstantIslands::optimizeThumb2JumpTables() {
1845 bool MadeChange = false;
1847 // FIXME: After the tables are shrunk, can we get rid some of the
1848 // constantpool tables?
1849 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1850 if (!MJTI) return false;
1852 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1853 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1854 MachineInstr *MI = T2JumpTables[i];
1855 const MCInstrDesc &MCID = MI->getDesc();
1856 unsigned NumOps = MCID.getNumOperands();
1857 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2);
1858 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1859 unsigned JTI = JTOP.getIndex();
1860 assert(JTI < JT.size());
1863 bool HalfWordOk = true;
1864 unsigned JTOffset = getOffsetOf(MI) + 4;
1865 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1866 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1867 MachineBasicBlock *MBB = JTBBs[j];
1868 unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
1869 // Negative offset is not ok. FIXME: We should change BB layout to make
1870 // sure all the branches are forward.
1871 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
1873 unsigned TBHLimit = ((1<<16)-1)*2;
1874 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
1876 if (!ByteOk && !HalfWordOk)
1880 if (ByteOk || HalfWordOk) {
1881 MachineBasicBlock *MBB = MI->getParent();
1882 unsigned BaseReg = MI->getOperand(0).getReg();
1883 bool BaseRegKill = MI->getOperand(0).isKill();
1886 unsigned IdxReg = MI->getOperand(1).getReg();
1887 bool IdxRegKill = MI->getOperand(1).isKill();
1889 // Scan backwards to find the instruction that defines the base
1890 // register. Due to post-RA scheduling, we can't count on it
1891 // immediately preceding the branch instruction.
1892 MachineBasicBlock::iterator PrevI = MI;
1893 MachineBasicBlock::iterator B = MBB->begin();
1894 while (PrevI != B && !PrevI->definesRegister(BaseReg))
1897 // If for some reason we didn't find it, we can't do anything, so
1898 // just skip this one.
1899 if (!PrevI->definesRegister(BaseReg))
1902 MachineInstr *AddrMI = PrevI;
1904 // Examine the instruction that calculates the jumptable entry address.
1905 // Make sure it only defines the base register and kills any uses
1906 // other than the index register.
1907 for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
1908 const MachineOperand &MO = AddrMI->getOperand(k);
1909 if (!MO.isReg() || !MO.getReg())
1911 if (MO.isDef() && MO.getReg() != BaseReg) {
1915 if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
1923 // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
1924 // that gave us the initial base register definition.
1925 for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
1928 // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
1929 // to delete it as well.
1930 MachineInstr *LeaMI = PrevI;
1931 if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
1932 LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
1933 LeaMI->getOperand(0).getReg() != BaseReg)
1939 DEBUG(dbgs() << "Shrink JT: " << *MI << " addr: " << *AddrMI
1940 << " lea: " << *LeaMI);
1941 unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
1942 MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
1943 .addReg(IdxReg, getKillRegState(IdxRegKill))
1944 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
1945 .addImm(MI->getOperand(JTOpIdx+1).getImm());
1946 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": " << *NewJTMI);
1947 // FIXME: Insert an "ALIGN" instruction to ensure the next instruction
1948 // is 2-byte aligned. For now, asm printer will fix it up.
1949 unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
1950 unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
1951 OrigSize += TII->GetInstSizeInBytes(LeaMI);
1952 OrigSize += TII->GetInstSizeInBytes(MI);
1954 AddrMI->eraseFromParent();
1955 LeaMI->eraseFromParent();
1956 MI->eraseFromParent();
1958 int delta = OrigSize - NewSize;
1959 BBInfo[MBB->getNumber()].Size -= delta;
1960 adjustBBOffsetsAfter(MBB);
1970 /// reorderThumb2JumpTables - Adjust the function's block layout to ensure that
1971 /// jump tables always branch forwards, since that's what tbb and tbh need.
1972 bool ARMConstantIslands::reorderThumb2JumpTables() {
1973 bool MadeChange = false;
1975 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1976 if (!MJTI) return false;
1978 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1979 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1980 MachineInstr *MI = T2JumpTables[i];
1981 const MCInstrDesc &MCID = MI->getDesc();
1982 unsigned NumOps = MCID.getNumOperands();
1983 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 3 : 2);
1984 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1985 unsigned JTI = JTOP.getIndex();
1986 assert(JTI < JT.size());
1988 // We prefer if target blocks for the jump table come after the jump
1989 // instruction so we can use TB[BH]. Loop through the target blocks
1990 // and try to adjust them such that that's true.
1991 int JTNumber = MI->getParent()->getNumber();
1992 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1993 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1994 MachineBasicBlock *MBB = JTBBs[j];
1995 int DTNumber = MBB->getNumber();
1997 if (DTNumber < JTNumber) {
1998 // The destination precedes the switch. Try to move the block forward
1999 // so we have a positive offset.
2000 MachineBasicBlock *NewBB =
2001 adjustJTTargetBlockForward(MBB, MI->getParent());
2003 MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
2012 MachineBasicBlock *ARMConstantIslands::
2013 adjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
2014 // If the destination block is terminated by an unconditional branch,
2015 // try to move it; otherwise, create a new block following the jump
2016 // table that branches back to the actual target. This is a very simple
2017 // heuristic. FIXME: We can definitely improve it.
2018 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
2019 SmallVector<MachineOperand, 4> Cond;
2020 SmallVector<MachineOperand, 4> CondPrior;
2021 MachineFunction::iterator BBi = BB;
2022 MachineFunction::iterator OldPrior = std::prev(BBi);
2024 // If the block terminator isn't analyzable, don't try to move the block
2025 bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
2027 // If the block ends in an unconditional branch, move it. The prior block
2028 // has to have an analyzable terminator for us to move this one. Be paranoid
2029 // and make sure we're not trying to move the entry block of the function.
2030 if (!B && Cond.empty() && BB != MF->begin() &&
2031 !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
2032 BB->moveAfter(JTBB);
2033 OldPrior->updateTerminator();
2034 BB->updateTerminator();
2035 // Update numbering to account for the block being moved.
2036 MF->RenumberBlocks();
2041 // Create a new MBB for the code after the jump BB.
2042 MachineBasicBlock *NewBB =
2043 MF->CreateMachineBasicBlock(JTBB->getBasicBlock());
2044 MachineFunction::iterator MBBI = JTBB; ++MBBI;
2045 MF->insert(MBBI, NewBB);
2047 // Add an unconditional branch from NewBB to BB.
2048 // There doesn't seem to be meaningful DebugInfo available; this doesn't
2049 // correspond directly to anything in the source.
2050 assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
2051 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB)
2052 .addImm(ARMCC::AL).addReg(0);
2054 // Update internal data structures to account for the newly inserted MBB.
2055 MF->RenumberBlocks(NewBB);
2058 NewBB->addSuccessor(BB);
2059 JTBB->removeSuccessor(BB);
2060 JTBB->addSuccessor(NewBB);