1 //===-- ARMConstantIslandPass.cpp - ARM constant islands --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-cp-islands"
18 #include "ARMAddressingModes.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMInstrInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
38 STATISTIC(NumCPEs, "Number of constpool entries");
39 STATISTIC(NumSplit, "Number of uncond branches inserted");
40 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
41 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
42 STATISTIC(NumTBs, "Number of table branches generated");
43 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
44 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
45 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
46 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
47 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
51 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
52 cl::desc("Adjust basic block layout to better use TB[BH]"));
55 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
56 /// requires constant pool entries to be scattered among the instructions
57 /// inside a function. To do this, it completely ignores the normal LLVM
58 /// constant pool; instead, it places constants wherever it feels like with
59 /// special instructions.
61 /// The terminology used in this pass includes:
62 /// Islands - Clumps of constants placed in the function.
63 /// Water - Potential places where an island could be formed.
64 /// CPE - A constant pool entry that has been placed somewhere, which
65 /// tracks a list of users.
66 class ARMConstantIslands : public MachineFunctionPass {
67 /// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed
68 /// by MBB Number. The two-byte pads required for Thumb alignment are
69 /// counted as part of the following block (i.e., the offset and size for
70 /// a padded block will both be ==2 mod 4).
71 std::vector<unsigned> BBSizes;
73 /// BBOffsets - the offset of each MBB in bytes, starting from 0.
74 /// The two-byte pads required for Thumb alignment are counted as part of
75 /// the following block.
76 std::vector<unsigned> BBOffsets;
78 /// WaterList - A sorted list of basic blocks where islands could be placed
79 /// (i.e. blocks that don't fall through to the following block, due
80 /// to a return, unreachable, or unconditional branch).
81 std::vector<MachineBasicBlock*> WaterList;
83 /// NewWaterList - The subset of WaterList that was created since the
84 /// previous iteration by inserting unconditional branches.
85 SmallSet<MachineBasicBlock*, 4> NewWaterList;
87 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
89 /// CPUser - One user of a constant pool, keeping the machine instruction
90 /// pointer, the constant pool being referenced, and the max displacement
91 /// allowed from the instruction to the CP. The HighWaterMark records the
92 /// highest basic block where a new CPEntry can be placed. To ensure this
93 /// pass terminates, the CP entries are initially placed at the end of the
94 /// function and then move monotonically to lower addresses. The
95 /// exception to this rule is when the current CP entry for a particular
96 /// CPUser is out of range, but there is another CP entry for the same
97 /// constant value in range. We want to use the existing in-range CP
98 /// entry, but if it later moves out of range, the search for new water
99 /// should resume where it left off. The HighWaterMark is used to record
104 MachineBasicBlock *HighWaterMark;
108 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
109 bool neg, bool soimm)
110 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
111 HighWaterMark = CPEMI->getParent();
115 /// CPUsers - Keep track of all of the machine instructions that use various
116 /// constant pools and their max displacement.
117 std::vector<CPUser> CPUsers;
119 /// CPEntry - One per constant pool entry, keeping the machine instruction
120 /// pointer, the constpool index, and the number of CPUser's which
121 /// reference this entry.
126 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
127 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
130 /// CPEntries - Keep track of all of the constant pool entry machine
131 /// instructions. For each original constpool index (i.e. those that
132 /// existed upon entry to this pass), it keeps a vector of entries.
133 /// Original elements are cloned as we go along; the clones are
134 /// put in the vector of the original element, but have distinct CPIs.
135 std::vector<std::vector<CPEntry> > CPEntries;
137 /// ImmBranch - One per immediate branch, keeping the machine instruction
138 /// pointer, conditional or unconditional, the max displacement,
139 /// and (if isCond is true) the corresponding unconditional branch
143 unsigned MaxDisp : 31;
146 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
147 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
150 /// ImmBranches - Keep track of all the immediate branch instructions.
152 std::vector<ImmBranch> ImmBranches;
154 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
156 SmallVector<MachineInstr*, 4> PushPopMIs;
158 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
159 SmallVector<MachineInstr*, 4> T2JumpTables;
161 /// HasFarJump - True if any far jump instruction has been emitted during
162 /// the branch fix up pass.
165 /// HasInlineAsm - True if the function contains inline assembly.
168 const ARMInstrInfo *TII;
169 const ARMSubtarget *STI;
170 ARMFunctionInfo *AFI;
176 ARMConstantIslands() : MachineFunctionPass(&ID) {}
178 virtual bool runOnMachineFunction(MachineFunction &MF);
180 virtual const char *getPassName() const {
181 return "ARM constant island placement and branch shortening pass";
185 void DoInitialPlacement(MachineFunction &MF,
186 std::vector<MachineInstr*> &CPEMIs);
187 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
188 void JumpTableFunctionScan(MachineFunction &MF);
189 void InitialFunctionScan(MachineFunction &MF,
190 const std::vector<MachineInstr*> &CPEMIs);
191 MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
192 void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
193 void AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta);
194 bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI);
195 int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
196 bool LookForWater(CPUser&U, unsigned UserOffset, water_iterator &WaterIter);
197 void CreateNewWater(unsigned CPUserIndex, unsigned UserOffset,
198 MachineBasicBlock *&NewMBB);
199 bool HandleConstantPoolUser(MachineFunction &MF, unsigned CPUserIndex);
200 void RemoveDeadCPEMI(MachineInstr *CPEMI);
201 bool RemoveUnusedCPEntries();
202 bool CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
203 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
204 bool DoDump = false);
205 bool WaterIsInRange(unsigned UserOffset, MachineBasicBlock *Water,
207 bool OffsetIsInRange(unsigned UserOffset, unsigned TrialOffset,
208 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
209 bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
210 bool FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br);
211 bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
212 bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
213 bool UndoLRSpillRestore();
214 bool OptimizeThumb2Instructions(MachineFunction &MF);
215 bool OptimizeThumb2Branches(MachineFunction &MF);
216 bool ReorderThumb2JumpTables(MachineFunction &MF);
217 bool OptimizeThumb2JumpTables(MachineFunction &MF);
218 MachineBasicBlock *AdjustJTTargetBlockForward(MachineBasicBlock *BB,
219 MachineBasicBlock *JTBB);
221 unsigned GetOffsetOf(MachineInstr *MI) const;
223 void verify(MachineFunction &MF);
225 char ARMConstantIslands::ID = 0;
228 /// verify - check BBOffsets, BBSizes, alignment of islands
229 void ARMConstantIslands::verify(MachineFunction &MF) {
230 assert(BBOffsets.size() == BBSizes.size());
231 for (unsigned i = 1, e = BBOffsets.size(); i != e; ++i)
232 assert(BBOffsets[i-1]+BBSizes[i-1] == BBOffsets[i]);
236 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
238 MachineBasicBlock *MBB = MBBI;
240 MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
241 unsigned MBBId = MBB->getNumber();
242 assert(HasInlineAsm ||
243 (BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) ||
244 (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0));
247 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
248 CPUser &U = CPUsers[i];
249 unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8);
250 unsigned CPEOffset = GetOffsetOf(U.CPEMI);
251 unsigned Disp = UserOffset < CPEOffset ? CPEOffset - UserOffset :
252 UserOffset - CPEOffset;
253 assert(Disp <= U.MaxDisp || "Constant pool entry out of range!");
258 /// print block size and offset information - debugging
259 void ARMConstantIslands::dumpBBs() {
260 for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
261 DEBUG(errs() << "block " << J << " offset " << BBOffsets[J]
262 << " size " << BBSizes[J] << "\n");
266 /// createARMConstantIslandPass - returns an instance of the constpool
268 FunctionPass *llvm::createARMConstantIslandPass() {
269 return new ARMConstantIslands();
272 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
273 MachineConstantPool &MCP = *MF.getConstantPool();
275 TII = (const ARMInstrInfo*)MF.getTarget().getInstrInfo();
276 AFI = MF.getInfo<ARMFunctionInfo>();
277 STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
279 isThumb = AFI->isThumbFunction();
280 isThumb1 = AFI->isThumb1OnlyFunction();
281 isThumb2 = AFI->isThumb2Function();
284 HasInlineAsm = false;
286 // Renumber all of the machine basic blocks in the function, guaranteeing that
287 // the numbers agree with the position of the block in the function.
290 // Try to reorder and otherwise adjust the block layout to make good use
291 // of the TB[BH] instructions.
292 bool MadeChange = false;
293 if (isThumb2 && AdjustJumpTableBlocks) {
294 JumpTableFunctionScan(MF);
295 MadeChange |= ReorderThumb2JumpTables(MF);
296 // Data is out of date, so clear it. It'll be re-computed later.
297 T2JumpTables.clear();
298 // Blocks may have shifted around. Keep the numbering up to date.
302 // Thumb1 functions containing constant pools get 4-byte alignment.
303 // This is so we can keep exact track of where the alignment padding goes.
305 // ARM and Thumb2 functions need to be 4-byte aligned.
307 MF.EnsureAlignment(2); // 2 = log2(4)
309 // Perform the initial placement of the constant pool entries. To start with,
310 // we put them all at the end of the function.
311 std::vector<MachineInstr*> CPEMIs;
312 if (!MCP.isEmpty()) {
313 DoInitialPlacement(MF, CPEMIs);
315 MF.EnsureAlignment(2); // 2 = log2(4)
318 /// The next UID to take is the first unused one.
319 AFI->initConstPoolEntryUId(CPEMIs.size());
321 // Do the initial scan of the function, building up information about the
322 // sizes of each block, the location of all the water, and finding all of the
323 // constant pool users.
324 InitialFunctionScan(MF, CPEMIs);
329 /// Remove dead constant pool entries.
330 RemoveUnusedCPEntries();
332 // Iteratively place constant pool entries and fix up branches until there
334 unsigned NoCPIters = 0, NoBRIters = 0;
336 bool CPChange = false;
337 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
338 CPChange |= HandleConstantPoolUser(MF, i);
339 if (CPChange && ++NoCPIters > 30)
340 llvm_unreachable("Constant Island pass failed to converge!");
343 // Clear NewWaterList now. If we split a block for branches, it should
344 // appear as "new water" for the next iteration of constant pool placement.
345 NewWaterList.clear();
347 bool BRChange = false;
348 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
349 BRChange |= FixUpImmediateBr(MF, ImmBranches[i]);
350 if (BRChange && ++NoBRIters > 30)
351 llvm_unreachable("Branch Fix Up pass failed to converge!");
354 if (!CPChange && !BRChange)
359 // Shrink 32-bit Thumb2 branch, load, and store instructions.
361 MadeChange |= OptimizeThumb2Instructions(MF);
363 // After a while, this might be made debug-only, but it is not expensive.
366 // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
367 // undo the spill / restore of LR if possible.
368 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
369 MadeChange |= UndoLRSpillRestore();
371 DEBUG(errs() << '\n'; dumpBBs());
380 T2JumpTables.clear();
385 /// DoInitialPlacement - Perform the initial placement of the constant pool
386 /// entries. To start with, we put them all at the end of the function.
387 void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
388 std::vector<MachineInstr*> &CPEMIs) {
389 // Create the basic block to hold the CPE's.
390 MachineBasicBlock *BB = MF.CreateMachineBasicBlock();
393 // Add all of the constants from the constant pool to the end block, use an
394 // identity mapping of CPI's to CPE's.
395 const std::vector<MachineConstantPoolEntry> &CPs =
396 MF.getConstantPool()->getConstants();
398 const TargetData &TD = *MF.getTarget().getTargetData();
399 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
400 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
401 // Verify that all constant pool entries are a multiple of 4 bytes. If not,
402 // we would have to pad them out or something so that instructions stay
404 assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
405 MachineInstr *CPEMI =
406 BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
407 .addImm(i).addConstantPoolIndex(i).addImm(Size);
408 CPEMIs.push_back(CPEMI);
410 // Add a new CPEntry, but no corresponding CPUser yet.
411 std::vector<CPEntry> CPEs;
412 CPEs.push_back(CPEntry(CPEMI, i));
413 CPEntries.push_back(CPEs);
415 DEBUG(errs() << "Moved CPI#" << i << " to end of function as #" << i
420 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
421 /// into the block immediately after it.
422 static bool BBHasFallthrough(MachineBasicBlock *MBB) {
423 // Get the next machine basic block in the function.
424 MachineFunction::iterator MBBI = MBB;
425 // Can't fall off end of function.
426 if (llvm::next(MBBI) == MBB->getParent()->end())
429 MachineBasicBlock *NextBB = llvm::next(MBBI);
430 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
431 E = MBB->succ_end(); I != E; ++I)
438 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
439 /// look up the corresponding CPEntry.
440 ARMConstantIslands::CPEntry
441 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
442 const MachineInstr *CPEMI) {
443 std::vector<CPEntry> &CPEs = CPEntries[CPI];
444 // Number of entries per constpool index should be small, just do a
446 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
447 if (CPEs[i].CPEMI == CPEMI)
453 /// JumpTableFunctionScan - Do a scan of the function, building up
454 /// information about the sizes of each block and the locations of all
456 void ARMConstantIslands::JumpTableFunctionScan(MachineFunction &MF) {
457 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
459 MachineBasicBlock &MBB = *MBBI;
461 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
463 if (I->getDesc().isBranch() && I->getOpcode() == ARM::t2BR_JT)
464 T2JumpTables.push_back(I);
468 /// InitialFunctionScan - Do the initial scan of the function, building up
469 /// information about the sizes of each block, the location of all the water,
470 /// and finding all of the constant pool users.
471 void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
472 const std::vector<MachineInstr*> &CPEMIs) {
473 // First thing, see if the function has any inline assembly in it. If so,
474 // we have to be conservative about alignment assumptions, as we don't
475 // know for sure the size of any instructions in the inline assembly.
476 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
478 MachineBasicBlock &MBB = *MBBI;
479 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
481 if (I->getOpcode() == ARM::INLINEASM)
485 // Now go back through the instructions and build up our data structures
487 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
489 MachineBasicBlock &MBB = *MBBI;
491 // If this block doesn't fall through into the next MBB, then this is
492 // 'water' that a constant pool island could be placed.
493 if (!BBHasFallthrough(&MBB))
494 WaterList.push_back(&MBB);
496 unsigned MBBSize = 0;
497 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
499 if (I->isDebugValue())
501 // Add instruction size to MBBSize.
502 MBBSize += TII->GetInstSizeInBytes(I);
504 int Opc = I->getOpcode();
505 if (I->getDesc().isBranch()) {
512 continue; // Ignore other JT branches
514 // A Thumb1 table jump may involve padding; for the offsets to
515 // be right, functions containing these must be 4-byte aligned.
516 // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
517 // table entries. So this code checks whether offset of tBR_JTr + 2
518 // is aligned. That is held in Offset+MBBSize, which already has
519 // 2 added in for the size of the mov pc instruction.
520 MF.EnsureAlignment(2U);
521 if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
522 // FIXME: Add a pseudo ALIGN instruction instead.
523 MBBSize += 2; // padding
524 continue; // Does not get an entry in ImmBranches
526 T2JumpTables.push_back(I);
527 continue; // Does not get an entry in ImmBranches
558 // Record this immediate branch.
559 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
560 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
563 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
564 PushPopMIs.push_back(I);
566 if (Opc == ARM::CONSTPOOL_ENTRY)
569 // Scan the instructions for constant pool operands.
570 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
571 if (I->getOperand(op).isCPI()) {
572 // We found one. The addressing mode tells us the max displacement
573 // from the PC that this instruction permits.
575 // Basic size info comes from the TSFlags field.
579 bool IsSoImm = false;
583 llvm_unreachable("Unknown addressing mode for CP reference!");
586 // Taking the address of a CP entry.
588 // This takes a SoImm, which is 8 bit immediate rotated. We'll
589 // pretend the maximum offset is 255 * 4. Since each instruction
590 // 4 byte wide, this is always correct. We'll check for other
591 // displacements that fits in a SoImm as well.
597 case ARM::t2LEApcrel:
609 Bits = 12; // +-offset_12
616 Scale = 4; // +(offset_8*4)
622 Scale = 4; // +-(offset_8*4)
627 // Remember that this is a user of a CP entry.
628 unsigned CPI = I->getOperand(op).getIndex();
629 MachineInstr *CPEMI = CPEMIs[CPI];
630 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
631 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
633 // Increment corresponding CPEntry reference count.
634 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
635 assert(CPE && "Cannot find a corresponding CPEntry!");
638 // Instructions can only use one CP entry, don't bother scanning the
639 // rest of the operands.
644 // In thumb mode, if this block is a constpool island, we may need padding
645 // so it's aligned on 4 byte boundary.
648 MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY &&
649 ((Offset%4) != 0 || HasInlineAsm))
652 BBSizes.push_back(MBBSize);
653 BBOffsets.push_back(Offset);
658 /// GetOffsetOf - Return the current offset of the specified machine instruction
659 /// from the start of the function. This offset changes as stuff is moved
660 /// around inside the function.
661 unsigned ARMConstantIslands::GetOffsetOf(MachineInstr *MI) const {
662 MachineBasicBlock *MBB = MI->getParent();
664 // The offset is composed of two things: the sum of the sizes of all MBB's
665 // before this instruction's block, and the offset from the start of the block
667 unsigned Offset = BBOffsets[MBB->getNumber()];
669 // If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has
670 // alignment padding, and compensate if so.
672 MI->getOpcode() == ARM::CONSTPOOL_ENTRY &&
673 (Offset%4 != 0 || HasInlineAsm))
676 // Sum instructions before MI in MBB.
677 for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
678 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
679 if (&*I == MI) return Offset;
680 Offset += TII->GetInstSizeInBytes(I);
684 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
686 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
687 const MachineBasicBlock *RHS) {
688 return LHS->getNumber() < RHS->getNumber();
691 /// UpdateForInsertedWaterBlock - When a block is newly inserted into the
692 /// machine function, it upsets all of the block numbers. Renumber the blocks
693 /// and update the arrays that parallel this numbering.
694 void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
695 // Renumber the MBB's to keep them consequtive.
696 NewBB->getParent()->RenumberBlocks(NewBB);
698 // Insert a size into BBSizes to align it properly with the (newly
699 // renumbered) block numbers.
700 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
702 // Likewise for BBOffsets.
703 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
705 // Next, update WaterList. Specifically, we need to add NewMBB as having
706 // available water after it.
708 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
710 WaterList.insert(IP, NewBB);
714 /// Split the basic block containing MI into two blocks, which are joined by
715 /// an unconditional branch. Update data structures and renumber blocks to
716 /// account for this change and returns the newly created block.
717 MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
718 MachineBasicBlock *OrigBB = MI->getParent();
719 MachineFunction &MF = *OrigBB->getParent();
721 // Create a new MBB for the code after the OrigBB.
722 MachineBasicBlock *NewBB =
723 MF.CreateMachineBasicBlock(OrigBB->getBasicBlock());
724 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
725 MF.insert(MBBI, NewBB);
727 // Splice the instructions starting with MI over to NewBB.
728 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
730 // Add an unconditional branch from OrigBB to NewBB.
731 // Note the new unconditional branch is not being recorded.
732 // There doesn't seem to be meaningful DebugInfo available; this doesn't
733 // correspond to anything in the source.
734 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
735 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
738 // Update the CFG. All succs of OrigBB are now succs of NewBB.
739 while (!OrigBB->succ_empty()) {
740 MachineBasicBlock *Succ = *OrigBB->succ_begin();
741 OrigBB->removeSuccessor(Succ);
742 NewBB->addSuccessor(Succ);
744 // This pass should be run after register allocation, so there should be no
745 // PHI nodes to update.
746 assert((Succ->empty() || !Succ->begin()->isPHI())
747 && "PHI nodes should be eliminated by now!");
750 // OrigBB branches to NewBB.
751 OrigBB->addSuccessor(NewBB);
753 // Update internal data structures to account for the newly inserted MBB.
754 // This is almost the same as UpdateForInsertedWaterBlock, except that
755 // the Water goes after OrigBB, not NewBB.
756 MF.RenumberBlocks(NewBB);
758 // Insert a size into BBSizes to align it properly with the (newly
759 // renumbered) block numbers.
760 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
762 // Likewise for BBOffsets.
763 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
765 // Next, update WaterList. Specifically, we need to add OrigMBB as having
766 // available water after it (but not if it's already there, which happens
767 // when splitting before a conditional branch that is followed by an
768 // unconditional branch - in that case we want to insert NewBB).
770 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
772 MachineBasicBlock* WaterBB = *IP;
773 if (WaterBB == OrigBB)
774 WaterList.insert(llvm::next(IP), NewBB);
776 WaterList.insert(IP, OrigBB);
777 NewWaterList.insert(OrigBB);
779 unsigned OrigBBI = OrigBB->getNumber();
780 unsigned NewBBI = NewBB->getNumber();
782 int delta = isThumb1 ? 2 : 4;
784 // Figure out how large the OrigBB is. As the first half of the original
785 // block, it cannot contain a tablejump. The size includes
786 // the new jump we added. (It should be possible to do this without
787 // recounting everything, but it's very confusing, and this is rarely
789 unsigned OrigBBSize = 0;
790 for (MachineBasicBlock::iterator I = OrigBB->begin(), E = OrigBB->end();
792 OrigBBSize += TII->GetInstSizeInBytes(I);
793 BBSizes[OrigBBI] = OrigBBSize;
795 // ...and adjust BBOffsets for NewBB accordingly.
796 BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI];
798 // Figure out how large the NewMBB is. As the second half of the original
799 // block, it may contain a tablejump.
800 unsigned NewBBSize = 0;
801 for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
803 NewBBSize += TII->GetInstSizeInBytes(I);
804 // Set the size of NewBB in BBSizes. It does not include any padding now.
805 BBSizes[NewBBI] = NewBBSize;
807 MachineInstr* ThumbJTMI = prior(NewBB->end());
808 if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
809 // We've added another 2-byte instruction before this tablejump, which
810 // means we will always need padding if we didn't before, and vice versa.
812 // The original offset of the jump instruction was:
813 unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta;
814 if (OrigOffset%4 == 0) {
815 // We had padding before and now we don't. No net change in code size.
818 // We didn't have padding before and now we do.
819 BBSizes[NewBBI] += 2;
824 // All BBOffsets following these blocks must be modified.
826 AdjustBBOffsetsAfter(NewBB, delta);
831 /// OffsetIsInRange - Checks whether UserOffset (the location of a constant pool
832 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
833 /// constant pool entry).
834 bool ARMConstantIslands::OffsetIsInRange(unsigned UserOffset,
835 unsigned TrialOffset, unsigned MaxDisp,
836 bool NegativeOK, bool IsSoImm) {
837 // On Thumb offsets==2 mod 4 are rounded down by the hardware for
838 // purposes of the displacement computation; compensate for that here.
839 // Effectively, the valid range of displacements is 2 bytes smaller for such
841 unsigned TotalAdj = 0;
842 if (isThumb && UserOffset%4 !=0) {
846 // CPEs will be rounded up to a multiple of 4.
847 if (isThumb && TrialOffset%4 != 0) {
852 // In Thumb2 mode, later branch adjustments can shift instructions up and
853 // cause alignment change. In the worst case scenario this can cause the
854 // user's effective address to be subtracted by 2 and the CPE's address to
856 if (isThumb2 && TotalAdj != 4)
857 MaxDisp -= (4 - TotalAdj);
859 if (UserOffset <= TrialOffset) {
860 // User before the Trial.
861 if (TrialOffset - UserOffset <= MaxDisp)
863 // FIXME: Make use full range of soimm values.
864 } else if (NegativeOK) {
865 if (UserOffset - TrialOffset <= MaxDisp)
867 // FIXME: Make use full range of soimm values.
872 /// WaterIsInRange - Returns true if a CPE placed after the specified
873 /// Water (a basic block) will be in range for the specific MI.
875 bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset,
876 MachineBasicBlock* Water, CPUser &U) {
877 unsigned MaxDisp = U.MaxDisp;
878 unsigned CPEOffset = BBOffsets[Water->getNumber()] +
879 BBSizes[Water->getNumber()];
881 // If the CPE is to be inserted before the instruction, that will raise
882 // the offset of the instruction.
883 if (CPEOffset < UserOffset)
884 UserOffset += U.CPEMI->getOperand(2).getImm();
886 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, U.NegOk, U.IsSoImm);
889 /// CPEIsInRange - Returns true if the distance between specific MI and
890 /// specific ConstPool entry instruction can fit in MI's displacement field.
891 bool ARMConstantIslands::CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
892 MachineInstr *CPEMI, unsigned MaxDisp,
893 bool NegOk, bool DoDump) {
894 unsigned CPEOffset = GetOffsetOf(CPEMI);
895 assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE");
898 DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
899 << " max delta=" << MaxDisp
900 << " insn address=" << UserOffset
901 << " CPE address=" << CPEOffset
902 << " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI);
905 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
909 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
910 /// unconditionally branches to its only successor.
911 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
912 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
915 MachineBasicBlock *Succ = *MBB->succ_begin();
916 MachineBasicBlock *Pred = *MBB->pred_begin();
917 MachineInstr *PredMI = &Pred->back();
918 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
919 || PredMI->getOpcode() == ARM::t2B)
920 return PredMI->getOperand(0).getMBB() == Succ;
925 void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB,
927 MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI);
928 for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
930 BBOffsets[i] += delta;
931 // If some existing blocks have padding, adjust the padding as needed, a
932 // bit tricky. delta can be negative so don't use % on that.
935 MachineBasicBlock *MBB = MBBI;
936 if (!MBB->empty() && !HasInlineAsm) {
937 // Constant pool entries require padding.
938 if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
939 unsigned OldOffset = BBOffsets[i] - delta;
940 if ((OldOffset%4) == 0 && (BBOffsets[i]%4) != 0) {
944 } else if ((OldOffset%4) != 0 && (BBOffsets[i]%4) == 0) {
945 // remove existing padding
950 // Thumb1 jump tables require padding. They should be at the end;
951 // following unconditional branches are removed by AnalyzeBranch.
952 // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
953 // table entries. So this code checks whether offset of tBR_JTr
954 // is aligned; if it is, the offset of the jump table following the
955 // instruction will not be aligned, and we need padding.
956 MachineInstr *ThumbJTMI = prior(MBB->end());
957 if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
958 unsigned NewMIOffset = GetOffsetOf(ThumbJTMI);
959 unsigned OldMIOffset = NewMIOffset - delta;
960 if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
961 // remove existing padding
964 } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
973 MBBI = llvm::next(MBBI);
977 /// DecrementOldEntry - find the constant pool entry with index CPI
978 /// and instruction CPEMI, and decrement its refcount. If the refcount
979 /// becomes 0 remove the entry and instruction. Returns true if we removed
980 /// the entry, false if we didn't.
982 bool ARMConstantIslands::DecrementOldEntry(unsigned CPI, MachineInstr *CPEMI) {
983 // Find the old entry. Eliminate it if it is no longer used.
984 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
985 assert(CPE && "Unexpected!");
986 if (--CPE->RefCount == 0) {
987 RemoveDeadCPEMI(CPEMI);
995 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
996 /// if not, see if an in-range clone of the CPE is in range, and if so,
997 /// change the data structures so the user references the clone. Returns:
998 /// 0 = no existing entry found
999 /// 1 = entry found, and there were no code insertions or deletions
1000 /// 2 = entry found, and there were code insertions or deletions
1001 int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
1003 MachineInstr *UserMI = U.MI;
1004 MachineInstr *CPEMI = U.CPEMI;
1006 // Check to see if the CPE is already in-range.
1007 if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, U.NegOk, true)) {
1008 DEBUG(errs() << "In range\n");
1012 // No. Look for previously created clones of the CPE that are in range.
1013 unsigned CPI = CPEMI->getOperand(1).getIndex();
1014 std::vector<CPEntry> &CPEs = CPEntries[CPI];
1015 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
1016 // We already tried this one
1017 if (CPEs[i].CPEMI == CPEMI)
1019 // Removing CPEs can leave empty entries, skip
1020 if (CPEs[i].CPEMI == NULL)
1022 if (CPEIsInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.MaxDisp, U.NegOk)) {
1023 DEBUG(errs() << "Replacing CPE#" << CPI << " with CPE#"
1024 << CPEs[i].CPI << "\n");
1025 // Point the CPUser node to the replacement
1026 U.CPEMI = CPEs[i].CPEMI;
1027 // Change the CPI in the instruction operand to refer to the clone.
1028 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
1029 if (UserMI->getOperand(j).isCPI()) {
1030 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1033 // Adjust the refcount of the clone...
1035 // ...and the original. If we didn't remove the old entry, none of the
1036 // addresses changed, so we don't need another pass.
1037 return DecrementOldEntry(CPI, CPEMI) ? 2 : 1;
1043 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1044 /// the specific unconditional branch instruction.
1045 static inline unsigned getUnconditionalBrDisp(int Opc) {
1048 return ((1<<10)-1)*2;
1050 return ((1<<23)-1)*2;
1055 return ((1<<23)-1)*4;
1058 /// LookForWater - Look for an existing entry in the WaterList in which
1059 /// we can place the CPE referenced from U so it's within range of U's MI.
1060 /// Returns true if found, false if not. If it returns true, WaterIter
1061 /// is set to the WaterList entry. For Thumb, prefer water that will not
1062 /// introduce padding to water that will. To ensure that this pass
1063 /// terminates, the CPE location for a particular CPUser is only allowed to
1064 /// move to a lower address, so search backward from the end of the list and
1065 /// prefer the first water that is in range.
1066 bool ARMConstantIslands::LookForWater(CPUser &U, unsigned UserOffset,
1067 water_iterator &WaterIter) {
1068 if (WaterList.empty())
1071 bool FoundWaterThatWouldPad = false;
1072 water_iterator IPThatWouldPad;
1073 for (water_iterator IP = prior(WaterList.end()),
1074 B = WaterList.begin();; --IP) {
1075 MachineBasicBlock* WaterBB = *IP;
1076 // Check if water is in range and is either at a lower address than the
1077 // current "high water mark" or a new water block that was created since
1078 // the previous iteration by inserting an unconditional branch. In the
1079 // latter case, we want to allow resetting the high water mark back to
1080 // this new water since we haven't seen it before. Inserting branches
1081 // should be relatively uncommon and when it does happen, we want to be
1082 // sure to take advantage of it for all the CPEs near that block, so that
1083 // we don't insert more branches than necessary.
1084 if (WaterIsInRange(UserOffset, WaterBB, U) &&
1085 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1086 NewWaterList.count(WaterBB))) {
1087 unsigned WBBId = WaterBB->getNumber();
1089 (BBOffsets[WBBId] + BBSizes[WBBId])%4 != 0) {
1090 // This is valid Water, but would introduce padding. Remember
1091 // it in case we don't find any Water that doesn't do this.
1092 if (!FoundWaterThatWouldPad) {
1093 FoundWaterThatWouldPad = true;
1094 IPThatWouldPad = IP;
1104 if (FoundWaterThatWouldPad) {
1105 WaterIter = IPThatWouldPad;
1111 /// CreateNewWater - No existing WaterList entry will work for
1112 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1113 /// block is used if in range, and the conditional branch munged so control
1114 /// flow is correct. Otherwise the block is split to create a hole with an
1115 /// unconditional branch around it. In either case NewMBB is set to a
1116 /// block following which the new island can be inserted (the WaterList
1117 /// is not adjusted).
1118 void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
1119 unsigned UserOffset,
1120 MachineBasicBlock *&NewMBB) {
1121 CPUser &U = CPUsers[CPUserIndex];
1122 MachineInstr *UserMI = U.MI;
1123 MachineInstr *CPEMI = U.CPEMI;
1124 MachineBasicBlock *UserMBB = UserMI->getParent();
1125 unsigned OffsetOfNextBlock = BBOffsets[UserMBB->getNumber()] +
1126 BBSizes[UserMBB->getNumber()];
1127 assert(OffsetOfNextBlock== BBOffsets[UserMBB->getNumber()+1]);
1129 // If the block does not end in an unconditional branch already, and if the
1130 // end of the block is within range, make new water there. (The addition
1131 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1132 // Thumb2, 2 on Thumb1. Possible Thumb1 alignment padding is allowed for
1133 // inside OffsetIsInRange.
1134 if (BBHasFallthrough(UserMBB) &&
1135 OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4),
1136 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1137 DEBUG(errs() << "Split at end of block\n");
1138 if (&UserMBB->back() == UserMI)
1139 assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
1140 NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
1141 // Add an unconditional branch from UserMBB to fallthrough block.
1142 // Record it for branch lengthening; this new branch will not get out of
1143 // range, but if the preceding conditional branch is out of range, the
1144 // targets will be exchanged, and the altered branch may be out of
1145 // range, so the machinery has to know about it.
1146 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1147 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1148 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1149 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1150 MaxDisp, false, UncondBr));
1151 int delta = isThumb1 ? 2 : 4;
1152 BBSizes[UserMBB->getNumber()] += delta;
1153 AdjustBBOffsetsAfter(UserMBB, delta);
1155 // What a big block. Find a place within the block to split it.
1156 // This is a little tricky on Thumb1 since instructions are 2 bytes
1157 // and constant pool entries are 4 bytes: if instruction I references
1158 // island CPE, and instruction I+1 references CPE', it will
1159 // not work well to put CPE as far forward as possible, since then
1160 // CPE' cannot immediately follow it (that location is 2 bytes
1161 // farther away from I+1 than CPE was from I) and we'd need to create
1162 // a new island. So, we make a first guess, then walk through the
1163 // instructions between the one currently being looked at and the
1164 // possible insertion point, and make sure any other instructions
1165 // that reference CPEs will be able to use the same island area;
1166 // if not, we back up the insertion point.
1168 // The 4 in the following is for the unconditional branch we'll be
1169 // inserting (allows for long branch on Thumb1). Alignment of the
1170 // island is handled inside OffsetIsInRange.
1171 unsigned BaseInsertOffset = UserOffset + U.MaxDisp -4;
1172 // This could point off the end of the block if we've already got
1173 // constant pool entries following this block; only the last one is
1174 // in the water list. Back past any possible branches (allow for a
1175 // conditional and a maximally long unconditional).
1176 if (BaseInsertOffset >= BBOffsets[UserMBB->getNumber()+1])
1177 BaseInsertOffset = BBOffsets[UserMBB->getNumber()+1] -
1179 unsigned EndInsertOffset = BaseInsertOffset +
1180 CPEMI->getOperand(2).getImm();
1181 MachineBasicBlock::iterator MI = UserMI;
1183 unsigned CPUIndex = CPUserIndex+1;
1184 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1185 Offset < BaseInsertOffset;
1186 Offset += TII->GetInstSizeInBytes(MI),
1187 MI = llvm::next(MI)) {
1188 if (CPUIndex < CPUsers.size() && CPUsers[CPUIndex].MI == MI) {
1189 CPUser &U = CPUsers[CPUIndex];
1190 if (!OffsetIsInRange(Offset, EndInsertOffset,
1191 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1192 BaseInsertOffset -= (isThumb1 ? 2 : 4);
1193 EndInsertOffset -= (isThumb1 ? 2 : 4);
1195 // This is overly conservative, as we don't account for CPEMIs
1196 // being reused within the block, but it doesn't matter much.
1197 EndInsertOffset += CPUsers[CPUIndex].CPEMI->getOperand(2).getImm();
1201 DEBUG(errs() << "Split in middle of big block\n");
1202 NewMBB = SplitBlockBeforeInstr(prior(MI));
1206 /// HandleConstantPoolUser - Analyze the specified user, checking to see if it
1207 /// is out-of-range. If so, pick up the constant pool value and move it some
1208 /// place in-range. Return true if we changed any addresses (thus must run
1209 /// another pass of branch lengthening), false otherwise.
1210 bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
1211 unsigned CPUserIndex) {
1212 CPUser &U = CPUsers[CPUserIndex];
1213 MachineInstr *UserMI = U.MI;
1214 MachineInstr *CPEMI = U.CPEMI;
1215 unsigned CPI = CPEMI->getOperand(1).getIndex();
1216 unsigned Size = CPEMI->getOperand(2).getImm();
1217 // Compute this only once, it's expensive. The 4 or 8 is the value the
1218 // hardware keeps in the PC.
1219 unsigned UserOffset = GetOffsetOf(UserMI) + (isThumb ? 4 : 8);
1221 // See if the current entry is within range, or there is a clone of it
1223 int result = LookForExistingCPEntry(U, UserOffset);
1224 if (result==1) return false;
1225 else if (result==2) return true;
1227 // No existing clone of this CPE is within range.
1228 // We will be generating a new clone. Get a UID for it.
1229 unsigned ID = AFI->createConstPoolEntryUId();
1231 // Look for water where we can place this CPE.
1232 MachineBasicBlock *NewIsland = MF.CreateMachineBasicBlock();
1233 MachineBasicBlock *NewMBB;
1235 if (LookForWater(U, UserOffset, IP)) {
1236 DEBUG(errs() << "found water in range\n");
1237 MachineBasicBlock *WaterBB = *IP;
1239 // If the original WaterList entry was "new water" on this iteration,
1240 // propagate that to the new island. This is just keeping NewWaterList
1241 // updated to match the WaterList, which will be updated below.
1242 if (NewWaterList.count(WaterBB)) {
1243 NewWaterList.erase(WaterBB);
1244 NewWaterList.insert(NewIsland);
1246 // The new CPE goes before the following block (NewMBB).
1247 NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
1251 DEBUG(errs() << "No water found\n");
1252 CreateNewWater(CPUserIndex, UserOffset, NewMBB);
1254 // SplitBlockBeforeInstr adds to WaterList, which is important when it is
1255 // called while handling branches so that the water will be seen on the
1256 // next iteration for constant pools, but in this context, we don't want
1257 // it. Check for this so it will be removed from the WaterList.
1258 // Also remove any entry from NewWaterList.
1259 MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
1260 IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
1261 if (IP != WaterList.end())
1262 NewWaterList.erase(WaterBB);
1264 // We are adding new water. Update NewWaterList.
1265 NewWaterList.insert(NewIsland);
1268 // Remove the original WaterList entry; we want subsequent insertions in
1269 // this vicinity to go after the one we're about to insert. This
1270 // considerably reduces the number of times we have to move the same CPE
1271 // more than once and is also important to ensure the algorithm terminates.
1272 if (IP != WaterList.end())
1273 WaterList.erase(IP);
1275 // Okay, we know we can put an island before NewMBB now, do it!
1276 MF.insert(NewMBB, NewIsland);
1278 // Update internal data structures to account for the newly inserted MBB.
1279 UpdateForInsertedWaterBlock(NewIsland);
1281 // Decrement the old entry, and remove it if refcount becomes 0.
1282 DecrementOldEntry(CPI, CPEMI);
1284 // Now that we have an island to add the CPE to, clone the original CPE and
1285 // add it to the island.
1286 U.HighWaterMark = NewIsland;
1287 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
1288 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
1289 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1292 BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()];
1293 // Compensate for .align 2 in thumb mode.
1294 if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm))
1296 // Increase the size of the island block to account for the new entry.
1297 BBSizes[NewIsland->getNumber()] += Size;
1298 AdjustBBOffsetsAfter(NewIsland, Size);
1300 // Finally, change the CPI in the instruction operand to be ID.
1301 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1302 if (UserMI->getOperand(i).isCPI()) {
1303 UserMI->getOperand(i).setIndex(ID);
1307 DEBUG(errs() << " Moved CPE to #" << ID << " CPI=" << CPI
1308 << '\t' << *UserMI);
1313 /// RemoveDeadCPEMI - Remove a dead constant pool entry instruction. Update
1314 /// sizes and offsets of impacted basic blocks.
1315 void ARMConstantIslands::RemoveDeadCPEMI(MachineInstr *CPEMI) {
1316 MachineBasicBlock *CPEBB = CPEMI->getParent();
1317 unsigned Size = CPEMI->getOperand(2).getImm();
1318 CPEMI->eraseFromParent();
1319 BBSizes[CPEBB->getNumber()] -= Size;
1320 // All succeeding offsets have the current size value added in, fix this.
1321 if (CPEBB->empty()) {
1322 // In thumb1 mode, the size of island may be padded by two to compensate for
1323 // the alignment requirement. Then it will now be 2 when the block is
1324 // empty, so fix this.
1325 // All succeeding offsets have the current size value added in, fix this.
1326 if (BBSizes[CPEBB->getNumber()] != 0) {
1327 Size += BBSizes[CPEBB->getNumber()];
1328 BBSizes[CPEBB->getNumber()] = 0;
1331 AdjustBBOffsetsAfter(CPEBB, -Size);
1332 // An island has only one predecessor BB and one successor BB. Check if
1333 // this BB's predecessor jumps directly to this BB's successor. This
1334 // shouldn't happen currently.
1335 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1336 // FIXME: remove the empty blocks after all the work is done?
1339 /// RemoveUnusedCPEntries - Remove constant pool entries whose refcounts
1341 bool ARMConstantIslands::RemoveUnusedCPEntries() {
1342 unsigned MadeChange = false;
1343 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1344 std::vector<CPEntry> &CPEs = CPEntries[i];
1345 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1346 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1347 RemoveDeadCPEMI(CPEs[j].CPEMI);
1348 CPEs[j].CPEMI = NULL;
1356 /// BBIsInRange - Returns true if the distance between specific MI and
1357 /// specific BB can fit in MI's displacement field.
1358 bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1360 unsigned PCAdj = isThumb ? 4 : 8;
1361 unsigned BrOffset = GetOffsetOf(MI) + PCAdj;
1362 unsigned DestOffset = BBOffsets[DestBB->getNumber()];
1364 DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber()
1365 << " from BB#" << MI->getParent()->getNumber()
1366 << " max delta=" << MaxDisp
1367 << " from " << GetOffsetOf(MI) << " to " << DestOffset
1368 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1370 if (BrOffset <= DestOffset) {
1371 // Branch before the Dest.
1372 if (DestOffset-BrOffset <= MaxDisp)
1375 if (BrOffset-DestOffset <= MaxDisp)
1381 /// FixUpImmediateBr - Fix up an immediate branch whose destination is too far
1382 /// away to fit in its displacement field.
1383 bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br) {
1384 MachineInstr *MI = Br.MI;
1385 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1387 // Check to see if the DestBB is already in-range.
1388 if (BBIsInRange(MI, DestBB, Br.MaxDisp))
1392 return FixUpUnconditionalBr(MF, Br);
1393 return FixUpConditionalBr(MF, Br);
1396 /// FixUpUnconditionalBr - Fix up an unconditional branch whose destination is
1397 /// too far away to fit in its displacement field. If the LR register has been
1398 /// spilled in the epilogue, then we can use BL to implement a far jump.
1399 /// Otherwise, add an intermediate branch instruction to a branch.
1401 ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
1402 MachineInstr *MI = Br.MI;
1403 MachineBasicBlock *MBB = MI->getParent();
1405 llvm_unreachable("FixUpUnconditionalBr is Thumb1 only!");
1407 // Use BL to implement far jump.
1408 Br.MaxDisp = (1 << 21) * 2;
1409 MI->setDesc(TII->get(ARM::tBfar));
1410 BBSizes[MBB->getNumber()] += 2;
1411 AdjustBBOffsetsAfter(MBB, 2);
1415 DEBUG(errs() << " Changed B to long jump " << *MI);
1420 /// FixUpConditionalBr - Fix up a conditional branch whose destination is too
1421 /// far away to fit in its displacement field. It is converted to an inverse
1422 /// conditional branch + an unconditional branch to the destination.
1424 ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
1425 MachineInstr *MI = Br.MI;
1426 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1428 // Add an unconditional branch to the destination and invert the branch
1429 // condition to jump over it:
1435 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1436 CC = ARMCC::getOppositeCondition(CC);
1437 unsigned CCReg = MI->getOperand(2).getReg();
1439 // If the branch is at the end of its MBB and that has a fall-through block,
1440 // direct the updated conditional branch to the fall-through block. Otherwise,
1441 // split the MBB before the next instruction.
1442 MachineBasicBlock *MBB = MI->getParent();
1443 MachineInstr *BMI = &MBB->back();
1444 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1448 if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
1449 BMI->getOpcode() == Br.UncondBr) {
1450 // Last MI in the BB is an unconditional branch. Can we simply invert the
1451 // condition and swap destinations:
1457 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1458 if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
1459 DEBUG(errs() << " Invert Bcc condition and swap its destination with "
1461 BMI->getOperand(0).setMBB(DestBB);
1462 MI->getOperand(0).setMBB(NewDest);
1463 MI->getOperand(1).setImm(CC);
1470 SplitBlockBeforeInstr(MI);
1471 // No need for the branch to the next block. We're adding an unconditional
1472 // branch to the destination.
1473 int delta = TII->GetInstSizeInBytes(&MBB->back());
1474 BBSizes[MBB->getNumber()] -= delta;
1475 MachineBasicBlock* SplitBB = llvm::next(MachineFunction::iterator(MBB));
1476 AdjustBBOffsetsAfter(SplitBB, -delta);
1477 MBB->back().eraseFromParent();
1478 // BBOffsets[SplitBB] is wrong temporarily, fixed below
1480 MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
1482 DEBUG(errs() << " Insert B to BB#" << DestBB->getNumber()
1483 << " also invert condition and change dest. to BB#"
1484 << NextBB->getNumber() << "\n");
1486 // Insert a new conditional branch and a new unconditional branch.
1487 // Also update the ImmBranch as well as adding a new entry for the new branch.
1488 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1489 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1490 Br.MI = &MBB->back();
1491 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1492 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1493 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1494 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1495 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1497 // Remove the old conditional branch. It may or may not still be in MBB.
1498 BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI);
1499 MI->eraseFromParent();
1501 // The net size change is an addition of one unconditional branch.
1502 int delta = TII->GetInstSizeInBytes(&MBB->back());
1503 AdjustBBOffsetsAfter(MBB, delta);
1507 /// UndoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1508 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1509 /// to do this if tBfar is not used.
1510 bool ARMConstantIslands::UndoLRSpillRestore() {
1511 bool MadeChange = false;
1512 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1513 MachineInstr *MI = PushPopMIs[i];
1514 // First two operands are predicates.
1515 if (MI->getOpcode() == ARM::tPOP_RET &&
1516 MI->getOperand(2).getReg() == ARM::PC &&
1517 MI->getNumExplicitOperands() == 3) {
1518 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
1519 MI->eraseFromParent();
1526 bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
1527 bool MadeChange = false;
1529 // Shrink ADR and LDR from constantpool.
1530 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1531 CPUser &U = CPUsers[i];
1532 unsigned Opcode = U.MI->getOpcode();
1533 unsigned NewOpc = 0;
1538 case ARM::t2LEApcrel:
1539 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1540 NewOpc = ARM::tLEApcrel;
1546 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1547 NewOpc = ARM::tLDRpci;
1557 unsigned UserOffset = GetOffsetOf(U.MI) + 4;
1558 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1559 // FIXME: Check if offset is multiple of scale if scale is not 4.
1560 if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1561 U.MI->setDesc(TII->get(NewOpc));
1562 MachineBasicBlock *MBB = U.MI->getParent();
1563 BBSizes[MBB->getNumber()] -= 2;
1564 AdjustBBOffsetsAfter(MBB, -2);
1570 MadeChange |= OptimizeThumb2Branches(MF);
1571 MadeChange |= OptimizeThumb2JumpTables(MF);
1575 bool ARMConstantIslands::OptimizeThumb2Branches(MachineFunction &MF) {
1576 bool MadeChange = false;
1578 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
1579 ImmBranch &Br = ImmBranches[i];
1580 unsigned Opcode = Br.MI->getOpcode();
1581 unsigned NewOpc = 0;
1599 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1600 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1601 if (BBIsInRange(Br.MI, DestBB, MaxOffs)) {
1602 Br.MI->setDesc(TII->get(NewOpc));
1603 MachineBasicBlock *MBB = Br.MI->getParent();
1604 BBSizes[MBB->getNumber()] -= 2;
1605 AdjustBBOffsetsAfter(MBB, -2);
1611 Opcode = Br.MI->getOpcode();
1612 if (Opcode != ARM::tBcc)
1616 unsigned PredReg = 0;
1617 ARMCC::CondCodes Pred = llvm::getInstrPredicate(Br.MI, PredReg);
1618 if (Pred == ARMCC::EQ)
1620 else if (Pred == ARMCC::NE)
1621 NewOpc = ARM::tCBNZ;
1624 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1625 // Check if the distance is within 126. Subtract starting offset by 2
1626 // because the cmp will be eliminated.
1627 unsigned BrOffset = GetOffsetOf(Br.MI) + 4 - 2;
1628 unsigned DestOffset = BBOffsets[DestBB->getNumber()];
1629 if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1630 MachineBasicBlock::iterator CmpMI = Br.MI; --CmpMI;
1631 if (CmpMI->getOpcode() == ARM::tCMPzi8) {
1632 unsigned Reg = CmpMI->getOperand(0).getReg();
1633 Pred = llvm::getInstrPredicate(CmpMI, PredReg);
1634 if (Pred == ARMCC::AL &&
1635 CmpMI->getOperand(1).getImm() == 0 &&
1636 isARMLowRegister(Reg)) {
1637 MachineBasicBlock *MBB = Br.MI->getParent();
1638 MachineInstr *NewBR =
1639 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1640 .addReg(Reg).addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
1641 CmpMI->eraseFromParent();
1642 Br.MI->eraseFromParent();
1644 BBSizes[MBB->getNumber()] -= 2;
1645 AdjustBBOffsetsAfter(MBB, -2);
1656 /// OptimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
1657 /// jumptables when it's possible.
1658 bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
1659 bool MadeChange = false;
1661 // FIXME: After the tables are shrunk, can we get rid some of the
1662 // constantpool tables?
1663 MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
1664 if (MJTI == 0) return false;
1666 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1667 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1668 MachineInstr *MI = T2JumpTables[i];
1669 const TargetInstrDesc &TID = MI->getDesc();
1670 unsigned NumOps = TID.getNumOperands();
1671 unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
1672 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1673 unsigned JTI = JTOP.getIndex();
1674 assert(JTI < JT.size());
1677 bool HalfWordOk = true;
1678 unsigned JTOffset = GetOffsetOf(MI) + 4;
1679 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1680 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1681 MachineBasicBlock *MBB = JTBBs[j];
1682 unsigned DstOffset = BBOffsets[MBB->getNumber()];
1683 // Negative offset is not ok. FIXME: We should change BB layout to make
1684 // sure all the branches are forward.
1685 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
1687 unsigned TBHLimit = ((1<<16)-1)*2;
1688 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
1690 if (!ByteOk && !HalfWordOk)
1694 if (ByteOk || HalfWordOk) {
1695 MachineBasicBlock *MBB = MI->getParent();
1696 unsigned BaseReg = MI->getOperand(0).getReg();
1697 bool BaseRegKill = MI->getOperand(0).isKill();
1700 unsigned IdxReg = MI->getOperand(1).getReg();
1701 bool IdxRegKill = MI->getOperand(1).isKill();
1703 // Scan backwards to find the instruction that defines the base
1704 // register. Due to post-RA scheduling, we can't count on it
1705 // immediately preceding the branch instruction.
1706 MachineBasicBlock::iterator PrevI = MI;
1707 MachineBasicBlock::iterator B = MBB->begin();
1708 while (PrevI != B && !PrevI->definesRegister(BaseReg))
1711 // If for some reason we didn't find it, we can't do anything, so
1712 // just skip this one.
1713 if (!PrevI->definesRegister(BaseReg))
1716 MachineInstr *AddrMI = PrevI;
1718 // Examine the instruction that calculates the jumptable entry address.
1719 // Make sure it only defines the base register and kills any uses
1720 // other than the index register.
1721 for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
1722 const MachineOperand &MO = AddrMI->getOperand(k);
1723 if (!MO.isReg() || !MO.getReg())
1725 if (MO.isDef() && MO.getReg() != BaseReg) {
1729 if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
1737 // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction
1738 // that gave us the initial base register definition.
1739 for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
1742 // The instruction should be a tLEApcrel or t2LEApcrelJT; we want
1743 // to delete it as well.
1744 MachineInstr *LeaMI = PrevI;
1745 if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
1746 LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
1747 LeaMI->getOperand(0).getReg() != BaseReg)
1753 unsigned Opc = ByteOk ? ARM::t2TBB : ARM::t2TBH;
1754 MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
1755 .addReg(IdxReg, getKillRegState(IdxRegKill))
1756 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
1757 .addImm(MI->getOperand(JTOpIdx+1).getImm());
1758 // FIXME: Insert an "ALIGN" instruction to ensure the next instruction
1759 // is 2-byte aligned. For now, asm printer will fix it up.
1760 unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
1761 unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
1762 OrigSize += TII->GetInstSizeInBytes(LeaMI);
1763 OrigSize += TII->GetInstSizeInBytes(MI);
1765 AddrMI->eraseFromParent();
1766 LeaMI->eraseFromParent();
1767 MI->eraseFromParent();
1769 int delta = OrigSize - NewSize;
1770 BBSizes[MBB->getNumber()] -= delta;
1771 AdjustBBOffsetsAfter(MBB, -delta);
1781 /// ReorderThumb2JumpTables - Adjust the function's block layout to ensure that
1782 /// jump tables always branch forwards, since that's what tbb and tbh need.
1783 bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) {
1784 bool MadeChange = false;
1786 MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
1787 if (MJTI == 0) return false;
1789 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1790 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1791 MachineInstr *MI = T2JumpTables[i];
1792 const TargetInstrDesc &TID = MI->getDesc();
1793 unsigned NumOps = TID.getNumOperands();
1794 unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
1795 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1796 unsigned JTI = JTOP.getIndex();
1797 assert(JTI < JT.size());
1799 // We prefer if target blocks for the jump table come after the jump
1800 // instruction so we can use TB[BH]. Loop through the target blocks
1801 // and try to adjust them such that that's true.
1802 int JTNumber = MI->getParent()->getNumber();
1803 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1804 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1805 MachineBasicBlock *MBB = JTBBs[j];
1806 int DTNumber = MBB->getNumber();
1808 if (DTNumber < JTNumber) {
1809 // The destination precedes the switch. Try to move the block forward
1810 // so we have a positive offset.
1811 MachineBasicBlock *NewBB =
1812 AdjustJTTargetBlockForward(MBB, MI->getParent());
1814 MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
1823 MachineBasicBlock *ARMConstantIslands::
1824 AdjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB)
1826 MachineFunction &MF = *BB->getParent();
1828 // If the destination block is terminated by an unconditional branch,
1829 // try to move it; otherwise, create a new block following the jump
1830 // table that branches back to the actual target. This is a very simple
1831 // heuristic. FIXME: We can definitely improve it.
1832 MachineBasicBlock *TBB = 0, *FBB = 0;
1833 SmallVector<MachineOperand, 4> Cond;
1834 SmallVector<MachineOperand, 4> CondPrior;
1835 MachineFunction::iterator BBi = BB;
1836 MachineFunction::iterator OldPrior = prior(BBi);
1838 // If the block terminator isn't analyzable, don't try to move the block
1839 bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
1841 // If the block ends in an unconditional branch, move it. The prior block
1842 // has to have an analyzable terminator for us to move this one. Be paranoid
1843 // and make sure we're not trying to move the entry block of the function.
1844 if (!B && Cond.empty() && BB != MF.begin() &&
1845 !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
1846 BB->moveAfter(JTBB);
1847 OldPrior->updateTerminator();
1848 BB->updateTerminator();
1849 // Update numbering to account for the block being moved.
1850 MF.RenumberBlocks();
1855 // Create a new MBB for the code after the jump BB.
1856 MachineBasicBlock *NewBB =
1857 MF.CreateMachineBasicBlock(JTBB->getBasicBlock());
1858 MachineFunction::iterator MBBI = JTBB; ++MBBI;
1859 MF.insert(MBBI, NewBB);
1861 // Add an unconditional branch from NewBB to BB.
1862 // There doesn't seem to be meaningful DebugInfo available; this doesn't
1863 // correspond directly to anything in the source.
1864 assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
1865 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
1867 // Update internal data structures to account for the newly inserted MBB.
1868 MF.RenumberBlocks(NewBB);
1871 NewBB->addSuccessor(BB);
1872 JTBB->removeSuccessor(BB);
1873 JTBB->addSuccessor(NewBB);