1 //===-- ARMConstantIslandPass.cpp - ARM constant islands --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-cp-islands"
18 #include "ARMAddressingModes.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMInstrInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/ADT/Statistic.h"
36 STATISTIC(NumCPEs, "Number of constpool entries");
37 STATISTIC(NumSplit, "Number of uncond branches inserted");
38 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
39 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
40 STATISTIC(NumTBs, "Number of table branches generated");
41 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
42 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
45 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
46 /// requires constant pool entries to be scattered among the instructions
47 /// inside a function. To do this, it completely ignores the normal LLVM
48 /// constant pool; instead, it places constants wherever it feels like with
49 /// special instructions.
51 /// The terminology used in this pass includes:
52 /// Islands - Clumps of constants placed in the function.
53 /// Water - Potential places where an island could be formed.
54 /// CPE - A constant pool entry that has been placed somewhere, which
55 /// tracks a list of users.
56 class VISIBILITY_HIDDEN ARMConstantIslands : public MachineFunctionPass {
57 /// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed
58 /// by MBB Number. The two-byte pads required for Thumb alignment are
59 /// counted as part of the following block (i.e., the offset and size for
60 /// a padded block will both be ==2 mod 4).
61 std::vector<unsigned> BBSizes;
63 /// BBOffsets - the offset of each MBB in bytes, starting from 0.
64 /// The two-byte pads required for Thumb alignment are counted as part of
65 /// the following block.
66 std::vector<unsigned> BBOffsets;
68 /// WaterList - A sorted list of basic blocks where islands could be placed
69 /// (i.e. blocks that don't fall through to the following block, due
70 /// to a return, unreachable, or unconditional branch).
71 std::vector<MachineBasicBlock*> WaterList;
73 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
75 /// CPUser - One user of a constant pool, keeping the machine instruction
76 /// pointer, the constant pool being referenced, and the max displacement
77 /// allowed from the instruction to the CP.
84 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
86 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {}
89 /// CPUsers - Keep track of all of the machine instructions that use various
90 /// constant pools and their max displacement.
91 std::vector<CPUser> CPUsers;
93 /// CPEntry - One per constant pool entry, keeping the machine instruction
94 /// pointer, the constpool index, and the number of CPUser's which
95 /// reference this entry.
100 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
101 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
104 /// CPEntries - Keep track of all of the constant pool entry machine
105 /// instructions. For each original constpool index (i.e. those that
106 /// existed upon entry to this pass), it keeps a vector of entries.
107 /// Original elements are cloned as we go along; the clones are
108 /// put in the vector of the original element, but have distinct CPIs.
109 std::vector<std::vector<CPEntry> > CPEntries;
111 /// ImmBranch - One per immediate branch, keeping the machine instruction
112 /// pointer, conditional or unconditional, the max displacement,
113 /// and (if isCond is true) the corresponding unconditional branch
117 unsigned MaxDisp : 31;
120 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
121 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
124 /// ImmBranches - Keep track of all the immediate branch instructions.
126 std::vector<ImmBranch> ImmBranches;
128 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
130 SmallVector<MachineInstr*, 4> PushPopMIs;
132 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
133 SmallVector<MachineInstr*, 4> T2JumpTables;
135 /// HasFarJump - True if any far jump instruction has been emitted during
136 /// the branch fix up pass.
139 const TargetInstrInfo *TII;
140 const ARMSubtarget *STI;
141 ARMFunctionInfo *AFI;
147 ARMConstantIslands() : MachineFunctionPass(&ID) {}
149 virtual bool runOnMachineFunction(MachineFunction &MF);
151 virtual const char *getPassName() const {
152 return "ARM constant island placement and branch shortening pass";
156 void DoInitialPlacement(MachineFunction &MF,
157 std::vector<MachineInstr*> &CPEMIs);
158 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
159 void InitialFunctionScan(MachineFunction &MF,
160 const std::vector<MachineInstr*> &CPEMIs);
161 MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
162 void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
163 void AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta);
164 bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI);
165 int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
166 bool LookForWater(CPUser&U, unsigned UserOffset,
167 MachineBasicBlock *&NewMBB);
168 MachineBasicBlock* AcceptWater(MachineBasicBlock *WaterBB,
170 void CreateNewWater(unsigned CPUserIndex, unsigned UserOffset,
171 MachineBasicBlock** NewMBB);
172 bool HandleConstantPoolUser(MachineFunction &MF, unsigned CPUserIndex);
173 void RemoveDeadCPEMI(MachineInstr *CPEMI);
174 bool RemoveUnusedCPEntries();
175 bool CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
176 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
177 bool DoDump = false);
178 bool WaterIsInRange(unsigned UserOffset, MachineBasicBlock *Water,
180 bool OffsetIsInRange(unsigned UserOffset, unsigned TrialOffset,
181 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
182 bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
183 bool FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br);
184 bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
185 bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
186 bool UndoLRSpillRestore();
187 bool OptimizeThumb2Instructions(MachineFunction &MF);
188 bool OptimizeThumb2Branches(MachineFunction &MF);
189 bool OptimizeThumb2JumpTables(MachineFunction &MF);
191 unsigned GetOffsetOf(MachineInstr *MI) const;
193 void verify(MachineFunction &MF);
195 char ARMConstantIslands::ID = 0;
198 /// verify - check BBOffsets, BBSizes, alignment of islands
199 void ARMConstantIslands::verify(MachineFunction &MF) {
200 assert(BBOffsets.size() == BBSizes.size());
201 for (unsigned i = 1, e = BBOffsets.size(); i != e; ++i)
202 assert(BBOffsets[i-1]+BBSizes[i-1] == BBOffsets[i]);
206 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
208 MachineBasicBlock *MBB = MBBI;
210 MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
211 unsigned MBBId = MBB->getNumber();
212 assert((BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) ||
213 (BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0));
219 /// print block size and offset information - debugging
220 void ARMConstantIslands::dumpBBs() {
221 for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
222 DEBUG(errs() << "block " << J << " offset " << BBOffsets[J]
223 << " size " << BBSizes[J] << "\n");
227 /// createARMConstantIslandPass - returns an instance of the constpool
229 FunctionPass *llvm::createARMConstantIslandPass() {
230 return new ARMConstantIslands();
233 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
234 MachineConstantPool &MCP = *MF.getConstantPool();
236 TII = MF.getTarget().getInstrInfo();
237 AFI = MF.getInfo<ARMFunctionInfo>();
238 STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
240 isThumb = AFI->isThumbFunction();
241 isThumb1 = AFI->isThumb1OnlyFunction();
242 isThumb2 = AFI->isThumb2Function();
246 // Renumber all of the machine basic blocks in the function, guaranteeing that
247 // the numbers agree with the position of the block in the function.
250 // Thumb1 functions containing constant pools get 4-byte alignment.
251 // This is so we can keep exact track of where the alignment padding goes.
253 // Set default. Thumb1 function is 2-byte aligned, ARM and Thumb2 are 4-byte
255 AFI->setAlign(isThumb1 ? 1U : 2U);
257 // Perform the initial placement of the constant pool entries. To start with,
258 // we put them all at the end of the function.
259 std::vector<MachineInstr*> CPEMIs;
260 if (!MCP.isEmpty()) {
261 DoInitialPlacement(MF, CPEMIs);
266 /// The next UID to take is the first unused one.
267 AFI->initConstPoolEntryUId(CPEMIs.size());
269 // Do the initial scan of the function, building up information about the
270 // sizes of each block, the location of all the water, and finding all of the
271 // constant pool users.
272 InitialFunctionScan(MF, CPEMIs);
275 /// Remove dead constant pool entries.
276 RemoveUnusedCPEntries();
278 // Iteratively place constant pool entries and fix up branches until there
280 bool MadeChange = false;
281 unsigned NoCPIters = 0, NoBRIters = 0;
283 bool CPChange = false;
284 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
285 CPChange |= HandleConstantPoolUser(MF, i);
286 if (CPChange && ++NoCPIters > 30)
287 llvm_unreachable("Constant Island pass failed to converge!");
290 bool BRChange = false;
291 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
292 BRChange |= FixUpImmediateBr(MF, ImmBranches[i]);
293 if (BRChange && ++NoBRIters > 30)
294 llvm_unreachable("Branch Fix Up pass failed to converge!");
297 if (!CPChange && !BRChange)
302 // Shrink 32-bit Thumb2 branch, load, and store instructions.
304 MadeChange |= OptimizeThumb2Instructions(MF);
306 // After a while, this might be made debug-only, but it is not expensive.
309 // If LR has been forced spilled and no far jumps (i.e. BL) has been issued.
310 // Undo the spill / restore of LR if possible.
311 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
312 MadeChange |= UndoLRSpillRestore();
321 T2JumpTables.clear();
326 /// DoInitialPlacement - Perform the initial placement of the constant pool
327 /// entries. To start with, we put them all at the end of the function.
328 void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
329 std::vector<MachineInstr*> &CPEMIs) {
330 // Create the basic block to hold the CPE's.
331 MachineBasicBlock *BB = MF.CreateMachineBasicBlock();
334 // Add all of the constants from the constant pool to the end block, use an
335 // identity mapping of CPI's to CPE's.
336 const std::vector<MachineConstantPoolEntry> &CPs =
337 MF.getConstantPool()->getConstants();
339 const TargetData &TD = *MF.getTarget().getTargetData();
340 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
341 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
342 // Verify that all constant pool entries are a multiple of 4 bytes. If not,
343 // we would have to pad them out or something so that instructions stay
345 assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
346 MachineInstr *CPEMI =
347 BuildMI(BB, DebugLoc::getUnknownLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
348 .addImm(i).addConstantPoolIndex(i).addImm(Size);
349 CPEMIs.push_back(CPEMI);
351 // Add a new CPEntry, but no corresponding CPUser yet.
352 std::vector<CPEntry> CPEs;
353 CPEs.push_back(CPEntry(CPEMI, i));
354 CPEntries.push_back(CPEs);
356 DEBUG(errs() << "Moved CPI#" << i << " to end of function as #" << i
361 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
362 /// into the block immediately after it.
363 static bool BBHasFallthrough(MachineBasicBlock *MBB) {
364 // Get the next machine basic block in the function.
365 MachineFunction::iterator MBBI = MBB;
366 if (next(MBBI) == MBB->getParent()->end()) // Can't fall off end of function.
369 MachineBasicBlock *NextBB = next(MBBI);
370 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
371 E = MBB->succ_end(); I != E; ++I)
378 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
379 /// look up the corresponding CPEntry.
380 ARMConstantIslands::CPEntry
381 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
382 const MachineInstr *CPEMI) {
383 std::vector<CPEntry> &CPEs = CPEntries[CPI];
384 // Number of entries per constpool index should be small, just do a
386 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
387 if (CPEs[i].CPEMI == CPEMI)
393 /// InitialFunctionScan - Do the initial scan of the function, building up
394 /// information about the sizes of each block, the location of all the water,
395 /// and finding all of the constant pool users.
396 void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
397 const std::vector<MachineInstr*> &CPEMIs) {
399 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
401 MachineBasicBlock &MBB = *MBBI;
403 // If this block doesn't fall through into the next MBB, then this is
404 // 'water' that a constant pool island could be placed.
405 if (!BBHasFallthrough(&MBB))
406 WaterList.push_back(&MBB);
408 unsigned MBBSize = 0;
409 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
411 // Add instruction size to MBBSize.
412 MBBSize += TII->GetInstSizeInBytes(I);
414 int Opc = I->getOpcode();
415 if (I->getDesc().isBranch()) {
422 continue; // Ignore other JT branches
424 // A Thumb1 table jump may involve padding; for the offsets to
425 // be right, functions containing these must be 4-byte aligned.
427 if ((Offset+MBBSize)%4 != 0)
428 // FIXME: Add a pseudo ALIGN instruction instead.
429 MBBSize += 2; // padding
430 continue; // Does not get an entry in ImmBranches
432 T2JumpTables.push_back(I);
433 continue; // Does not get an entry in ImmBranches
464 // Record this immediate branch.
465 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
466 ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
469 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
470 PushPopMIs.push_back(I);
472 if (Opc == ARM::CONSTPOOL_ENTRY)
475 // Scan the instructions for constant pool operands.
476 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
477 if (I->getOperand(op).isCPI()) {
478 // We found one. The addressing mode tells us the max displacement
479 // from the PC that this instruction permits.
481 // Basic size info comes from the TSFlags field.
485 bool IsSoImm = false;
489 llvm_unreachable("Unknown addressing mode for CP reference!");
492 // Taking the address of a CP entry.
494 // This takes a SoImm, which is 8 bit immediate rotated. We'll
495 // pretend the maximum offset is 255 * 4. Since each instruction
496 // 4 byte wide, this is always correct. We'llc heck for other
497 // displacements that fits in a SoImm as well.
503 case ARM::t2LEApcrel:
515 Bits = 12; // +-offset_12
522 Scale = 4; // +(offset_8*4)
528 Scale = 4; // +-(offset_8*4)
533 // Remember that this is a user of a CP entry.
534 unsigned CPI = I->getOperand(op).getIndex();
535 MachineInstr *CPEMI = CPEMIs[CPI];
536 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
537 CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
539 // Increment corresponding CPEntry reference count.
540 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
541 assert(CPE && "Cannot find a corresponding CPEntry!");
544 // Instructions can only use one CP entry, don't bother scanning the
545 // rest of the operands.
550 // In thumb mode, if this block is a constpool island, we may need padding
551 // so it's aligned on 4 byte boundary.
554 MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY &&
558 BBSizes.push_back(MBBSize);
559 BBOffsets.push_back(Offset);
564 /// GetOffsetOf - Return the current offset of the specified machine instruction
565 /// from the start of the function. This offset changes as stuff is moved
566 /// around inside the function.
567 unsigned ARMConstantIslands::GetOffsetOf(MachineInstr *MI) const {
568 MachineBasicBlock *MBB = MI->getParent();
570 // The offset is composed of two things: the sum of the sizes of all MBB's
571 // before this instruction's block, and the offset from the start of the block
573 unsigned Offset = BBOffsets[MBB->getNumber()];
575 // If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has
576 // alignment padding, and compensate if so.
578 MI->getOpcode() == ARM::CONSTPOOL_ENTRY &&
582 // Sum instructions before MI in MBB.
583 for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
584 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
585 if (&*I == MI) return Offset;
586 Offset += TII->GetInstSizeInBytes(I);
590 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
592 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
593 const MachineBasicBlock *RHS) {
594 return LHS->getNumber() < RHS->getNumber();
597 /// UpdateForInsertedWaterBlock - When a block is newly inserted into the
598 /// machine function, it upsets all of the block numbers. Renumber the blocks
599 /// and update the arrays that parallel this numbering.
600 void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
601 // Renumber the MBB's to keep them consequtive.
602 NewBB->getParent()->RenumberBlocks(NewBB);
604 // Insert a size into BBSizes to align it properly with the (newly
605 // renumbered) block numbers.
606 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
608 // Likewise for BBOffsets.
609 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
611 // Next, update WaterList. Specifically, we need to add NewMBB as having
612 // available water after it.
614 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
616 WaterList.insert(IP, NewBB);
620 /// Split the basic block containing MI into two blocks, which are joined by
621 /// an unconditional branch. Update datastructures and renumber blocks to
622 /// account for this change and returns the newly created block.
623 MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
624 MachineBasicBlock *OrigBB = MI->getParent();
625 MachineFunction &MF = *OrigBB->getParent();
627 // Create a new MBB for the code after the OrigBB.
628 MachineBasicBlock *NewBB =
629 MF.CreateMachineBasicBlock(OrigBB->getBasicBlock());
630 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
631 MF.insert(MBBI, NewBB);
633 // Splice the instructions starting with MI over to NewBB.
634 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
636 // Add an unconditional branch from OrigBB to NewBB.
637 // Note the new unconditional branch is not being recorded.
638 // There doesn't seem to be meaningful DebugInfo available; this doesn't
639 // correspond to anything in the source.
640 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
641 BuildMI(OrigBB, DebugLoc::getUnknownLoc(), TII->get(Opc)).addMBB(NewBB);
644 // Update the CFG. All succs of OrigBB are now succs of NewBB.
645 while (!OrigBB->succ_empty()) {
646 MachineBasicBlock *Succ = *OrigBB->succ_begin();
647 OrigBB->removeSuccessor(Succ);
648 NewBB->addSuccessor(Succ);
650 // This pass should be run after register allocation, so there should be no
651 // PHI nodes to update.
652 assert((Succ->empty() || Succ->begin()->getOpcode() != TargetInstrInfo::PHI)
653 && "PHI nodes should be eliminated by now!");
656 // OrigBB branches to NewBB.
657 OrigBB->addSuccessor(NewBB);
659 // Update internal data structures to account for the newly inserted MBB.
660 // This is almost the same as UpdateForInsertedWaterBlock, except that
661 // the Water goes after OrigBB, not NewBB.
662 MF.RenumberBlocks(NewBB);
664 // Insert a size into BBSizes to align it properly with the (newly
665 // renumbered) block numbers.
666 BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
668 // Likewise for BBOffsets.
669 BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
671 // Next, update WaterList. Specifically, we need to add OrigMBB as having
672 // available water after it (but not if it's already there, which happens
673 // when splitting before a conditional branch that is followed by an
674 // unconditional branch - in that case we want to insert NewBB).
676 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
678 MachineBasicBlock* WaterBB = *IP;
679 if (WaterBB == OrigBB)
680 WaterList.insert(next(IP), NewBB);
682 WaterList.insert(IP, OrigBB);
684 // Figure out how large the first NewMBB is. (It cannot
685 // contain a constpool_entry or tablejump.)
686 unsigned NewBBSize = 0;
687 for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
689 NewBBSize += TII->GetInstSizeInBytes(I);
691 unsigned OrigBBI = OrigBB->getNumber();
692 unsigned NewBBI = NewBB->getNumber();
693 // Set the size of NewBB in BBSizes.
694 BBSizes[NewBBI] = NewBBSize;
696 // We removed instructions from UserMBB, subtract that off from its size.
697 // Add 2 or 4 to the block to count the unconditional branch we added to it.
698 int delta = isThumb1 ? 2 : 4;
699 BBSizes[OrigBBI] -= NewBBSize - delta;
701 // ...and adjust BBOffsets for NewBB accordingly.
702 BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI];
704 // All BBOffsets following these blocks must be modified.
705 AdjustBBOffsetsAfter(NewBB, delta);
710 /// OffsetIsInRange - Checks whether UserOffset (the location of a constant pool
711 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
712 /// constant pool entry).
713 bool ARMConstantIslands::OffsetIsInRange(unsigned UserOffset,
714 unsigned TrialOffset, unsigned MaxDisp,
715 bool NegativeOK, bool IsSoImm) {
716 // On Thumb offsets==2 mod 4 are rounded down by the hardware for
717 // purposes of the displacement computation; compensate for that here.
718 // Effectively, the valid range of displacements is 2 bytes smaller for such
720 unsigned TotalAdj = 0;
721 if (isThumb && UserOffset%4 !=0) {
725 // CPEs will be rounded up to a multiple of 4.
726 if (isThumb && TrialOffset%4 != 0) {
731 // In Thumb2 mode, later branch adjustments can shift instructions up and
732 // cause alignment change. In the worst case scenario this can cause the
733 // user's effective address to be subtracted by 2 and the CPE's address to
735 if (isThumb2 && TotalAdj != 4)
736 MaxDisp -= (4 - TotalAdj);
738 if (UserOffset <= TrialOffset) {
739 // User before the Trial.
740 if (TrialOffset - UserOffset <= MaxDisp)
742 // FIXME: Make use full range of soimm values.
743 } else if (NegativeOK) {
744 if (UserOffset - TrialOffset <= MaxDisp)
746 // FIXME: Make use full range of soimm values.
751 /// WaterIsInRange - Returns true if a CPE placed after the specified
752 /// Water (a basic block) will be in range for the specific MI.
754 bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset,
755 MachineBasicBlock* Water, CPUser &U) {
756 unsigned MaxDisp = U.MaxDisp;
757 unsigned CPEOffset = BBOffsets[Water->getNumber()] +
758 BBSizes[Water->getNumber()];
760 // If the CPE is to be inserted before the instruction, that will raise
761 // the offset of the instruction. (Currently applies only to ARM, so
762 // no alignment compensation attempted here.)
763 if (CPEOffset < UserOffset)
764 UserOffset += U.CPEMI->getOperand(2).getImm();
766 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, U.NegOk, U.IsSoImm);
769 /// CPEIsInRange - Returns true if the distance between specific MI and
770 /// specific ConstPool entry instruction can fit in MI's displacement field.
771 bool ARMConstantIslands::CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
772 MachineInstr *CPEMI, unsigned MaxDisp,
773 bool NegOk, bool DoDump) {
774 unsigned CPEOffset = GetOffsetOf(CPEMI);
775 assert(CPEOffset%4 == 0 && "Misaligned CPE");
778 DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
779 << " max delta=" << MaxDisp
780 << " insn address=" << UserOffset
781 << " CPE address=" << CPEOffset
782 << " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI);
785 return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
789 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
790 /// unconditionally branches to its only successor.
791 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
792 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
795 MachineBasicBlock *Succ = *MBB->succ_begin();
796 MachineBasicBlock *Pred = *MBB->pred_begin();
797 MachineInstr *PredMI = &Pred->back();
798 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
799 || PredMI->getOpcode() == ARM::t2B)
800 return PredMI->getOperand(0).getMBB() == Succ;
805 void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB,
807 MachineFunction::iterator MBBI = BB; MBBI = next(MBBI);
808 for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
810 BBOffsets[i] += delta;
811 // If some existing blocks have padding, adjust the padding as needed, a
812 // bit tricky. delta can be negative so don't use % on that.
815 MachineBasicBlock *MBB = MBBI;
817 // Constant pool entries require padding.
818 if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
819 unsigned OldOffset = BBOffsets[i] - delta;
820 if ((OldOffset%4) == 0 && (BBOffsets[i]%4) != 0) {
824 } else if ((OldOffset%4) != 0 && (BBOffsets[i]%4) == 0) {
825 // remove existing padding
830 // Thumb1 jump tables require padding. They should be at the end;
831 // following unconditional branches are removed by AnalyzeBranch.
832 MachineInstr *ThumbJTMI = prior(MBB->end());
833 if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
834 unsigned NewMIOffset = GetOffsetOf(ThumbJTMI);
835 unsigned OldMIOffset = NewMIOffset - delta;
836 if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
837 // remove existing padding
840 } else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
853 /// DecrementOldEntry - find the constant pool entry with index CPI
854 /// and instruction CPEMI, and decrement its refcount. If the refcount
855 /// becomes 0 remove the entry and instruction. Returns true if we removed
856 /// the entry, false if we didn't.
858 bool ARMConstantIslands::DecrementOldEntry(unsigned CPI, MachineInstr *CPEMI) {
859 // Find the old entry. Eliminate it if it is no longer used.
860 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
861 assert(CPE && "Unexpected!");
862 if (--CPE->RefCount == 0) {
863 RemoveDeadCPEMI(CPEMI);
871 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
872 /// if not, see if an in-range clone of the CPE is in range, and if so,
873 /// change the data structures so the user references the clone. Returns:
874 /// 0 = no existing entry found
875 /// 1 = entry found, and there were no code insertions or deletions
876 /// 2 = entry found, and there were code insertions or deletions
877 int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
879 MachineInstr *UserMI = U.MI;
880 MachineInstr *CPEMI = U.CPEMI;
882 // Check to see if the CPE is already in-range.
883 if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, U.NegOk, true)) {
884 DEBUG(errs() << "In range\n");
888 // No. Look for previously created clones of the CPE that are in range.
889 unsigned CPI = CPEMI->getOperand(1).getIndex();
890 std::vector<CPEntry> &CPEs = CPEntries[CPI];
891 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
892 // We already tried this one
893 if (CPEs[i].CPEMI == CPEMI)
895 // Removing CPEs can leave empty entries, skip
896 if (CPEs[i].CPEMI == NULL)
898 if (CPEIsInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.MaxDisp, U.NegOk)) {
899 DEBUG(errs() << "Replacing CPE#" << CPI << " with CPE#"
900 << CPEs[i].CPI << "\n");
901 // Point the CPUser node to the replacement
902 U.CPEMI = CPEs[i].CPEMI;
903 // Change the CPI in the instruction operand to refer to the clone.
904 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
905 if (UserMI->getOperand(j).isCPI()) {
906 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
909 // Adjust the refcount of the clone...
911 // ...and the original. If we didn't remove the old entry, none of the
912 // addresses changed, so we don't need another pass.
913 return DecrementOldEntry(CPI, CPEMI) ? 2 : 1;
919 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
920 /// the specific unconditional branch instruction.
921 static inline unsigned getUnconditionalBrDisp(int Opc) {
924 return ((1<<10)-1)*2;
926 return ((1<<23)-1)*2;
931 return ((1<<23)-1)*4;
934 /// AcceptWater - Small amount of common code factored out of the following.
936 MachineBasicBlock* ARMConstantIslands::AcceptWater(MachineBasicBlock *WaterBB,
938 DEBUG(errs() << "found water in range\n");
939 // Remove the original WaterList entry; we want subsequent
940 // insertions in this vicinity to go after the one we're
941 // about to insert. This considerably reduces the number
942 // of times we have to move the same CPE more than once.
944 // CPE goes before following block (NewMBB).
945 return next(MachineFunction::iterator(WaterBB));
948 /// LookForWater - look for an existing entry in the WaterList in which
949 /// we can place the CPE referenced from U so it's within range of U's MI.
950 /// Returns true if found, false if not. If it returns true, NewMBB
951 /// is set to the WaterList entry.
952 /// For ARM, we prefer the water that's farthest away. For Thumb, prefer
953 /// water that will not introduce padding to water that will; within each
954 /// group, prefer the water that's farthest away.
955 bool ARMConstantIslands::LookForWater(CPUser &U, unsigned UserOffset,
956 MachineBasicBlock *&NewMBB) {
957 water_iterator IPThatWouldPad;
958 MachineBasicBlock* WaterBBThatWouldPad = NULL;
959 if (WaterList.empty())
962 for (water_iterator IP = prior(WaterList.end()),
963 B = WaterList.begin();; --IP) {
964 MachineBasicBlock* WaterBB = *IP;
965 if (WaterIsInRange(UserOffset, WaterBB, U)) {
966 unsigned WBBId = WaterBB->getNumber();
968 (BBOffsets[WBBId] + BBSizes[WBBId])%4 != 0) {
969 // This is valid Water, but would introduce padding. Remember
970 // it in case we don't find any Water that doesn't do this.
971 if (!WaterBBThatWouldPad) {
972 WaterBBThatWouldPad = WaterBB;
976 NewMBB = AcceptWater(WaterBB, IP);
983 if (isThumb && WaterBBThatWouldPad) {
984 NewMBB = AcceptWater(WaterBBThatWouldPad, IPThatWouldPad);
990 /// CreateNewWater - No existing WaterList entry will work for
991 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
992 /// block is used if in range, and the conditional branch munged so control
993 /// flow is correct. Otherwise the block is split to create a hole with an
994 /// unconditional branch around it. In either case *NewMBB is set to a
995 /// block following which the new island can be inserted (the WaterList
996 /// is not adjusted).
998 void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
999 unsigned UserOffset, MachineBasicBlock** NewMBB) {
1000 CPUser &U = CPUsers[CPUserIndex];
1001 MachineInstr *UserMI = U.MI;
1002 MachineInstr *CPEMI = U.CPEMI;
1003 MachineBasicBlock *UserMBB = UserMI->getParent();
1004 unsigned OffsetOfNextBlock = BBOffsets[UserMBB->getNumber()] +
1005 BBSizes[UserMBB->getNumber()];
1006 assert(OffsetOfNextBlock== BBOffsets[UserMBB->getNumber()+1]);
1008 // If the use is at the end of the block, or the end of the block
1009 // is within range, make new water there. (The addition below is
1010 // for the unconditional branch we will be adding: 4 bytes on ARM + Thumb2,
1011 // 2 on Thumb1. Possible Thumb1 alignment padding is allowed for
1012 // inside OffsetIsInRange.
1013 // If the block ends in an unconditional branch already, it is water,
1014 // and is known to be out of range, so we'll always be adding a branch.)
1015 if (&UserMBB->back() == UserMI ||
1016 OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4),
1017 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1018 DEBUG(errs() << "Split at end of block\n");
1019 if (&UserMBB->back() == UserMI)
1020 assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
1021 *NewMBB = next(MachineFunction::iterator(UserMBB));
1022 // Add an unconditional branch from UserMBB to fallthrough block.
1023 // Record it for branch lengthening; this new branch will not get out of
1024 // range, but if the preceding conditional branch is out of range, the
1025 // targets will be exchanged, and the altered branch may be out of
1026 // range, so the machinery has to know about it.
1027 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1028 BuildMI(UserMBB, DebugLoc::getUnknownLoc(),
1029 TII->get(UncondBr)).addMBB(*NewMBB);
1030 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1031 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1032 MaxDisp, false, UncondBr));
1033 int delta = isThumb1 ? 2 : 4;
1034 BBSizes[UserMBB->getNumber()] += delta;
1035 AdjustBBOffsetsAfter(UserMBB, delta);
1037 // What a big block. Find a place within the block to split it.
1038 // This is a little tricky on Thumb1 since instructions are 2 bytes
1039 // and constant pool entries are 4 bytes: if instruction I references
1040 // island CPE, and instruction I+1 references CPE', it will
1041 // not work well to put CPE as far forward as possible, since then
1042 // CPE' cannot immediately follow it (that location is 2 bytes
1043 // farther away from I+1 than CPE was from I) and we'd need to create
1044 // a new island. So, we make a first guess, then walk through the
1045 // instructions between the one currently being looked at and the
1046 // possible insertion point, and make sure any other instructions
1047 // that reference CPEs will be able to use the same island area;
1048 // if not, we back up the insertion point.
1050 // The 4 in the following is for the unconditional branch we'll be
1051 // inserting (allows for long branch on Thumb1). Alignment of the
1052 // island is handled inside OffsetIsInRange.
1053 unsigned BaseInsertOffset = UserOffset + U.MaxDisp -4;
1054 // This could point off the end of the block if we've already got
1055 // constant pool entries following this block; only the last one is
1056 // in the water list. Back past any possible branches (allow for a
1057 // conditional and a maximally long unconditional).
1058 if (BaseInsertOffset >= BBOffsets[UserMBB->getNumber()+1])
1059 BaseInsertOffset = BBOffsets[UserMBB->getNumber()+1] -
1061 unsigned EndInsertOffset = BaseInsertOffset +
1062 CPEMI->getOperand(2).getImm();
1063 MachineBasicBlock::iterator MI = UserMI;
1065 unsigned CPUIndex = CPUserIndex+1;
1066 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
1067 Offset < BaseInsertOffset;
1068 Offset += TII->GetInstSizeInBytes(MI),
1070 if (CPUIndex < CPUsers.size() && CPUsers[CPUIndex].MI == MI) {
1071 CPUser &U = CPUsers[CPUIndex];
1072 if (!OffsetIsInRange(Offset, EndInsertOffset,
1073 U.MaxDisp, U.NegOk, U.IsSoImm)) {
1074 BaseInsertOffset -= (isThumb1 ? 2 : 4);
1075 EndInsertOffset -= (isThumb1 ? 2 : 4);
1077 // This is overly conservative, as we don't account for CPEMIs
1078 // being reused within the block, but it doesn't matter much.
1079 EndInsertOffset += CPUsers[CPUIndex].CPEMI->getOperand(2).getImm();
1083 DEBUG(errs() << "Split in middle of big block\n");
1084 *NewMBB = SplitBlockBeforeInstr(prior(MI));
1088 /// HandleConstantPoolUser - Analyze the specified user, checking to see if it
1089 /// is out-of-range. If so, pick up the constant pool value and move it some
1090 /// place in-range. Return true if we changed any addresses (thus must run
1091 /// another pass of branch lengthening), false otherwise.
1092 bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
1093 unsigned CPUserIndex) {
1094 CPUser &U = CPUsers[CPUserIndex];
1095 MachineInstr *UserMI = U.MI;
1096 MachineInstr *CPEMI = U.CPEMI;
1097 unsigned CPI = CPEMI->getOperand(1).getIndex();
1098 unsigned Size = CPEMI->getOperand(2).getImm();
1099 MachineBasicBlock *NewMBB;
1100 // Compute this only once, it's expensive. The 4 or 8 is the value the
1101 // hardware keeps in the PC.
1102 unsigned UserOffset = GetOffsetOf(UserMI) + (isThumb ? 4 : 8);
1104 // See if the current entry is within range, or there is a clone of it
1106 int result = LookForExistingCPEntry(U, UserOffset);
1107 if (result==1) return false;
1108 else if (result==2) return true;
1110 // No existing clone of this CPE is within range.
1111 // We will be generating a new clone. Get a UID for it.
1112 unsigned ID = AFI->createConstPoolEntryUId();
1114 // Look for water where we can place this CPE. We look for the farthest one
1115 // away that will work. Forward references only for now (although later
1116 // we might find some that are backwards).
1118 if (!LookForWater(U, UserOffset, NewMBB)) {
1120 DEBUG(errs() << "No water found\n");
1121 CreateNewWater(CPUserIndex, UserOffset, &NewMBB);
1124 // Okay, we know we can put an island before NewMBB now, do it!
1125 MachineBasicBlock *NewIsland = MF.CreateMachineBasicBlock();
1126 MF.insert(NewMBB, NewIsland);
1128 // Update internal data structures to account for the newly inserted MBB.
1129 UpdateForInsertedWaterBlock(NewIsland);
1131 // Decrement the old entry, and remove it if refcount becomes 0.
1132 DecrementOldEntry(CPI, CPEMI);
1134 // Now that we have an island to add the CPE to, clone the original CPE and
1135 // add it to the island.
1136 U.CPEMI = BuildMI(NewIsland, DebugLoc::getUnknownLoc(),
1137 TII->get(ARM::CONSTPOOL_ENTRY))
1138 .addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
1139 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1142 BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()];
1143 // Compensate for .align 2 in thumb mode.
1144 if (isThumb && BBOffsets[NewIsland->getNumber()]%4 != 0)
1146 // Increase the size of the island block to account for the new entry.
1147 BBSizes[NewIsland->getNumber()] += Size;
1148 AdjustBBOffsetsAfter(NewIsland, Size);
1150 // Finally, change the CPI in the instruction operand to be ID.
1151 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1152 if (UserMI->getOperand(i).isCPI()) {
1153 UserMI->getOperand(i).setIndex(ID);
1157 DEBUG(errs() << " Moved CPE to #" << ID << " CPI=" << CPI
1158 << '\t' << *UserMI);
1163 /// RemoveDeadCPEMI - Remove a dead constant pool entry instruction. Update
1164 /// sizes and offsets of impacted basic blocks.
1165 void ARMConstantIslands::RemoveDeadCPEMI(MachineInstr *CPEMI) {
1166 MachineBasicBlock *CPEBB = CPEMI->getParent();
1167 unsigned Size = CPEMI->getOperand(2).getImm();
1168 CPEMI->eraseFromParent();
1169 BBSizes[CPEBB->getNumber()] -= Size;
1170 // All succeeding offsets have the current size value added in, fix this.
1171 if (CPEBB->empty()) {
1172 // In thumb1 mode, the size of island may be padded by two to compensate for
1173 // the alignment requirement. Then it will now be 2 when the block is
1174 // empty, so fix this.
1175 // All succeeding offsets have the current size value added in, fix this.
1176 if (BBSizes[CPEBB->getNumber()] != 0) {
1177 Size += BBSizes[CPEBB->getNumber()];
1178 BBSizes[CPEBB->getNumber()] = 0;
1181 AdjustBBOffsetsAfter(CPEBB, -Size);
1182 // An island has only one predecessor BB and one successor BB. Check if
1183 // this BB's predecessor jumps directly to this BB's successor. This
1184 // shouldn't happen currently.
1185 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1186 // FIXME: remove the empty blocks after all the work is done?
1189 /// RemoveUnusedCPEntries - Remove constant pool entries whose refcounts
1191 bool ARMConstantIslands::RemoveUnusedCPEntries() {
1192 unsigned MadeChange = false;
1193 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1194 std::vector<CPEntry> &CPEs = CPEntries[i];
1195 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1196 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1197 RemoveDeadCPEMI(CPEs[j].CPEMI);
1198 CPEs[j].CPEMI = NULL;
1206 /// BBIsInRange - Returns true if the distance between specific MI and
1207 /// specific BB can fit in MI's displacement field.
1208 bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1210 unsigned PCAdj = isThumb ? 4 : 8;
1211 unsigned BrOffset = GetOffsetOf(MI) + PCAdj;
1212 unsigned DestOffset = BBOffsets[DestBB->getNumber()];
1214 DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber()
1215 << " from BB#" << MI->getParent()->getNumber()
1216 << " max delta=" << MaxDisp
1217 << " from " << GetOffsetOf(MI) << " to " << DestOffset
1218 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1220 if (BrOffset <= DestOffset) {
1221 // Branch before the Dest.
1222 if (DestOffset-BrOffset <= MaxDisp)
1225 if (BrOffset-DestOffset <= MaxDisp)
1231 /// FixUpImmediateBr - Fix up an immediate branch whose destination is too far
1232 /// away to fit in its displacement field.
1233 bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br) {
1234 MachineInstr *MI = Br.MI;
1235 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1237 // Check to see if the DestBB is already in-range.
1238 if (BBIsInRange(MI, DestBB, Br.MaxDisp))
1242 return FixUpUnconditionalBr(MF, Br);
1243 return FixUpConditionalBr(MF, Br);
1246 /// FixUpUnconditionalBr - Fix up an unconditional branch whose destination is
1247 /// too far away to fit in its displacement field. If the LR register has been
1248 /// spilled in the epilogue, then we can use BL to implement a far jump.
1249 /// Otherwise, add an intermediate branch instruction to a branch.
1251 ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
1252 MachineInstr *MI = Br.MI;
1253 MachineBasicBlock *MBB = MI->getParent();
1255 llvm_unreachable("FixUpUnconditionalBr is Thumb1 only!");
1257 // Use BL to implement far jump.
1258 Br.MaxDisp = (1 << 21) * 2;
1259 MI->setDesc(TII->get(ARM::tBfar));
1260 BBSizes[MBB->getNumber()] += 2;
1261 AdjustBBOffsetsAfter(MBB, 2);
1265 DEBUG(errs() << " Changed B to long jump " << *MI);
1270 /// FixUpConditionalBr - Fix up a conditional branch whose destination is too
1271 /// far away to fit in its displacement field. It is converted to an inverse
1272 /// conditional branch + an unconditional branch to the destination.
1274 ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
1275 MachineInstr *MI = Br.MI;
1276 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1278 // Add an unconditional branch to the destination and invert the branch
1279 // condition to jump over it:
1285 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1286 CC = ARMCC::getOppositeCondition(CC);
1287 unsigned CCReg = MI->getOperand(2).getReg();
1289 // If the branch is at the end of its MBB and that has a fall-through block,
1290 // direct the updated conditional branch to the fall-through block. Otherwise,
1291 // split the MBB before the next instruction.
1292 MachineBasicBlock *MBB = MI->getParent();
1293 MachineInstr *BMI = &MBB->back();
1294 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1298 if (next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
1299 BMI->getOpcode() == Br.UncondBr) {
1300 // Last MI in the BB is an unconditional branch. Can we simply invert the
1301 // condition and swap destinations:
1307 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1308 if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
1309 DEBUG(errs() << " Invert Bcc condition and swap its destination with "
1311 BMI->getOperand(0).setMBB(DestBB);
1312 MI->getOperand(0).setMBB(NewDest);
1313 MI->getOperand(1).setImm(CC);
1320 SplitBlockBeforeInstr(MI);
1321 // No need for the branch to the next block. We're adding an unconditional
1322 // branch to the destination.
1323 int delta = TII->GetInstSizeInBytes(&MBB->back());
1324 BBSizes[MBB->getNumber()] -= delta;
1325 MachineBasicBlock* SplitBB = next(MachineFunction::iterator(MBB));
1326 AdjustBBOffsetsAfter(SplitBB, -delta);
1327 MBB->back().eraseFromParent();
1328 // BBOffsets[SplitBB] is wrong temporarily, fixed below
1330 MachineBasicBlock *NextBB = next(MachineFunction::iterator(MBB));
1332 DEBUG(errs() << " Insert B to BB#" << DestBB->getNumber()
1333 << " also invert condition and change dest. to BB#"
1334 << NextBB->getNumber() << "\n");
1336 // Insert a new conditional branch and a new unconditional branch.
1337 // Also update the ImmBranch as well as adding a new entry for the new branch.
1338 BuildMI(MBB, DebugLoc::getUnknownLoc(),
1339 TII->get(MI->getOpcode()))
1340 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1341 Br.MI = &MBB->back();
1342 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1343 BuildMI(MBB, DebugLoc::getUnknownLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1344 BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
1345 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1346 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1348 // Remove the old conditional branch. It may or may not still be in MBB.
1349 BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI);
1350 MI->eraseFromParent();
1352 // The net size change is an addition of one unconditional branch.
1353 int delta = TII->GetInstSizeInBytes(&MBB->back());
1354 AdjustBBOffsetsAfter(MBB, delta);
1358 /// UndoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1359 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1360 /// to do this if tBfar is not used.
1361 bool ARMConstantIslands::UndoLRSpillRestore() {
1362 bool MadeChange = false;
1363 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1364 MachineInstr *MI = PushPopMIs[i];
1365 // First two operands are predicates, the third is a zero since there
1367 if (MI->getOpcode() == ARM::tPOP_RET &&
1368 MI->getOperand(3).getReg() == ARM::PC &&
1369 MI->getNumExplicitOperands() == 4) {
1370 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
1371 MI->eraseFromParent();
1378 bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
1379 bool MadeChange = false;
1381 // Shrink ADR and LDR from constantpool.
1382 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1383 CPUser &U = CPUsers[i];
1384 unsigned Opcode = U.MI->getOpcode();
1385 unsigned NewOpc = 0;
1390 case ARM::t2LEApcrel:
1391 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1392 NewOpc = ARM::tLEApcrel;
1398 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1399 NewOpc = ARM::tLDRpci;
1409 unsigned UserOffset = GetOffsetOf(U.MI) + 4;
1410 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1411 // FIXME: Check if offset is multiple of scale if scale is not 4.
1412 if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1413 U.MI->setDesc(TII->get(NewOpc));
1414 MachineBasicBlock *MBB = U.MI->getParent();
1415 BBSizes[MBB->getNumber()] -= 2;
1416 AdjustBBOffsetsAfter(MBB, -2);
1422 MadeChange |= OptimizeThumb2Branches(MF);
1423 MadeChange |= OptimizeThumb2JumpTables(MF);
1427 bool ARMConstantIslands::OptimizeThumb2Branches(MachineFunction &MF) {
1428 bool MadeChange = false;
1430 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
1431 ImmBranch &Br = ImmBranches[i];
1432 unsigned Opcode = Br.MI->getOpcode();
1433 unsigned NewOpc = 0;
1452 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1453 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1454 if (BBIsInRange(Br.MI, DestBB, MaxOffs)) {
1455 Br.MI->setDesc(TII->get(NewOpc));
1456 MachineBasicBlock *MBB = Br.MI->getParent();
1457 BBSizes[MBB->getNumber()] -= 2;
1458 AdjustBBOffsetsAfter(MBB, -2);
1468 /// OptimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
1469 /// jumptables when it's possible.
1470 bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
1471 bool MadeChange = false;
1473 // FIXME: After the tables are shrunk, can we get rid some of the
1474 // constantpool tables?
1475 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
1476 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1477 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
1478 MachineInstr *MI = T2JumpTables[i];
1479 const TargetInstrDesc &TID = MI->getDesc();
1480 unsigned NumOps = TID.getNumOperands();
1481 unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
1482 MachineOperand JTOP = MI->getOperand(JTOpIdx);
1483 unsigned JTI = JTOP.getIndex();
1484 assert(JTI < JT.size());
1487 bool HalfWordOk = true;
1488 unsigned JTOffset = GetOffsetOf(MI) + 4;
1489 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1490 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
1491 MachineBasicBlock *MBB = JTBBs[j];
1492 unsigned DstOffset = BBOffsets[MBB->getNumber()];
1493 // Negative offset is not ok. FIXME: We should change BB layout to make
1494 // sure all the branches are forward.
1495 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
1497 unsigned TBHLimit = ((1<<16)-1)*2;
1498 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
1500 if (!ByteOk && !HalfWordOk)
1504 if (ByteOk || HalfWordOk) {
1505 MachineBasicBlock *MBB = MI->getParent();
1506 unsigned BaseReg = MI->getOperand(0).getReg();
1507 bool BaseRegKill = MI->getOperand(0).isKill();
1510 unsigned IdxReg = MI->getOperand(1).getReg();
1511 bool IdxRegKill = MI->getOperand(1).isKill();
1512 MachineBasicBlock::iterator PrevI = MI;
1513 if (PrevI == MBB->begin())
1516 MachineInstr *AddrMI = --PrevI;
1518 // Examine the instruction that calculate the jumptable entry address.
1519 // If it's not the one just before the t2BR_JT, we won't delete it, then
1520 // it's not worth doing the optimization.
1521 for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
1522 const MachineOperand &MO = AddrMI->getOperand(k);
1523 if (!MO.isReg() || !MO.getReg())
1525 if (MO.isDef() && MO.getReg() != BaseReg) {
1529 if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
1537 // The previous instruction should be a tLEApcrel or t2LEApcrelJT, we want
1538 // to delete it as well.
1539 MachineInstr *LeaMI = --PrevI;
1540 if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
1541 LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
1542 LeaMI->getOperand(0).getReg() != BaseReg)
1548 unsigned Opc = ByteOk ? ARM::t2TBB : ARM::t2TBH;
1549 MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
1550 .addReg(IdxReg, getKillRegState(IdxRegKill))
1551 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
1552 .addImm(MI->getOperand(JTOpIdx+1).getImm());
1553 // FIXME: Insert an "ALIGN" instruction to ensure the next instruction
1554 // is 2-byte aligned. For now, asm printer will fix it up.
1555 unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
1556 unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
1557 OrigSize += TII->GetInstSizeInBytes(LeaMI);
1558 OrigSize += TII->GetInstSizeInBytes(MI);
1560 AddrMI->eraseFromParent();
1561 LeaMI->eraseFromParent();
1562 MI->eraseFromParent();
1564 int delta = OrigSize - NewSize;
1565 BBSizes[MBB->getNumber()] -= delta;
1566 AdjustBBOffsetsAfter(MBB, -delta);